CN114597251A - Shielding gate VDMOS (vertical double-diffused metal oxide semiconductor) with reinforced total dose radiation resistance - Google Patents
Shielding gate VDMOS (vertical double-diffused metal oxide semiconductor) with reinforced total dose radiation resistance Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 161
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 44
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- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000002955 isolation Methods 0.000 claims abstract description 11
- 229920005591 polysilicon Polymers 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
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- 238000005510 radiation hardening Methods 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
Abstract
The invention provides a shielding grid VDMOS (vertical double-diffused metal oxide semiconductor) resisting total dose radiation reinforcement, which comprises: the semiconductor device comprises drain electrode metal, a heavily doped first conduction type semiconductor substrate, a first layer of first conduction type semiconductor drift region, a second conduction type semiconductor well region, a heavily doped second conduction type semiconductor ohmic contact region, a heavily doped first conduction type semiconductor source region, a shielding grid polycrystalline silicon electrode, a shielding grid dielectric layer, an isolation dielectric layer, a grid source-source dielectric layer and source electrode metal. The invention provides the non-uniform doping distribution of the drift region of the shield grid VDMOS, which can ensure that the longitudinal electric field of the drift region is uniformly distributed after a device is radiated by a certain total dose, and the breakdown voltage is the maximum value at the moment. Thus, when the device is subjected to a total dose of radiation, the breakdown voltage changes from increasing to decreasing as the radiation dose increases, such that a greater radiation dose is required to degrade the device to failure.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a shielding grid VDMOS (vertical double-diffused metal oxide semiconductor) with total dose radiation hardening resistance.
Background
In contrast to conventional trench-gate VDMOS, shield-gate VDMOS (sgt VDMOS) has a polysilicon shield gate connected to the source under the gate polysilicon in the trench. The shielding grid not only serves as an in-vivo field plate to modulate the longitudinal electric field of the drift region, so that the breakdown voltage of the device is increased, but also most of the grid-drain capacitance CgdIs converted into a gate-source capacitance CgsResulting in a higher switching speed of the device. However, the more uniform electric field distribution of the drift region also makes the breakdown voltage degradation of the shielded gate VDMOS more severe at the total dose irradiation. When the shielding grid VDMOS is radiated by total dose, fixed positive charges and interface state charges are formed at the semiconductor interface of the internal oxide layer of the shielding grid VDMOS, and the net charge quantity of the fixed positive charges and the interface state charges is positive. The positive charges existing in the oxide layer on the side wall of the shielding grid change the distribution of the longitudinal electric field of the drift region, the electric field at the bottom of the trench is reduced, and P isbase-NdriftThe junction electric field is enhanced, resulting in a decrease in breakdown voltage. To limit this degradation process, the shield gate VDMOS needs to be designed to be radiation-hardened against the total dose.
Disclosure of Invention
In view of the degradation phenomenon existing in the total dose radiation in the prior art, the invention provides a shielding grid VDMOS structure which can inhibit the breakdown voltage degradation in the total dose radiation process. The structure adopts the non-uniform doping distribution of the drift region, so that the longitudinal electric field of the drift region is uniformly distributed after the device is irradiated by a certain total dose, the breakdown voltage is the maximum value, when the radiation dose is less than the value, the breakdown voltage is less than the maximum value, and when the radiation dose exceeds the value, the breakdown voltage is also less than the maximum value. Therefore, when the device proposed by the present invention is subjected to a total dose of radiation, the breakdown voltage changes from increasing to decreasing as the radiation dose increases, which delays the failure of the device, so that a larger radiation dose is required to degrade the device to failure.
In order to achieve the above purpose, the invention provides a shielded gate VDMOS device with a non-uniformly doped drift region, which has a structure as shown in fig. 1, wherein the drift region is divided into two parts, a first layer of drift region below and a second layer of drift region above, the doping concentration of the first layer of drift region increases linearly from top to bottom, and the second layer of drift region is uniformly doped with low concentration. By adopting the doping distribution, the longitudinal electric field of the drift region can be uniformly distributed when a certain amount of positive charges exist in the side wall oxide layer of the shielding grid.
The technical scheme adopted by the invention is as follows:
a shielding grid VDMOS (vertical double-diffused metal oxide semiconductor) with reinforced total dose radiation resistance comprises a drain metal 1, a heavily doped first conduction type semiconductor substrate 2, a first layer of first conduction type semiconductor drift region 3, a second layer of first conduction type semiconductor drift region 4, a second conduction type semiconductor well region 5, a heavily doped second conduction type semiconductor ohmic contact region 6, a heavily doped first conduction type semiconductor source region 7, a shielding grid polysilicon electrode 8, a grid polysilicon electrode 9, a shielding grid dielectric layer 10, an isolation dielectric layer 11, a grid dielectric layer 12, an inter-grid-source dielectric layer 13 and a source metal 14;
the heavily doped first conduction type semiconductor substrate 2 is positioned above the drain metal 1, the first layer of first conduction type semiconductor drift region 3 is positioned above the heavily doped first conduction type semiconductor substrate 2, and the second layer of first conduction type semiconductor drift region 4 is positioned above the first layer of first conduction type semiconductor drift region 3; the second layer of drift region 4 of the first conductivity type semiconductor has a doping concentration lower than 1e16cm-3The doping concentration of the first layer of the first conductive type semiconductor drift region 3 is distributed in a linear increasing manner from top to bottom; the doping concentration of the first layer of first conduction type semiconductor drift region 3 at the junction with the second layer of first conduction type semiconductor drift region 4 is the same as that of the second layer of first conduction type semiconductor drift region 4; the second conductive type semiconductor well region 5 is positioned above the second layer first conductive type semiconductor drift region 4, the heavily doped second conductive type semiconductor ohmic contact region 6 is positioned in the middle above the second conductive type semiconductor well region 5, and the heavily doped first conductive type semiconductor source regions 7 are arranged on two sides of the heavily doped second conductive type semiconductor ohmic contact region 6; polysilicon gate by shieldA groove structure consisting of an electrode 8, a gate polycrystalline silicon electrode 9, a shielding gate dielectric layer 10 and an isolation dielectric layer 11 extends into the first layer of first conductive type semiconductor drift region 3, and the groove structure is positioned at two sides of the unit cell; in the groove, a shielding grid polycrystalline silicon electrode 8 is positioned below a grid polycrystalline silicon electrode 9 and is separated by an isolation dielectric layer 11, shielding grid polycrystalline silicon electrodes 8 and a first layer of first conduction type semiconductor drift region 3, shielding grid polycrystalline silicon electrodes 8 and a second layer of first conduction type semiconductor drift region 4 are separated by a shielding grid dielectric layer 10, and grid polycrystalline silicon electrodes 9 and a second conduction type semiconductor well region 5, and grid polycrystalline silicon electrodes 9 and a heavily doped first conduction type semiconductor source region 7 are separated by a grid dielectric layer 12; the inter-gate-source dielectric layer 13 is positioned above the gate polysilicon electrode 9, and the inter-gate-source dielectric layer 13 covers a part of the heavily doped first conductivity type semiconductor source region 7; the source metal 14 is positioned above the heavily doped second conductive type semiconductor ohmic contact region 6 and covers the other part of the heavily doped first conductive type semiconductor source region 7; the grid polysilicon electrode 9 is connected with grid potential, the drain metal 1 is connected with drain potential, and the shield grid polysilicon electrode 8 and the source metal 14 are in short circuit and are connected with source potential.
Preferably, the depth of the heavily doped second conductivity type semiconductor ohmic contact region 6 is deeper than the heavily doped first conductivity type semiconductor source region 7 and is not deeper than the second conductivity type semiconductor well region 5.
Preferably, the source metal 14 extends into the semiconductor material and it is still in contact with the heavily doped ohmic contact region 6 of the second conductivity type semiconductor and the heavily doped source region 7 of the first conductivity type semiconductor.
Preferably, the dielectric layer material is silicon dioxide or a high-K material with a dielectric constant higher than that of silicon dioxide.
Preferably, the semiconductor material is silicon or silicon carbide.
Preferably, the first conductivity type semiconductor is an N-type semiconductor, and the second conductivity type semiconductor is a P-type semiconductor; or the first conductivity type semiconductor is a P-type semiconductor and the second conductivity type semiconductor is an N-type semiconductor.
Preferably, the heavily doped doping concentration is greater than 1e19cm-3。
The invention has the beneficial effects that: the structure adopts the non-uniform doping distribution of the drift region, so that the longitudinal electric field of the drift region is uniformly distributed after the device is irradiated by a certain total dose, the breakdown voltage is the maximum value, when the radiation dose is less than the value, the breakdown voltage is less than the maximum value, and when the radiation dose exceeds the value, the breakdown voltage is also less than the maximum value. Therefore, when the device proposed by the present invention is subjected to a total dose of radiation, the breakdown voltage changes from increasing to decreasing as the radiation dose increases, which delays the failure of the device, so that a larger radiation dose is required to degrade the device to failure.
Drawings
Fig. 1 is a schematic diagram of a cell structure of a total dose radiation hardening resistant shielded gate VDMOS according to embodiment 1 of the present invention.
Fig. 2 shows the lateral electric field distribution in the shield gate VDMOS drift region and the shield gate oxide layer against total dose radiation hardening according to embodiment 1 of the present invention.
Fig. 3 is a graph of drift region doping concentration distribution theoretically derived in embodiment 1 of the present invention.
Fig. 4 is a graph showing the doping concentration profile of the drift region actually used in embodiment 1 of the present invention.
Fig. 5 is a schematic diagram of the longitudinal electric field distribution of the drift region of the device proposed by the invention in embodiment 1 when the radiation dose is equal to the set value.
Fig. 6 is a schematic diagram of the longitudinal electric field distribution of the drift region of the device proposed by the invention in embodiment 1 when the radiation dose is less than the set value.
Fig. 7 is a schematic diagram of the longitudinal electric field distribution of the drift region of the device proposed by the invention in example 1 when the radiation dose is greater than the set value.
Fig. 8 is a schematic diagram of the variation of the breakdown voltage with the radiation dose of the device proposed in embodiment 1 of the present invention.
The structure comprises a substrate, a drain electrode metal 1, a heavily doped first conductivity type semiconductor substrate 2, a first layer of first conductivity type semiconductor drift region 3, a second layer of first conductivity type semiconductor drift region 4, a second conductivity type semiconductor well region 5, a heavily doped second conductivity type semiconductor ohmic contact region 6, a heavily doped first conductivity type semiconductor source region 7, a shield gate polysilicon electrode 8, a gate polysilicon electrode 9, a shield gate dielectric layer 10, an isolation dielectric layer 11, a gate dielectric layer 12, an inter-gate-source dielectric layer 13 and a source electrode metal 14.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Example 1
The embodiment provides a total dose radiation hardening resistant shielding grid VDMOS, the cellular structure of which comprises:
the transistor comprises a drain metal 1, a heavily doped first conduction type semiconductor substrate 2, a first layer of first conduction type semiconductor drift region 3, a second layer of first conduction type semiconductor drift region 4, a second conduction type semiconductor well region 5, a heavily doped second conduction type semiconductor ohmic contact region 6, a heavily doped first conduction type semiconductor source region 7, a shielding gate polysilicon electrode 8, a gate polysilicon electrode 9, a shielding gate dielectric layer 10, an isolation dielectric layer 11, a gate dielectric layer 12, an inter-gate-source dielectric layer 13 and a source metal 14;
the heavily doped first conduction type semiconductor substrate 2 is positioned above the drain metal 1, the first layer of first conduction type semiconductor drift region 3 is positioned above the heavily doped first conduction type semiconductor substrate 2, and the second layer of first conduction type semiconductor drift region 4 is positioned above the first layer of first conduction type semiconductor drift region 3; the second layer of drift region 4 of the first conductivity type semiconductor has a doping concentration of less than 1e16cm-3The doping concentration of the first layer of the first conductive type semiconductor drift region 3 is distributed in a linear increasing manner from top to bottom; and the first layer isThe doping concentration of the first-conductivity-type semiconductor drift region 3 at the junction with the second-layer first-conductivity-type semiconductor drift region 4 is the same as that of the second-layer first-conductivity-type semiconductor drift region 4; the second conductive type semiconductor well region 5 is positioned above the second layer first conductive type semiconductor drift region 4, the heavily doped second conductive type semiconductor ohmic contact region 6 is positioned in the middle of the upper part of the second conductive type semiconductor well region 5, and heavily doped first conductive type semiconductor source regions 7 are arranged on two sides of the heavily doped second conductive type semiconductor ohmic contact region 6; a groove structure consisting of a shielding grid polycrystalline silicon electrode 8, a grid polycrystalline silicon electrode 9, a shielding grid dielectric layer 10 and an isolation dielectric layer 11 extends into the first layer of the first conductive type semiconductor drift region 3, and the groove structure is positioned at two sides of the unit cell; in the groove, a shielding grid polycrystalline silicon electrode 8 is positioned below a grid polycrystalline silicon electrode 9 and is separated by an isolation dielectric layer 11, shielding grid polycrystalline silicon electrodes 8 and a first layer of first conduction type semiconductor drift region 3, shielding grid polycrystalline silicon electrodes 8 and a second layer of first conduction type semiconductor drift region 4 are separated by a shielding grid dielectric layer 10, and grid polycrystalline silicon electrodes 9 and a second conduction type semiconductor well region 5, and grid polycrystalline silicon electrodes 9 and a heavily doped first conduction type semiconductor source region 7 are separated by a grid dielectric layer 12; the inter-gate-source dielectric layer 13 is positioned above the gate polysilicon electrode 9, and the inter-gate-source dielectric layer 13 covers a part of the heavily doped first conductivity type semiconductor source region 7; the source metal 14 is positioned above the heavily doped second conductive type semiconductor ohmic contact region 6 and covers the other part of the heavily doped first conductive type semiconductor source region 7; the grid polysilicon electrode 9 is connected with grid potential, the drain metal 1 is connected with drain potential, and the shield grid polysilicon electrode 8 is in short circuit with the source metal 14 and is connected with source potential.
Preferably, the dielectric layer material is silicon dioxide or a high-K material with a dielectric constant higher than that of silicon dioxide.
Preferably, the semiconductor material is silicon or silicon carbide.
Preferably, the first conductivity type semiconductor is an N-type semiconductor, and the second conductivity type semiconductor is a P-type semiconductor; or the first conductive type semiconductor is a P-type semiconductor and the second conductive type semiconductor is an N-type semiconductor.
Heavily doped with a doping concentration greater than 1e19cm-3。
The basic working principle is explained by taking the first conductive type semiconductor as an N-type semiconductor, the second conductive type semiconductor as a P-type semiconductor, the dielectric layer material as silicon dioxide and the semiconductor material as silicon as examples: when the bias voltage of the grid electrode is larger than the threshold voltage, an inversion layer is formed on the surface of the channel region, electrons flow out from the source electrode under the action of the high voltage of the drain electrode, sequentially pass through the channel region, the drift region of the second layer and the drift region of the first layer, then enter the substrate, and form a complete current path, namely the conducting state of the device. When the grid bias voltage is smaller than the threshold voltage, the inversion layer is not formed in the channel region, the device is in an off state, and the voltage is controlled to be Pbase-NdriftThe junction assumes the drain-source voltage.
The improvement effect of the structure provided by the invention on total dose radiation degradation is reflected as follows: in the total dose radiation process, electron-hole pairs are excited in an oxidation layer in the device, electrons with high mobility move out of the oxidation layer under the action of an electric field, holes with low mobility are captured by hole traps in the oxidation layer to form fixed positive charges, and the fixed positive charges of the oxidation layer have adverse effects on the electrical characteristics of the device. The fixed positive charges in the side wall oxide layer of the shielding grid destroy the original charge balance of the device, so that the longitudinal electric field of the drift region is weakened near the bottom of the groove and is weakened at Pbase-NdriftThe vicinity of the junction is enhanced, thereby reducing the breakdown voltage of the device. As the radiation dose increases, the variation of the longitudinal electric field of the drift region becomes more severe, and thus the breakdown voltage of the device continues to decrease. In the practical application process of the device, when the breakdown voltage is reduced to the actual voltage at two ends of the drain and the source of the device, the device is failed. In order to inhibit the degradation process, the doping distribution of the drift region can be adjusted, so that when a certain radiation dose exists in the shielding gate oxide layer, a longitudinal electric field of the drift region is uniformly distributed, and the breakdown voltage of the device is the maximum value. Then, when the radiation dose is less than the set value, the longitudinal electric field of the drift region is at Pbase-NdriftWeak near the knotStronger near the trench bottom; when the radiation dose is larger than the set value, the longitudinal electric field of the drift region is in Pbase-NdriftStronger near the junction and weaker near the trench bottom. When the radiation dose is larger than or smaller than a set value, the longitudinal electric field of the drift region is non-uniform, and the breakdown voltage is smaller than the maximum value, so that the breakdown voltage of the device changes from increasing to decreasing with the increase of the radiation dose, the radiation dose required for reducing the breakdown voltage to an invalid value becomes larger, and the failure process of the device is delayed.
The impurity concentration distribution of the drift region to be employed in the present invention is quantitatively derived as follows:
assuming that the longitudinal electric field in the drift region of the device is uniformly distributed after being irradiated by a certain total dose, the potential distribution in the drift region in the y direction, i.e. the longitudinal direction, is proportional to the depth y of the drift region:
V(y)＝Ey·y＝Ec·y (1)
wherein V (y) is the on-line distance P in the drift regionbase-NdriftDrift region potential at junction depth y, EyA longitudinal electric field in the drift region, EcIs the critical breakdown field.
In the transverse direction of the drift region, according to the boundary conditions of maxwell equations, the following can be obtained:
wherein epsilonoxIs the dielectric constant of the oxide layer, epsilonsiIs the dielectric constant of silicon, EoxTo shield the transverse electric field in the gate oxide layer, ExIs the lateral electric field in silicon.
The lateral electric field distribution of the device is shown in fig. 2, so the potential at any depth y on the line in the drift region can also be expressed as:
wherein, VoxFor the voltage drop in the oxide layer, VsIs the voltage drop across the semiconductor, EoxFor shielding the transverse electric field, t, in the gate oxide layeroxFor shielding the gate oxide thickness, ExIs a transverse electric field in silicon, WMIs the width of the drift region, QoxPositive charge quantity, epsilon, in the oxide layer of the shielding grid corresponding to a certain radiation doseoxIs the dielectric constant of the oxide layer, epsilonsiIs the dielectric constant of silicon.
In addition, in the transverse direction, there are:
wherein E isxIs a transverse electric field in silicon, WMIs the width of the drift region, epsilonsiIs the dielectric constant of silicon, q is the amount of elementary charge, NDAnd (y) is the doping concentration of the drift region at the depth y.
Substituting (1) and (4) into (3) can solve the doping concentration N of the drift regionD(y) the relationship of variation with depth y is:
visible drift region doping concentration NDThe (y) and the depth y are linear functions, and a schematic diagram is shown in FIG. 3. At a depth less than LD1When the doping concentration is negative, i.e. the doping type is P-type, this conflicts with the assumption that the depth will be less than LD1The doping concentration of the drift region is set to be uniformly lightly doped N-type, and the doping concentration of the drift region is shown in fig. 4.
Performing breakdown voltage simulation on a shielded gate VDMOS (vertical double-diffused metal oxide semiconductor) by using the doping distribution in the method, wherein FIG. 5 shows the longitudinal electric field distribution of the drift region when the radiation dose is equal to a set value, and the electric field distribution in the whole drift region is approximately uniformly distributed; FIG. 6 shows the longitudinal electric field distribution in the drift region when the radiation dose is smaller than the set value, in which the electric field gradually increases from the PN junction to the bottom of the trench; fig. 7 shows the longitudinal electric field distribution in the drift region when the radiation dose is larger than the set value, and the electric field gradually decreases from the PN junction to the bottom of the trench. Fig. 8 is a schematic illustration of the breakdown voltage of the proposed device as a function of radiation dose, the breakdown voltage of the device increasing first and then decreasing as a function of increasing radiation dose, consistent with theoretical predictions.
Example 2
This example differs from example 1 in that: the heavily doped second conductivity type semiconductor ohmic contact region 6 has a depth deeper than the heavily doped first conductivity type semiconductor source region 7 and not deeper than the second conductivity type semiconductor well region 5.
Example 3
This example differs from example 1 in that: the source metal 14 extends into the semiconductor material and it is still in contact with the heavily doped second conductivity type semiconductor ohmic contact regions 6 and the heavily doped first conductivity type semiconductor source regions 7.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (7)
1. A total dose radiation hardening resistant shielded gate VDMOS, characterized in that: the transistor comprises drain electrode metal (1), a heavily doped first conduction type semiconductor substrate (2), a first layer of first conduction type semiconductor drift region (3), a second layer of first conduction type semiconductor drift region (4), a second conduction type semiconductor well region (5), a heavily doped second conduction type semiconductor ohmic contact region (6), a heavily doped first conduction type semiconductor source region (7), a shielded gate polycrystalline silicon electrode (8), a gate polycrystalline silicon electrode (9), a shielded gate dielectric layer (10), an isolation dielectric layer (11), a gate dielectric layer (12), an inter-gate-source dielectric layer (13) and source electrode metal (14);
a heavily doped semiconductor substrate (2) of the first conductivity type at the drainThe first layer of first conduction type semiconductor drift region (3) is positioned above the heavily doped first conduction type semiconductor substrate (2), and the second layer of first conduction type semiconductor drift region (4) is positioned above the first layer of first conduction type semiconductor drift region (3); the second layer of drift region (4) of the first conductivity type semiconductor has a doping concentration of less than 1e16cm-3The doping concentration of the first layer of the first conductive type semiconductor drift region (3) is distributed in a linear increasing mode from top to bottom; the doping concentration of the first layer of first conduction type semiconductor drift region (3) at the junction with the second layer of first conduction type semiconductor drift region (4) is the same as that of the second layer of first conduction type semiconductor drift region (4); the second conductive type semiconductor well region (5) is positioned above the second layer first conductive type semiconductor drift region (4), the heavily doped second conductive type semiconductor ohmic contact region (6) is positioned in the middle above the second conductive type semiconductor well region (5), and the heavily doped first conductive type semiconductor source regions (7) are arranged on two sides of the heavily doped second conductive type semiconductor ohmic contact region (6); a groove structure consisting of a shielding grid polycrystalline silicon electrode (8), a grid polycrystalline silicon electrode (9), a shielding grid dielectric layer (10) and an isolation dielectric layer (11) extends into the first layer of the first conductive type semiconductor drift region (3), and the groove structure is positioned on two sides of the unit cell; in the groove, a shielding grid polycrystalline silicon electrode (8) is positioned below a grid polycrystalline silicon electrode (9) and is separated by an isolation dielectric layer (11), the shielding grid polycrystalline silicon electrode (8) and a first layer of first conductive type semiconductor drift region (3) and the shielding grid polycrystalline silicon electrode (8) and a second layer of first conductive type semiconductor drift region (4) are separated by a shielding grid dielectric layer (10), and the grid polycrystalline silicon electrode (9) and a second conductive type semiconductor drift region (5) and the grid polycrystalline silicon electrode (9) and a well region (7) of a heavily doped first conductive type semiconductor are separated by a grid dielectric layer (12); the inter-gate-source dielectric layer (13) is positioned above the gate polycrystalline silicon electrode (9), and the inter-gate-source dielectric layer (13) covers a part of the heavily doped first conductive type semiconductor source region (7); the source metal (14) is positioned above the heavily doped second conductive type semiconductor ohmic contact region (6) and covers the other part of the heavily doped first conductive type semiconductor source region (7); the grid polysilicon electrode (9) is connected with the gridAnd the potential, the drain electrode metal (1) is connected with the drain electrode potential, and the shield grid polycrystalline silicon electrode (8) is in short circuit with the source electrode metal (14) and is connected with the source electrode potential.
2. A total dose radiation hardening resistant shielded gate VDMOS as defined in claim 1 wherein: the depth of the heavily doped second conduction type semiconductor ohmic contact region (6) is deeper than the heavily doped first conduction type semiconductor source region (7) and is not deeper than the second conduction type semiconductor well region (5).
3. A total dose radiation hardening resistant shielded gate VDMOS as defined in claim 1 wherein: the source metal (14) extends into the semiconductor material and it is still in contact with the heavily doped ohmic contact region (6) of the second conductivity type semiconductor and the heavily doped source region (7) of the first conductivity type semiconductor.
4. A total dose radiation hardening resistant shielded gate VDMOS as defined in claim 1 wherein: the dielectric layer material is silicon dioxide or a high-K material with a dielectric constant higher than that of the silicon dioxide.
5. A total dose radiation hardening resistant shielded gate VDMOS as defined in claim 1 wherein: the semiconductor material is silicon or silicon carbide.
6. A total dose radiation hardening resistant shielded gate VDMOS as recited in claim 1, wherein: the first conductive type semiconductor is an N-type semiconductor, and the second conductive type semiconductor is a P-type semiconductor; or the first conductive type semiconductor is a P-type semiconductor and the second conductive type semiconductor is an N-type semiconductor.
7. The total dose radiation hardening resistant shielded gate VDMOS according to any one of claims 1 to 6, wherein: heavily doped with a doping concentration greater than 1e19cm-3。
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