CN115472696A - SiC power MOS device structure for reducing electric field at grid groove - Google Patents

SiC power MOS device structure for reducing electric field at grid groove Download PDF

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CN115472696A
CN115472696A CN202210963709.6A CN202210963709A CN115472696A CN 115472696 A CN115472696 A CN 115472696A CN 202210963709 A CN202210963709 A CN 202210963709A CN 115472696 A CN115472696 A CN 115472696A
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electric field
gate
power mos
device structure
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李�浩
钟铭浩
刘莉
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Xidian University
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Xidian University
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Abstract

A SiC power MOS device structure for reducing an electric field at a grid groove comprises a drain region, a substrate and a drift region from bottom to top, grid polycrystalline silicon is arranged above the drift region, symmetrical half-cell structures are arranged on the left side and the right side of the grid polycrystalline silicon, each half-cell structure comprises source metal located on the edge above the drift region, a P + region is arranged below the source metal, the lower side and the inner side of the P + region are both surrounded by Pwell, an N + source region is arranged between the upper side of the inner side of the source metal and the grid polycrystalline silicon, the Pwell extends upwards to the bottom of one side, away from the grid polycrystalline silicon, of the N + source region, pbody is arranged below the bottom of the other side of the N + source region, an N-type current expansion layer is arranged between the Pbody and the drift region, the bottom of the grid polycrystalline silicon and the side and bottom of an oxidation layer of the grid polycrystalline silicon are both connected in a mode, and the P + + region is arranged between the bottom of the oxidation layer and the drift region and serves as an electric field termination layer at the bottom of the oxidation layer. The invention can reduce the electric field at the corner of the groove gate and reduce the on-resistance at the same time.

Description

SiC power MOS device structure for reducing electric field at grid groove
Technical Field
The invention belongs to the technical field of integrated circuits, relates to a silicon carbide power device, and particularly relates to a SiC power MOS device structure for reducing an electric field at a grid groove.
Background
The silicon carbide (SiC) material has the excellent characteristics of wide forbidden band, high thermal conductivity, high breakdown electric field, high carrier saturation drift velocity and the like, so the silicon carbide (SiC) material is particularly suitable for manufacturing high-voltage and high-power semiconductor power electronic devices.
The trench power MOS (UMOS) is a power semiconductor device developed based on a trench gate process, and because a JFET (junction field effect transistor) area in a VDMOS (vertical double diffused metal oxide semiconductor) structure is eliminated, the opportunity of reducing internal impedance is provided for the power MOS, and the on-resistance is closer to an ideal value; compared with a transverse device, the cell size is small, so that the cell density is higher, the current density is also higher, the chip area is saved, large current drive can be generated, and a submicron channel is easy to form. Therefore, the power SiC UMOS has the advantage of smaller on-resistance and higher cell density, so that it is called a second generation SiC MOSFET device and has a higher market share.
However, UMOS is inferior to a lateral device in voltage withstanding, and is limited by a power MOS working scenario and a UMOS structural characteristic, a source-drain end often suddenly bears a large voltage during power MOS operation, so that a large electric field is generated, the electric field is more easily concentrated at a corner of a gate oxide layer due to the UMOS structural characteristic, the gate oxide layer may be broken down, and a serious reliability problem exists. At present, two approaches are mainly used for solving the reliability of the gate oxide layer, one is to improve the quality of the gate oxide layer so that the gate oxide layer can bear a higher electric field, and the improvement can only be made in the aspect of materials; the other is to protect the bottom of the gate oxide layer under the premise of not reducing the performance of the device, so that the electric field applied to the gate oxide layer is reduced. Therefore, the SiC UMOS has a contradiction between low on-resistance and high breakdown voltage in design, which becomes a main research direction for the current UMOS technology development.
In the existing protection measures, the electric field at the bottom of the trench gate is mostly reduced by adding a P + + shielding region below the gate trench, but the structure can generate a JFET resistance formed by Pbody and the P + + shielding region, so that the on-resistance is increased, and a Current Spreading Layer (CSL) is added below Pbody to alleviate the trend of increasing the on-conduction conductivity later, but the effect is not obvious, and the barre plus figure of merit is also reduced.
Disclosure of Invention
In order to overcome the above drawbacks of the prior art, an object of the present invention is to provide a SiC power MOS device structure for reducing an electric field at a gate trench, which employs a multi-step oxygen structure, and combines a P + + shielding region and a current spreading layer, so as to further reduce an on-resistance while reducing an electric field at a corner of a trench gate, and ensure that a belief figure of merit is not significantly reduced or even improved.
In order to achieve the purpose, the invention adopts the technical scheme that:
a SiC power MOS device structure for reducing an electric field at a gate trench, comprising a drain region, a substrate and a drift region arranged from bottom to top, a gate polysilicon disposed at a central position above the drift region, symmetrical half-cell structures disposed at left and right sides of the gate polysilicon, each of the half-cell structures including a source metal disposed at an edge above the drift region, a P + region disposed below the source metal, and a P + region surrounded by Pwell below and inside the P + region, an N + source region disposed between an inside top of the source metal and the gate polysilicon, the Pwell extending upward to a bottom of a side of the N + source region away from the gate polysilicon, a Pbody disposed below a bottom of the N + source region, an N-type current spreading layer disposed between the Pbody and the drift region, the gate polysilicon surrounded by an oxide layer except for a top thereof, and the bottom of the gate polysilicon and the oxide layer thereof are connected in a ladder manner, a P region disposed between the bottom of the oxide layer and the drift region, the P region serving as an electric field termination layer at the bottom of the oxide layer, and a doping concentration thereof is greater than a doping concentration of the P + region.
In one embodiment, the source metal is aluminum and the trench depth ranges from 0.98 to 1.02 μm.
In one embodiment, the doping concentration range of the P + region is (2.8-3.2) multiplied by 10 18 The doping concentration range of the Pwell is (1.8-2.2). Times.10 18 The doping concentration range of the N + source region is (4.8-5.2) multiplied by 10 18 The depth range of Pbody is 0.48-0.52 μm, and the doping concentration range (1.8-2.2) x 10 17 The doping concentration range of the N-type current extension layer is (1.8-2.2) multiplied by 10 17 The doping concentration range of the P + + region is (0.8-1.2) multiplied by 10 20 。
In one embodiment, the P + region is located below a side of the source metal away from the gate polysilicon.
In one embodiment, the step structure between the side surface and the bottom of the oxide layer is only adjacent to the P + + region.
In one embodiment, the step structure between the side surface and the bottom of the oxide layer is adjacent to the P + + region and the N-type current spreading layer.
In one embodiment, the bottom of the N-type current spreading layer is flush with the bottom of the trench gate, and the doping concentration of the N-type current spreading layer is (1.2-1.4) × 10 17 。
Compared with the prior art, the invention has the beneficial effects that:
1. the invention reduces the on-resistance and has stronger current driving capability.
2. The invention reduces the electric field at the corner of the grooved gate, so that the bottom of the grooved gate is better protected, and the Figure of Merit FOM (Figure of Merit) is improved.
Drawings
Fig. 1 is an overall structural view of the present invention.
Fig. 2 is a top view of the present invention.
Fig. 3 is a schematic diagram of a conventional MOS structure.
Fig. 4 is a schematic diagram of the electric field at the corners of a conventional fm MOS.
Fig. 5 is a schematic diagram of the improved structure of the conventional μ MOS.
Fig. 6 is a schematic diagram of the electric field at the corner of a conventional MOS after modification.
Fig. 7 is a schematic diagram of structure 1 after improvement of the step oxygen MOS according to the present invention.
Fig. 8 is a schematic diagram of the electric field at the corner after the step oxygen MOS is improved according to the present invention.
Fig. 9 is a schematic diagram of structure 2 after improvement of the step oxygen MOS according to the present invention.
Fig. 10 is a schematic diagram of the electric field at the corner after the step oxygen MOS is improved according to the present invention.
Detailed Description
The embodiments of the present invention will be described in detail below with reference to the drawings and examples.
Compared with a planar metal oxide semiconductor (VDMOS) device, the SiC groove type MOS (Mu MOS) device has lower on-resistance, but the electric field intensity at the groove gate corner is very high, which is easy to cause reliability problem, and in the application process of the power SiC MOSFET device, usually under the scenes of large capacity, high power and inductive load, the device can work in a blocking mode, and the gate oxide SiO is 2 Bear high electric field and easily reach SiO 2 The critical breakdown field strength causes the oxide layer to be degraded or broken down, thereby causing the failure of the device and having serious potential safety hazard. Specifically, the electric field at the bottom of the trench gate of these structures is strong, affecting the reliability of the gate oxide layer; some existing improvement methods can relieve the electric field at the bottom of the trench gate, but make the on-resistance larger.
Based on the structure, the invention uses sendauraus software to carry out structural design and verification, the whole structure is shown in figure 1, and because the structure is bilaterally symmetrical, subsequent pictures are all given in a left half cell form.
Referring to fig. 1 and fig. 2, the present invention provides a SiC power MOS device structure for reducing an electric field at a gate trench, including a drain region, a substrate, and a drift region, wherein the substrate is on the drain region, the drift region is on the substrate, gate polysilicon is disposed at a central position above the drift region, and symmetric half-cell structures are disposed at left and right sides of the gate polysilicon.
Taking the structure of the left half cell as an example, which includes a source metal located at the upper edge of the drift region, in the present invention, the source metal is aluminum, and the trench depth may be set to 0.98-1.02 μm, preferably 1 μm, for example. In the present invention, the depth refers to the vertical direction.
The P + region is disposed under the source metal, and the P + region is preferably disposed under the side of the source metal away from the gate polysilicon, i.e. the width in the left-right direction should preferably be smaller than that of the source metal, and the doping concentration of the P + region is in the range of 2.8-3.2 × 10 18 Preferably 3X 10 18 . The P + region is surrounded by Pwell at the lower and inner sides, and the doping concentration of Pwell is 1.8-2.2 × 10 18 Preferably 2X 10 18 . Pwell and drift regionThe PN junction is a main voltage bearing area, and the bottom of the source level groove and the grid groove bear voltage together, so that an electric field below the groove grid can be relieved to a certain degree.
The N + source region is arranged between the upper part of the inner side of the source metal and the grid polysilicon, pwell extends upwards to the bottom of the left side of the N + source region, and the doping concentration range of the N + source region is 4.8-5.2 multiplied by 10 18 Preferably 5X 10 18 . Pbody is arranged below the bottom of the right side of the N + source region, the left side of the Pbody is connected with the right side of the Pwell, and the Pbody has a depth ranging from 0.48 to 0.52 μm, preferably 0.5 μm, and a doping concentration ranging from 1.8 to 2.2 × 10 17 Preferably 2X 10 17 。
The invention arranges an N-type current spreading layer between the Pbody and the drift region, and the doping concentration range of the N-type current spreading layer is 1.8-2.2 multiplied by 10 17 Preferably 2X 10 17 . The N-type current spreading layer increases the carrier concentration of the current path and is therefore a key component in reducing the on-resistance.
Except the top of the grid polysilicon, the bottom surface and all side surfaces are all oxidized layers, namely SiO 2 Surrounding, connecting the bottom of the gate polysilicon and the side and bottom of the oxide layer in a step manner, disposing a P + + region between the bottom of the oxide layer and the drift region, wherein the P + + region is used as an electric field stop layer at the bottom of the oxide layer and has a doping concentration obviously greater than that of the P + region, which can be, for example, 0.8-1.2 × 10 20 Preferably 1X 10 20 。
According to the structure, the electric field intensity at the bottom of the groove gate is reduced on the premise of basically not influencing other performances of the device, the on-resistance is reduced compared with the existing improvement method, and the breakdown voltage of the device can be improved. The principle is as follows: the current spreading layer increases the carrier concentration on the current path, so that the on-resistance is reduced; the grid oxide layer is in a step shape, so that a depletion region of the device in an avalanche state is increased, and the breakdown voltage of the device is improved.
FIG. 3 shows a conventional UMOS structure, which is not provided with an N-type current spreading layer and a P + + region and has an on-resistance of 7.322m Ω · cm in comparison with the present invention 2 Breakdown ofThe voltage was 1322V, the value of the Barre plus Merit FOM (Figure of Merit) was 0.238kV 2 /mΩ·cm 2 Since the bottom of the gate oxide layer is not protected, the bottom electric field reaches 3.79MV, as shown in FIG. 4. The parameter conditions are as follows: the grid-source voltage VGS is 15V, the drain-source voltage is increased, and when the drain-source voltage VDS is 1.86V, the on-resistance is obtained; the gate-source voltage VGS is 0V, the drain-source voltage is increased, and when the drain current ID is 1mA, the breakdown voltage is obtained.
The structure form of the prior art after the improvement is shown in fig. 5, and an N-type current extension layer and a P + + region are added, but the step form of the present invention is not adopted.
Compared with the structure of fig. 3, the P + + region is increased, but the P + + region and Pbody form a JFET region, so that the on-resistance is increased, and therefore, an N-type current spreading layer is introduced to reduce the on-resistance. The on-resistance is 11.062 mOmega cm 2 The breakdown voltage is 1466V, and the Baligu FOM is 0.194kV 2 /mΩ·cm 2 It can be seen that although the breakdown voltage of the structure is increased, the on-resistance is also increased, so the bargara figure of merit is reduced, and due to the existence of the P + + masking region, the maximum electric field appears below the P + + masking region and is 3.37MV, but the bottom of the trench gate is effectively protected, and the electric field is reduced to below 3MV, as shown in fig. 6. The parameter conditions are the same as those of fig. 3 and 4 described above.
The invention uses a step form to balance the relation among the on-resistance, the breakdown voltage and the electric field at the corner of the groove gate. The depletion effect of the P + + masking region is weakened by the step-shaped oxide layer, so that the corners of the trench gate are protected and the on-resistance is reduced, and the structures after the structure are respectively shown in fig. 7 and fig. 9.
In the structure of fig. 7, a step structure is formed between the side surface and the bottom of the oxide layer, and the P + + region and the N-type current spreading layer are adjacent to each other. The on-resistance was 8.171 m.OMEGA.cm 2 The breakdown voltage is 1429V, the Baligu FOM is 0.25kV 2 /mΩ·cm 2 Compared with the prior art, the on-resistance is reduced by 26.1%, the BarlGau value is remarkably improved, the maximum electric field is generated below the P + masking region and is 3.09MV, and the corners of the groove gate are provided with groovesThe electric field also drops below 3MV as shown in fig. 8. The parameter conditions are the same as those of fig. 3 and 4 described above.
In the structure of fig. 9, the step structure between the side surface and the bottom of the oxide layer is only adjacent to the P + + region. The on-resistance is 9.084m omega cm 2 The breakdown voltage is 1461V, and the Barre plus merit FOM is 0.235kV 2 /mΩ·cm 2 Compared with the prior art, the breakdown voltage is basically unchanged, the on-resistance is reduced by 17.9%, the bargara figure of merit is improved, the maximum electric field appears below the P + masking region and is 3.37MV, the electric field at the corner of the trench gate is about 2.7MV, and as shown in figure 10, the electric field intensity is obviously inhibited. The parameter conditions are the same as those of fig. 3 and 4 described above.
In an alternative of the invention, the trench gate can be protected by changing the shape of the current spreading layer and adjusting its doping concentration. For example, the bottom of the N-type current spreading layer and the bottom of the trench gate can be kept flush, and the doping concentration of the N-type current spreading layer can be adjusted to be (1.2-1.4) × 10 17 And the P + + region is used as an electric field termination layer to reduce the influence of a high electric field of the drain electrode on the bottom of the trench gate.

Claims (7)

1. A SiC power MOS device structure for reducing an electric field at a gate trench, comprising a drain region, a substrate and a drift region arranged from bottom to top, a gate polysilicon disposed at a central position above the drift region, symmetrical half-cell structures disposed at left and right sides of the gate polysilicon, each of the half-cell structures including a source metal disposed at an edge above the drift region, a P + region disposed below the source metal, and a P + region surrounded by Pwell below and inside the P + region, a N + source region disposed between the inside of the source metal and the gate polysilicon, the Pwell extending upward to a bottom of a side of the N + source region away from the gate polysilicon, a Pbody disposed below a bottom of the N + source region, wherein an N-type current spreading layer is disposed between the Pbody and the drift region, the gate polysilicon is surrounded by an oxide layer except for a top portion thereof, and a bottom of the gate polysilicon and a side and a bottom of the oxide layer thereof are connected in a step-like manner, a P region is disposed between the bottom of the oxide layer and the drift region, the P region serves as an electric field termination layer, and a concentration of the doped region at the bottom of the P + region is greater than a + + region.
2. The SiC power MOS device structure for reducing the electric field at the gate trench of claim 1 wherein the source metal is aluminum and the trench depth ranges from 0.98 μ ι η to 1.02 μ ι η.
3. The SiC power MOS device structure of claim 1 with reduced electric field at the gate trench, wherein the P + region has a doping concentration in the range of (2.8-3.2) × 10 18 The doping concentration range of the Pwell is (1.8-2.2). Times.10 18 The doping concentration range of the N + source region is (4.8-5.2) multiplied by 10 18 The depth range of Pbody is 0.48-0.52 μm, and the doping concentration range is (1.8-2.2). Times.10 17 The doping concentration range of the N-type current expansion layer is (1.8-2.2) multiplied by 10 17 The doping concentration range of the P + + region is (0.8-1.2) multiplied by 10 20 。
4. The SiC power MOS device structure for reducing the electric field at the gate trench according to claim 1 or 3, wherein the P + region is located below a side of the source metal away from the gate polysilicon.
5. The SiC power MOS device structure for reducing the electric field at the gate trench of claim 1, wherein the step structure between the side and bottom of the oxide layer is adjacent to only the P + + region.
6. The SiC power MOS device structure for reducing the electric field at the gate trench of claim 1, wherein a step structure between a side surface and a bottom of the oxide layer is simultaneously adjacent to the P + + region and the N-type current spreading layer.
7. The SiC power MOS device structure for reducing the electric field at the gate trench of claim 1, wherein a bottom of the N-type current spreading layer and the trench gateThe bottom is flush, the doping concentration of the N-type current expansion layer is (1.2-1.4) multiplied by 10 17 。
CN202210963709.6A 2022-08-11 2022-08-11 SiC power MOS device structure for reducing electric field at grid groove Pending CN115472696A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116598347A (en) * 2023-07-19 2023-08-15 北京昕感科技有限责任公司 SiC MOSFET cell structure with curved gate trench, device and preparation method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116598347A (en) * 2023-07-19 2023-08-15 北京昕感科技有限责任公司 SiC MOSFET cell structure with curved gate trench, device and preparation method
CN116598347B (en) * 2023-07-19 2023-09-29 北京昕感科技有限责任公司 SiC MOSFET cell structure with curved gate trench, device and preparation method

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