WO2016026422A1 - Ldmos device and manufacturing method thereof - Google Patents

Ldmos device and manufacturing method thereof Download PDF

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Publication number
WO2016026422A1
WO2016026422A1 PCT/CN2015/087333 CN2015087333W WO2016026422A1 WO 2016026422 A1 WO2016026422 A1 WO 2016026422A1 CN 2015087333 W CN2015087333 W CN 2015087333W WO 2016026422 A1 WO2016026422 A1 WO 2016026422A1
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region
field oxide
type
oxide layer
body region
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PCT/CN2015/087333
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French (fr)
Chinese (zh)
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金宏峰
李许超
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无锡华润上华半导体有限公司
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Publication of WO2016026422A1 publication Critical patent/WO2016026422A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to an LDMOS device and a method of fabricating the same.
  • High voltage lateral double diffused metal oxide semiconductor (High Voltage lateral) in 0.35um BCD process Double diffusion metal oxide Semiconductor, referred to as HVLDMOS) (18-24V operating voltage) uses the field oxide layer as a drift region to achieve withstand voltage.
  • HCI hot carrier injection
  • the usual way to improve HCI is to optimize the electric field distribution near the channel by adjusting the injection energy and dose (NM/NG level injection) to reduce the impact ionization intensity, which is reflected in the first peak of ISUB.
  • the table in Figure 1 lists the results of four experimental shards, all aimed at reducing ISUB. The 1st peak improves the HCI lifetime.
  • An LDMOS device including:
  • the body region and the drift region are formed on the surface of the semiconductor substrate and spaced apart from each other, and the body region and the drift region have a first conductivity type and a second conductivity type, respectively;
  • the field oxide layer formed above the drift region, the field oxide layer having a thickness ranging from 1000 to 3000 angstroms;
  • a source region and a drain region are located on both sides of the field oxide layer and are respectively formed in the body region and the drift region;
  • a gate electrode is formed on the semiconductor substrate between the body region and the drift region and partially covers the body region and the field oxide layer.
  • a method for fabricating an LDMOS device comprising:
  • the field oxide layer Forming a field oxide layer above the drift region, the field oxide layer having a thickness ranging from 1000 to 3000 angstroms;
  • a gate is formed over the gate dielectric layer that extends over the field oxide layer adjacent the gate dielectric layer.
  • the thickness of the field oxide layer above the drift region is thinner, and the RESURF effect of the polysilicon field plate is enhanced, and the maximum impact ionization point is shifted from the channel surface to the drift region.
  • the body is transferred away from the channel, and the hot electrons are less likely to enter the gate oxide, thereby greatly increasing the lifetime of the device's HCI (hot carrier), thereby improving device reliability and yield.
  • HCI hot carrier
  • Figure 1 is a list of the results obtained by adjusting the IMP parameters four times
  • Figure 2 is a peak distribution map of Isub for the fourth IMP adjustment
  • FIG. 3 is a schematic cross-sectional view of an LDMOS device of an embodiment
  • FIG. 6 is a flow chart of a method of fabricating an LDMOS device of an embodiment.
  • FIG. 3 is a schematic cross-sectional view showing a HVLDMOS according to an embodiment of the present invention.
  • the HVLDMOS is an N-type LDMOS, and the N-type LDMOS of the present embodiment will be specifically described below with reference to FIG.
  • the LDMOS device 30 includes a semiconductor substrate 300, a body region 301, a drift region 302, a deep well region 303 surrounding the body region 301 and the drift region 302, a field oxide layer 304 over the drift region 302, and a gate.
  • the body region 301 and the drift region 302 are formed on the surface of the semiconductor substrate 300 at intervals from each other, and have a first conductivity type and a second conductivity type, respectively.
  • the deep well region 303 has the same conductivity type as the body region 301, that is, the first conductivity type.
  • the semiconductor substrate 300 of the LDMOS device 30 provided by the present invention may be silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI). And at least one of germanium on insulator (GeOI).
  • the semiconductor substrate 300 includes a silicon substrate, a buried layer formed at a surface of the silicon substrate, and an epitaxial layer formed on the buried layer.
  • Components or regions such as body region 301, drift region 302, deep well region 303, gate 305, source region 306, drain region 307, and body region lead-out region 308 of LDMOS device 30 may be formed on the epitaxial layer.
  • the semiconductor substrate 300 of such a structure has a good isolation effect and a small parasitic capacitance.
  • the body region 301 and the deep well region 303 of the LDMOS device 30 have a first conductivity type, and the drift region 302 has a second conductivity type different from the body region 301 and the deep well region 303.
  • the types of conductivity in semiconductor devices mainly include two types, namely, P-type doping and N-type doping.
  • the main doping elements of the P-type doping include boron (B) and phosphorus (P), and the main doping element of the N-type doping is arsenic (As).
  • the first conductivity type may be a P-type dopant
  • the second conductivity type may be an N-type dopant. That is, the body region 301 and the deep well region 303 are P-type doped, and the drift region 302 is N-type doped.
  • Doping is generally achieved by means of implantation.
  • the doping concentration of the drift region 302 is relatively low, which is equivalent to forming a high resistance layer between the source region 306 and the drain region 307, which can increase the breakdown voltage and reduce the source region 306 and the drain region 307.
  • the parasitic capacitance between them helps to improve the frequency characteristics.
  • the implantation dose of the drift region 302 may be 1.5 x 1012 to 5 x 1012 cm-2.
  • the doping concentration of the body region 301 is relatively high, and the implantation dose is correspondingly high.
  • the implantation dose of the body region 301 may be 1 x 1013 to 3 x 1013 cm-2.
  • the conductivity type of the deep well region 303 may be the same as that of the body region 301, and the doping concentrations of the two may be different. As an example, the doping concentration of the deep well region 303 may be lower than the doping concentration of the body region 301. Accordingly, the implantation dose of the deep well region 303 may be lower than the implantation dose of the body region 301 during the implantation process. It should be noted that since the implantation depth of the deep well region 303 needs to be larger than the implantation depth of the body region 301, the energy of ions is higher when the deep well region 303 is formed by ion implantation, and the body region 301 is formed by ion implantation. At the time, the energy of the ions is low.
  • the field oxide layer 304 is formed over the drift region 302, and the field oxide layer 304 has a thickness ranging from 1000 to 3000 angstroms.
  • the source region 306 and the drain region 307 are located on both sides of the field oxide layer 304 and are formed in the body region 301 and the drift region 302, respectively.
  • Source region 306 and drain region 307 may be formed by existing doping processes.
  • a body region lead-out region 308 is formed in the body region 301, and the body region lead-out region 308 is spaced apart from the source region 306 also located in the body region 301.
  • a gate electrode 305 is formed on the semiconductor substrate 110 between the body region 301 and the drift region 302, and partially covers the body region 301 and the field oxide layer 304.
  • a gate dielectric layer 309 is formed under the gate 305 , and the gate dielectric layer 309 is located between the source region 306 and the field oxide layer 304 .
  • the thickness of the field oxide layer above the drift region is thinner, and the surface electric field effect of the polysilicon field plate is enhanced (Reduced Surface Field, Resurf), the maximum impact ionization point is transferred from the channel surface to the drift region.
  • Resurf Reduced Surface Field
  • the strongest position of the impact ionization is close to the lower surface of the field oxide layer and close to the surface of the semiconductor substrate (near the channel region), so the hot electrons are easy to enter.
  • the gate dielectric layer above the channel affects the lifetime of the HCI (hot carrier).
  • HCI hot carrier
  • a slice experiment was performed on the thickness of the field oxide layer above the drift region, which was reduced to 3000 ⁇ on the basis of the original 4000 ⁇ .
  • the ISUB curve shows that the peak change is not obvious, and the overall ISUB value is not the smallest compared with the previous one, indicating that the impact ionization is not significantly weakened, but the HCI (hot carrier) life improvement effect is improved.
  • HCI hot carrier
  • the HCI of the 18-24V device can reach the standard, which verifies that the thickness of the oxide layer in the drift region is thinned to make the maximum impact ionization point away from the channel, and the hot electrons. It is less likely to enter the gate dielectric layer. And it can be seen from the deterioration trend graph that the degradation is small.
  • the thickness of the field oxide layer above the drift region is thinner, enhancing the RESURF effect of the polysilicon field plate, and transferring the maximum impact ionization point from the channel surface to the drift region.
  • hot electrons are less likely to enter the gate oxide, which greatly increases the device's HCI (hot carrier) lifetime, thereby increasing device reliability and yield.
  • the present invention provides a method for fabricating an LDMOS device, including:
  • Step 601 providing a semiconductor substrate, implanting an N-type buried layer in the semiconductor substrate, and forming an epitaxial layer on the buried layer.
  • the semiconductor substrate is P-type doped, and its specific doping concentration is not limited by the present invention.
  • the semiconductor substrate may be specifically formed by epitaxial growth or may be a wafer substrate.
  • An N-type buried layer is formed in the semiconductor substrate, and the implanted layer may have a plurality of implant elements.
  • the implanted element of the buried layer may be germanium (Sb).
  • a P-type epitaxial layer is prepared on a semiconductor substrate implanted with an N-type buried layer.
  • Step 602 performing P-type ion implantation in the P-type epitaxial layer to form a P-type deep well region.
  • a P-type deep well region is prepared by ion implantation of boron.
  • the energy of ion implantation when forming the deep well region is 600 KeV to 1000 KeV.
  • Step 603 patterning the body region and the drift region in the surface of the P-type deep well region.
  • An N-type drift region is generated by ion implantation of an N-type impurity (for example, phosphorus).
  • the body region and the deep well region have the same doping type, both of which are P-type.
  • Step 604 forming a field oxide layer over the drift region.
  • the field oxide layer may be formed by local oxidation of the LOCOS process.
  • the thickness of the field oxide layer is reduced by at least 1000 angstroms to a thickness ranging from 1000 to 3000 angstroms.
  • Step 605 forming source and drain regions on both sides of the field oxide layer and in the body region and the drift region, respectively.
  • the source and drain regions are formed by patterning the N-type doping of the substrate to form an N+ well, and the doping concentrations of the source and drain regions may be the same, and thus, the two may be doped simultaneously.
  • a source S and a drain D may be formed respectively above the source and drain regions; a source S is used to extract the source region, and two are defined as source terminals of the LDMOS; and a drain D is used to lead the drain region, the two are defined It is the drain of LDMOS.
  • Step 606 forming a gate dielectric layer between the source region and the field oxide layer. Specifically, it may form a gate dielectric layer by local oxidation, and of course, a gate dielectric layer may be patterned by a method such as thin film deposition.
  • Step 607 forming a gate on the gate dielectric layer, the gate portion extending over the field oxide layer adjacent to the gate dielectric layer.
  • the gate specific material is not limited by the present invention, for example, it may be formed by low resistivity polysilicon patterning, or may be deposited by chemical vapor deposition, physical vapor deposition, magnetron sputtering, or the like.
  • the maximum impact ionization point is transferred from the channel surface to the drift region away from the channel by reducing the thickness of the drift field oxide layer and enhancing the RESURF effect of the polysilicon field plate. It is less likely to enter the gate oxide to greatly increase the device's HCI (hot carrier) lifetime, thereby increasing device reliability and yield.
  • HCI hot carrier

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Abstract

An LDMOS device (30) and manufacturing method thereof; the LDMOS device (30) comprises: a semiconductor substrate (300); a body region (301) and a drift region (302) formed on the surface of the semiconductor substrate (300) with an interval therebetween and respectively having a first conduction type and a second conduction type; a field oxidation layer (304) formed on the drift region (302) and having a thickness range of 1000-3000 angstroms; a source region (306) and a drain region (307) located at two sides of the field oxidation layer (304) and respectively formed in the body region (301) and the drift region (302); a body region extraction region (308) formed in the body region (301) and separated by an interval from the source region (306); and a gate electrode (305) formed on the semiconductor substrate (300) between the body region (301) and the drift region (302) and partially covering the body region (301) and the field oxidation layer (304).

Description

LDMOS器件及其制作方法 LDMOS device and manufacturing method thereof
【技术领域】[Technical Field]
本发明涉及半导体技术领域，尤其涉及一种LDMOS器件及其制作方法。The present invention relates to the field of semiconductor technologies, and in particular, to an LDMOS device and a method of fabricating the same.
【背景技术】【Background technique】
在0.35um BCD工艺中，高压横向双扩散金属氧化物半导体（High Voltage lateral double diffusion metal oxide semiconductor，简称HVLDMOS）（18-24V操作电压）使用场氧化层做漂移区实现耐压功能。在可靠性评估过程中，最大的问题来自于热载流子注入(Hot carrier injection，简称HCI)失效。改善HCI通常的办法是通过调整注入能量、剂量（NM/NG层次注入）来优化沟道附近电场分布，减弱碰撞电离强度，具体表现在ISUB第一个峰值的降低。图1中表格列出了四次实验分片的结果，目的都是为了降低ISUB 1st峰值从而改善HCI寿命，可以看出，虽然四次注入组合都逐步优化电场分布，从图2的ISUB 1st峰值看碰撞电离减弱，但是HCI寿命时间并没有得到有效改善，还是没有达标(HCI目标>0.2Year)，因此仅通过调整离子注入能量剂量来减弱碰撞电离的角度出发，虽然电场大小优化确实对HCI寿命有改善，但是并不能达到HCI通过的可靠性标准。而且离子注入剂量调整范围有限，难以达到优化沟道附近电场分布，减弱碰撞电离强度，提高器件可靠性和良率的目的。High voltage lateral double diffused metal oxide semiconductor (High Voltage lateral) in 0.35um BCD process Double diffusion metal oxide Semiconductor, referred to as HVLDMOS) (18-24V operating voltage) uses the field oxide layer as a drift region to achieve withstand voltage. In the reliability assessment process, the biggest problem comes from hot carrier injection (Hot Carrier Injection, referred to as HCI) is invalid. The usual way to improve HCI is to optimize the electric field distribution near the channel by adjusting the injection energy and dose (NM/NG level injection) to reduce the impact ionization intensity, which is reflected in the first peak of ISUB. The table in Figure 1 lists the results of four experimental shards, all aimed at reducing ISUB. The 1st peak improves the HCI lifetime. It can be seen that although the four injection combinations gradually optimize the electric field distribution, from the ISUB of Figure 2 The 1st peak sees the impact ionization weakened, but the HCI life time has not been effectively improved, or it has not reached the standard (HCI target >0.2Year), so only by adjusting the ion implantation energy dose to reduce the impact ionization angle, although the electric field size optimization is indeed HCI has improved life, but it does not meet the reliability standards passed by HCI. Moreover, the ion implantation dose adjustment range is limited, and it is difficult to achieve the purpose of optimizing the electric field distribution near the channel, weakening the impact ionization intensity, and improving device reliability and yield.
【发明内容】 [Summary of the Invention]
基于此，有必要提出一种新的横向双扩散金属氧化物半导体场效应晶体管及其制作方法，以提高器件的可靠性和良率。Based on this, it is necessary to propose a new lateral double-diffused metal oxide semiconductor field effect transistor and its fabrication method to improve the reliability and yield of the device.
一种LDMOS器件，包括：An LDMOS device, including:
半导体衬底;Semiconductor substrate
体区和漂移区，形成于半导体衬底的表面且相互间隔，体区和漂移区分别具有第一导电类型和第二导电类型；The body region and the drift region are formed on the surface of the semiconductor substrate and spaced apart from each other, and the body region and the drift region have a first conductivity type and a second conductivity type, respectively;
场氧化层，形成于漂移区上方，该场氧化层的厚度范围为1000~3000埃；a field oxide layer formed above the drift region, the field oxide layer having a thickness ranging from 1000 to 3000 angstroms;
源区和漏区，位于场氧化层的两侧并分别形成于体区和漂移区内； a source region and a drain region are located on both sides of the field oxide layer and are respectively formed in the body region and the drift region;
体区引出区，形成于体区内且与源区间隔开；及a body region lead-out area formed in the body region and separated from the source region; and
栅极，形成于位于体区和漂移区之间的半导体衬底上，并部分覆盖体区和场氧化层。A gate electrode is formed on the semiconductor substrate between the body region and the drift region and partially covers the body region and the field oxide layer.
一种LDMOS器件的制作方法，包括：A method for fabricating an LDMOS device, comprising:
提供半导体衬底，在半导体衬底内注入形成N型掩埋层，在N型掩埋层上形成P型外延层；Providing a semiconductor substrate, implanting an N-type buried layer in the semiconductor substrate, and forming a P-type epitaxial layer on the N-type buried layer;
在P型外延层中进行P型离子注入形成P型深阱区；Performing P-type ion implantation in the P-type epitaxial layer to form a P-type deep well region;
在P型深阱区的表面内构图形成体区和漂移区；Forming a body region and a drift region in the surface of the P-type deep well region;
在漂移区上方形成场氧化层，该场氧化层的厚度范围为1000~3000埃；Forming a field oxide layer above the drift region, the field oxide layer having a thickness ranging from 1000 to 3000 angstroms;
在场氧化层的两侧并分别于体区和漂移区内形成源区和漏区；Forming source and drain regions on both sides of the field oxide layer and in the body region and the drift region, respectively;
在源区和场氧化层之间形成栅介电层；及Forming a gate dielectric layer between the source region and the field oxide layer; and
在栅介电层上形成栅极，该栅极部分延伸至与栅介电层相邻的场氧化层的上方。A gate is formed over the gate dielectric layer that extends over the field oxide layer adjacent the gate dielectric layer.
综上所述，根据本发明的LDMOS器件及其制作方法，在漂移区上方的场氧化层的厚度较薄，增强了多晶硅场板的RESURF作用，将最大碰撞电离点从沟道表面向漂移区体内转移使其远离沟道，热电子更不容易进入栅氧从而大幅提高器件的HCI（热载流子）寿命，进而提高了器件的可靠性和良率。In summary, according to the LDMOS device of the present invention and the manufacturing method thereof, the thickness of the field oxide layer above the drift region is thinner, and the RESURF effect of the polysilicon field plate is enhanced, and the maximum impact ionization point is shifted from the channel surface to the drift region. The body is transferred away from the channel, and the hot electrons are less likely to enter the gate oxide, thereby greatly increasing the lifetime of the device's HCI (hot carrier), thereby improving device reliability and yield.
【附图说明】[Description of the Drawings]
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，其中：In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, wherein:
图1为四次IMP参数调整所获得结果的列表图；Figure 1 is a list of the results obtained by adjusting the IMP parameters four times;
图2为四次IMP调整对应Isub的峰值分布图；Figure 2 is a peak distribution map of Isub for the fourth IMP adjustment;
图3为一实施例的LDMOS器件的剖面示意图；3 is a schematic cross-sectional view of an LDMOS device of an embodiment;
图4为一实施例的场氧化层减薄后24V HS Isub的曲线图；4 is a graph of 24V HS Isub after field oxide thinning in an embodiment;
图5为一实施例的LDMOS器件的HCI寿命测试结果的列表图；5 is a list of HCI life test results of an LDMOS device of an embodiment;
图6为一实施例的LDMOS器件的制作方法的流程图。6 is a flow chart of a method of fabricating an LDMOS device of an embodiment.
【具体实施方式】 【detailed description】
对于本发明的包括结构和对部分的组合的各种新颖细节的以上及其他的特征，和其他的优点，现在将参考附图进行更特别地描述并且在权利要求中指出。应理解的是，实现本发明的特定的方法和装置，是以本发明的例证的方式并且不作为本发明的限制而示出的。在不偏离本发明的范围的情况下，可在各种各样的和大量的实施例中采用本发明的原理和特征。The above and other features, and other advantages of the present invention, which are described in the appended claims and the claims. It is to be understood that the specific methods and apparatus of the invention are shown in The principles and features of the present invention may be employed in a variety of and numerous embodiments without departing from the scope of the invention.
图3所示为按照本发明一实施例的HVLDMOS的基本剖面示意图。在本该实施例中，HVLDMOS为N型LDMOS，以下结合图3对本该实施例的N型LDMOS进行具体说明。3 is a schematic cross-sectional view showing a HVLDMOS according to an embodiment of the present invention. In the present embodiment, the HVLDMOS is an N-type LDMOS, and the N-type LDMOS of the present embodiment will be specifically described below with reference to FIG.
本发明提供一种LDMOS器件。如图3所示，LDMOS器件30包括：半导体衬底300、体区301、漂移区302、环绕体区301和漂移区302的深阱区303、位于漂移区302上方的场氧化层304、栅极305、源区306、漏区307以及体区引出区308。其中，体区301和漂移区302相互间隔地形成于半导体衬底300的表面，且分别具有第一导电类型和第二导电类型。深阱区303具有与体区301相同的导电类型，即第一导电类型。The present invention provides an LDMOS device. As shown in FIG. 3, the LDMOS device 30 includes a semiconductor substrate 300, a body region 301, a drift region 302, a deep well region 303 surrounding the body region 301 and the drift region 302, a field oxide layer 304 over the drift region 302, and a gate. The pole 305, the source region 306, the drain region 307, and the body region lead-out region 308. Wherein, the body region 301 and the drift region 302 are formed on the surface of the semiconductor substrate 300 at intervals from each other, and have a first conductivity type and a second conductivity type, respectively. The deep well region 303 has the same conductivity type as the body region 301, that is, the first conductivity type.
本发明提供的LDMOS器件30的半导体衬底300可以是硅、绝缘体上硅（SOI）、绝缘体上层叠硅（SSOI）、绝缘体上层叠锗化硅（S-SiGeOI）、绝缘体上锗化硅（SiGeOI）以及绝缘体上锗（GeOI）中的至少一种。优选地，在一个实施例中，半导体衬底300包括硅基底、形成在硅基底表面处的掩埋层以及形成在掩埋层上的外延层。LDMOS器件30的体区301、漂移区302、深阱区303、栅极305、源区306、漏区307以及体区引出区308等部件或区域可以形成在外延层上。这种结构的半导体衬底300具有良好的隔离效果以及较小的寄生电容。The semiconductor substrate 300 of the LDMOS device 30 provided by the present invention may be silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI). And at least one of germanium on insulator (GeOI). Preferably, in one embodiment, the semiconductor substrate 300 includes a silicon substrate, a buried layer formed at a surface of the silicon substrate, and an epitaxial layer formed on the buried layer. Components or regions such as body region 301, drift region 302, deep well region 303, gate 305, source region 306, drain region 307, and body region lead-out region 308 of LDMOS device 30 may be formed on the epitaxial layer. The semiconductor substrate 300 of such a structure has a good isolation effect and a small parasitic capacitance.
LDMOS器件30的体区301和深阱区303具有第一导电类型，而漂移区302具有不同于体区301和深阱区303的第二导电类型。一般来说，半导体器件中的导电类型主要包括两种，即：P型掺杂和N型掺杂。其中，P型掺杂的主要掺杂元素包括硼（B）和磷（P），而N型掺杂的主要掺杂元素为砷（As）。在一个优选的实施例中，第一导电类型可以为P型掺杂，相应地，第二导电类型可以为N型掺杂。即体区301和深阱区303为P型掺杂，而漂移区302为N型掺杂。The body region 301 and the deep well region 303 of the LDMOS device 30 have a first conductivity type, and the drift region 302 has a second conductivity type different from the body region 301 and the deep well region 303. In general, the types of conductivity in semiconductor devices mainly include two types, namely, P-type doping and N-type doping. Among them, the main doping elements of the P-type doping include boron (B) and phosphorus (P), and the main doping element of the N-type doping is arsenic (As). In a preferred embodiment, the first conductivity type may be a P-type dopant, and accordingly, the second conductivity type may be an N-type dopant. That is, the body region 301 and the deep well region 303 are P-type doped, and the drift region 302 is N-type doped.
掺杂一般是通过注入的方法实现。所需要的掺杂浓度越高，则注入过程中的注入剂量相应地也应该越高。一般来说，漂移区302的掺杂浓度较低，相当于在源区306和漏区307之间形成一个高阻层，能够提高击穿电压，并减小了源区306和漏区307之间的寄生电容，有利于提高频率特性。例如，在一个实施例中，漂移区302的注入剂量可以为1.5×1012~5×1012cm-2。Doping is generally achieved by means of implantation. The higher the doping concentration required, the correspondingly the implant dose during the injection should also be higher. In general, the doping concentration of the drift region 302 is relatively low, which is equivalent to forming a high resistance layer between the source region 306 and the drain region 307, which can increase the breakdown voltage and reduce the source region 306 and the drain region 307. The parasitic capacitance between them helps to improve the frequency characteristics. For example, in one embodiment, the implantation dose of the drift region 302 may be 1.5 x 1012 to 5 x 1012 cm-2.
体区301的掺杂浓度相对较高，注入剂量相应地也高。例如，在一个实施例中，体区301的注入剂量可以为1×1013~3×1013cm-2。The doping concentration of the body region 301 is relatively high, and the implantation dose is correspondingly high. For example, in one embodiment, the implantation dose of the body region 301 may be 1 x 1013 to 3 x 1013 cm-2.
深阱区303的导电类型可以与体区301的导电类型相同，而二者的掺杂浓度可以不同。作为示例，深阱区303的掺杂浓度可以低于体区301的掺杂浓度。相应地，在注入的过程中，深阱区303的注入剂量可以低于体区301的注入剂量。需要说明的是，由于深阱区303的注入深度需要大于体区301的注入深度，因此，在通过离子注入形成深阱区303时，离子的能量较高，而在通过离子注入形成体区301时，离子的能量较低。The conductivity type of the deep well region 303 may be the same as that of the body region 301, and the doping concentrations of the two may be different. As an example, the doping concentration of the deep well region 303 may be lower than the doping concentration of the body region 301. Accordingly, the implantation dose of the deep well region 303 may be lower than the implantation dose of the body region 301 during the implantation process. It should be noted that since the implantation depth of the deep well region 303 needs to be larger than the implantation depth of the body region 301, the energy of ions is higher when the deep well region 303 is formed by ion implantation, and the body region 301 is formed by ion implantation. At the time, the energy of the ions is low.
场氧化层304，形成于漂移区302上方，该场氧化层304的厚度范围为1000~3000埃。The field oxide layer 304 is formed over the drift region 302, and the field oxide layer 304 has a thickness ranging from 1000 to 3000 angstroms.
源区306和漏区307位于场氧化层304的两侧且分别形成于体区301和漂移区302内。源区306和漏区307可以是通过现有的掺杂工艺来形成的。此外，体区301内还形成有体区引出区308，体区引出区308与同样位于体区301内的源区306相互间隔。The source region 306 and the drain region 307 are located on both sides of the field oxide layer 304 and are formed in the body region 301 and the drift region 302, respectively. Source region 306 and drain region 307 may be formed by existing doping processes. In addition, a body region lead-out region 308 is formed in the body region 301, and the body region lead-out region 308 is spaced apart from the source region 306 also located in the body region 301.
栅极305形成于位于体区301和漂移区302之间的半导体衬底110上，并部分覆盖体区301和场氧化层304。可选地，栅极305下方还形成有栅介电层309，该栅介电层309位于源区306和场氧化层304之间。A gate electrode 305 is formed on the semiconductor substrate 110 between the body region 301 and the drift region 302, and partially covers the body region 301 and the field oxide layer 304. Optionally, a gate dielectric layer 309 is formed under the gate 305 , and the gate dielectric layer 309 is located between the source region 306 and the field oxide layer 304 .
本发明的LDMOS器件，在漂移区上方的场氧化层的厚度较薄，增强了多晶硅场板的降低表面电场效应（Reduced Surface Field，Resurf）的作用，将最大碰撞电离点从沟道表面向漂移区体内转移，通过仿真优化及实际数据验证，通过降低漂移区上方场氧化层的厚度来改变碰撞电离的位置，从而有效地提升HCI寿命。In the LDMOS device of the present invention, the thickness of the field oxide layer above the drift region is thinner, and the surface electric field effect of the polysilicon field plate is enhanced (Reduced Surface Field, Resurf), the maximum impact ionization point is transferred from the channel surface to the drift region. Through simulation optimization and actual data verification, the position of the impact ionization is changed by reducing the thickness of the field oxide layer above the drift region, thereby effectively Improve HCI life.
通过对器件（N型）的仿真，发现器件开启后，碰撞电离最强的位置距离场氧化层下表面很近，离半导体衬底表面很接近(临近沟道区)，所以热电子很容易进入沟道上方栅介电层从而影响HCI（热载流子）寿命。要使碰撞电离远离半导体衬底表面，通过仿真优化发现降低漂移区场氧化层厚度可以有效地将最大碰撞电离点由沟道表面向漂移区体内转移。当漂移区上方场氧化层的厚度减少1000Å，碰撞电离最强点离半导体衬底表面距离增加0.03μm。Through the simulation of the device (N-type), it is found that the strongest position of the impact ionization is close to the lower surface of the field oxide layer and close to the surface of the semiconductor substrate (near the channel region), so the hot electrons are easy to enter. The gate dielectric layer above the channel affects the lifetime of the HCI (hot carrier). In order to make the impact ionization away from the surface of the semiconductor substrate, it is found through simulation optimization that reducing the thickness of the field oxide layer in the drift region can effectively transfer the maximum impact ionization point from the channel surface to the drift region. When the thickness of the field oxide layer above the drift region is reduced by 1000 Å, the distance from the strongest point of the impact ionization is increased by 0.03 μm from the surface of the semiconductor substrate.
在一个示例中，对漂移区上方场氧化层的厚度做分片实验，在原有4000Å基础上降低至3000Å。如图4所示，和以往曲线相比ISUB曲线显示峰值变化不明显，整体ISUB值和以前相比，并不是最小的，说明碰撞电离没有明显弱化，但是HCI（热载流子）寿命改善效果却非常明显，如图5所示的HCI测试结果可以看出，例如，18-24V器件HCI都可达标，验证了漂移区场氧化层厚度减薄能使最大碰撞电离点远离沟道，热电子更不容易进入栅介电层。并且从退化量趋势图可以看出退化较小。In one example, a slice experiment was performed on the thickness of the field oxide layer above the drift region, which was reduced to 3000 Å on the basis of the original 4000 Å. As shown in Fig. 4, compared with the previous curve, the ISUB curve shows that the peak change is not obvious, and the overall ISUB value is not the smallest compared with the previous one, indicating that the impact ionization is not significantly weakened, but the HCI (hot carrier) life improvement effect is improved. However, it is very obvious that the HCI test results shown in Figure 5 can be seen. For example, the HCI of the 18-24V device can reach the standard, which verifies that the thickness of the oxide layer in the drift region is thinned to make the maximum impact ionization point away from the channel, and the hot electrons. It is less likely to enter the gate dielectric layer. And it can be seen from the deterioration trend graph that the degradation is small.
综上所述，根据本发明的LDMOS器件，在漂移区上方的场氧化层的厚度较薄，增强了多晶硅场板的RESURF作用，将最大碰撞电离点从沟道表面向漂移区体内转移使其远离沟道，热电子更不容易进入栅氧从而大幅提高器件的HCI（热载流子）寿命，进而提高了器件的可靠性和良率。In summary, according to the LDMOS device of the present invention, the thickness of the field oxide layer above the drift region is thinner, enhancing the RESURF effect of the polysilicon field plate, and transferring the maximum impact ionization point from the channel surface to the drift region. Far from the channel, hot electrons are less likely to enter the gate oxide, which greatly increases the device's HCI (hot carrier) lifetime, thereby increasing device reliability and yield.
如图6所示，本发明提供一种LDMOS器件的制作方法，包括：As shown in FIG. 6, the present invention provides a method for fabricating an LDMOS device, including:
步骤601，提供半导体衬底，在该半导体衬底内注入形成N型掩埋层，在掩埋层上形成外延层。Step 601, providing a semiconductor substrate, implanting an N-type buried layer in the semiconductor substrate, and forming an epitaxial layer on the buried layer.
对于N沟道LDMOS，半导体衬底为P型掺杂，其具体掺杂浓度不受本发明限制。半导体衬底具体地可以通过外延生长形成、也可以为晶圆衬底。For N-channel LDMOS, the semiconductor substrate is P-type doped, and its specific doping concentration is not limited by the present invention. The semiconductor substrate may be specifically formed by epitaxial growth or may be a wafer substrate.
半导体衬底内注入形成有N型掩埋层，掩埋层的注入元素可以有多种。在一个优选的实施例中，掩埋层的注入元素可以为锑（Sb）。在注入N型掩埋层的半导体衬底上制备P型外延层。An N-type buried layer is formed in the semiconductor substrate, and the implanted layer may have a plurality of implant elements. In a preferred embodiment, the implanted element of the buried layer may be germanium (Sb). A P-type epitaxial layer is prepared on a semiconductor substrate implanted with an N-type buried layer.
步骤602，在P型外延层中进行P型离子注入形成P型深阱区。通过离子注入硼制备P型深阱区。作为示例，在一个实施例中，形成深阱区时的离子注入的能量为600KeV~1000KeV。Step 602, performing P-type ion implantation in the P-type epitaxial layer to form a P-type deep well region. A P-type deep well region is prepared by ion implantation of boron. As an example, in one embodiment, the energy of ion implantation when forming the deep well region is 600 KeV to 1000 KeV.
步骤603，在P型深阱区的表面内构图形成体区和漂移区。通过离子注入N型杂质（例如：磷）生成N型漂移区。体区与深阱区具有相同的掺杂类型，均为P型。Step 603, patterning the body region and the drift region in the surface of the P-type deep well region. An N-type drift region is generated by ion implantation of an N-type impurity (for example, phosphorus). The body region and the deep well region have the same doping type, both of which are P-type.
步骤604，在漂移区上方形成场氧化层。可采用LOCOS工艺局部氧化形成场氧化层，在本实施例中，将场氧化层的厚度减薄至少1000埃，使其厚度范围为1000~3000埃。Step 604, forming a field oxide layer over the drift region. The field oxide layer may be formed by local oxidation of the LOCOS process. In this embodiment, the thickness of the field oxide layer is reduced by at least 1000 angstroms to a thickness ranging from 1000 to 3000 angstroms.
步骤605，在场氧化层的两侧且分别于体区和漂移区内形成源区和漏区。Step 605, forming source and drain regions on both sides of the field oxide layer and in the body region and the drift region, respectively.
在本实施例中，源区和漏区通过对衬底构图N型掺杂形成N+阱来形成，源区和漏区的掺杂浓度可以相同，因此，二者可以同步地掺杂形成。源区和漏区之上可以分别形成源极S和漏极D；源极S用于引出源区，二者被定义为LDMOS的源端；漏极D用于引出漏区，二者被定义为LDMOS的漏端。In the present embodiment, the source and drain regions are formed by patterning the N-type doping of the substrate to form an N+ well, and the doping concentrations of the source and drain regions may be the same, and thus, the two may be doped simultaneously. A source S and a drain D may be formed respectively above the source and drain regions; a source S is used to extract the source region, and two are defined as source terminals of the LDMOS; and a drain D is used to lead the drain region, the two are defined It is the drain of LDMOS.
步骤606，在源区和场氧化层之间形成栅介电层。具体地，其可以通过局部氧化形成栅介电层，当然，也可以通过薄膜沉积等方法构图形成栅介电层。Step 606, forming a gate dielectric layer between the source region and the field oxide layer. Specifically, it may form a gate dielectric layer by local oxidation, and of course, a gate dielectric layer may be patterned by a method such as thin film deposition.
步骤607，在栅介电层上形成栅极，该栅极部分延伸至与栅介电层相邻的场氧化层的上方。栅极具体材料不受本发明限制，例如，其可以为低电阻率的多晶硅构图形成，也可以通过化学气相沉积、物理气相沉积、磁控溅射等方法沉积形成。Step 607, forming a gate on the gate dielectric layer, the gate portion extending over the field oxide layer adjacent to the gate dielectric layer. The gate specific material is not limited by the present invention, for example, it may be formed by low resistivity polysilicon patterning, or may be deposited by chemical vapor deposition, physical vapor deposition, magnetron sputtering, or the like.
尽管本发明实施例中尽管只示出了N型LDMOS的制作方法，但其也可适用于P型LDMOS，在此不作赘述。Although the method for fabricating the N-type LDMOS is shown in the embodiment of the present invention, it can also be applied to the P-type LDMOS, and details are not described herein.
综上所述，根据本发明的制作方法，通过降低漂移区场氧化层厚度增强多晶硅场板的RESURF作用，将最大碰撞电离点从沟道表面向漂移区体内转移使其远离沟道，热电子更不容易进入栅氧从而大幅提高器件的HCI（热载流子）寿命，进而提高了器件的可靠性和良率。In summary, according to the fabrication method of the present invention, the maximum impact ionization point is transferred from the channel surface to the drift region away from the channel by reducing the thickness of the drift field oxide layer and enhancing the RESURF effect of the polysilicon field plate. It is less likely to enter the gate oxide to greatly increase the device's HCI (hot carrier) lifetime, thereby increasing device reliability and yield.
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。The present invention has been described by the above-described embodiments, but it should be understood that the above-described embodiments are only for the purpose of illustration and description. Further, those skilled in the art can understand that the present invention is not limited to the above embodiments, and various modifications and changes can be made according to the teachings of the present invention. These modifications and modifications are all claimed in the present invention. Within the scope. The scope of the invention is defined by the appended claims and their equivalents.

Claims (8)

  1. 一种LDMOS器件，包括：An LDMOS device, including:
    半导体衬底;Semiconductor substrate
    体区和漂移区，形成于所述半导体衬底的表面且相互间隔，所述体区和所述漂移区分别具有第一导电类型和第二导电类型；a body region and a drift region formed on a surface of the semiconductor substrate and spaced apart from each other, the body region and the drift region having a first conductivity type and a second conductivity type, respectively;
    场氧化层，形成于所述漂移区上方，所述场氧化层的厚度范围为1000~3000埃；a field oxide layer formed over the drift region, the field oxide layer having a thickness ranging from 1000 to 3000 angstroms;
    源区和漏区，位于所述场氧化层的两侧并分别形成于所述体区和所述漂移区内；a source region and a drain region are located on both sides of the field oxide layer and are respectively formed in the body region and the drift region;
    体区引出区，形成于所述体区内且与所述源区间隔开；及a body region lead-out region formed in the body region and spaced apart from the source region; and
    栅极，形成于位于所述体区和所述漂移区之间的所述半导体衬底上，并部分覆盖所述体区和所述场氧化层。A gate electrode is formed on the semiconductor substrate between the body region and the drift region and partially covers the body region and the field oxide layer.
  2. 根据权利要求1所述的LDMOS器件，其特征在于，所述第一导电类型为P型，所述第二导电类型为N型。The LDMOS device according to claim 1, wherein said first conductivity type is a P type and said second conductivity type is an N type.
  3. 根据权利要求1所述的LDMOS器件，其特征在于，还包括环绕所述体区和漂移区的深阱区，所述深阱区具有所述第一导电类型。The LDMOS device of claim 1 further comprising a deep well region surrounding said body region and said drift region, said deep well region having said first conductivity type.
  4. 根据权利要求1所述的LDMOS器件，其特征在于，所述LDMOS器件为HVLDMOS器件。The LDMOS device of claim 1 wherein said LDMOS device is a HVLDMOS device.
  5. 根据权利要求1所述的LDMOS器件，其特征在于，所述半导体衬底包括硅基底、形成于所述硅基底表面的掩埋层以及形成于所述掩埋层上的外延层。The LDMOS device according to claim 1, wherein said semiconductor substrate comprises a silicon substrate, a buried layer formed on a surface of said silicon substrate, and an epitaxial layer formed on said buried layer.
  6. 根据权利要求1所述的LDMOS器件，其特征在于，所述栅极下方还形成有栅介电层，所述栅介电层位于所述源区和所述场氧化层之间。The LDMOS device of claim 1 wherein a gate dielectric layer is further formed under the gate, the gate dielectric layer being between the source region and the field oxide layer.
  7. 一种LDMOS器件的制作方法，包括：A method for fabricating an LDMOS device, comprising:
    提供半导体衬底，在所述半导体衬底内注入形成N型掩埋层，在所述N型掩埋层上形成P型外延层；Providing a semiconductor substrate, implanting an N-type buried layer in the semiconductor substrate, and forming a P-type epitaxial layer on the N-type buried layer;
    在所述P型外延层中进行P型离子注入形成P型深阱区；Performing P-type ion implantation in the P-type epitaxial layer to form a P-type deep well region;
    在所述P型深阱区的表面内构图形成体区和漂移区；Forming a body region and a drift region in a surface of the P-type deep well region;
    在所述漂移区上方形成场氧化层，所述场氧化层的厚度范围为1000~3000埃；Forming a field oxide layer over the drift region, the field oxide layer having a thickness ranging from 1000 to 3000 angstroms;
    在所述场氧化层的两侧并分别于所述体区和所述漂移区内形成源区和漏区；Forming source and drain regions on both sides of the field oxide layer and respectively in the body region and the drift region;
    在所述源区和所述场氧化层之间形成栅介电层；及Forming a gate dielectric layer between the source region and the field oxide layer; and
    在所述栅介电层上形成栅极，所述栅极部分延伸至与所述栅介电层相邻的所述场氧化层的上方。A gate is formed on the gate dielectric layer, the gate portion extending over the field oxide layer adjacent to the gate dielectric layer.
  8. 根据权利要求7所述的方法，其特征在于，采用LOCOS工艺局部氧化形成所述场氧化层。The method of claim 7 wherein said field oxide layer is formed by local oxidation using a LOCOS process.
PCT/CN2015/087333 2014-08-22 2015-08-18 Ldmos device and manufacturing method thereof WO2016026422A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113161422A (en) * 2021-05-19 2021-07-23 电子科技大学 Low-radiation leakage high-voltage LDMOS device structure

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107527857B (en) * 2016-06-22 2020-06-09 中芯国际集成电路制造(上海)有限公司 Semiconductor device, manufacturing method thereof and electronic device
CN111446299A (en) * 2020-05-11 2020-07-24 杰华特微电子（杭州）有限公司 L DMOS device and manufacturing method thereof
CN111785639B (en) * 2020-08-26 2024-02-02 上海华虹宏力半导体制造有限公司 LDMOS transistor and preparation method thereof
CN113782611B (en) * 2021-09-26 2022-06-14 深圳基本半导体有限公司 SiC LDMOS device and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6468837B1 (en) * 1997-11-25 2002-10-22 Texas Instruments Incorporated Reduced surface field device having an extended field plate and method for forming the same
CN1755944A (en) * 2004-10-01 2006-04-05 恩益禧电子股份有限公司 Semiconductor device including an LDMOS transistor
CN102709325A (en) * 2012-06-25 2012-10-03 电子科技大学 High-voltage lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS) device
CN102931089A (en) * 2011-08-10 2013-02-13 无锡华润上华半导体有限公司 LDMOS (Laterally Diffused Metal Oxide Semiconductor) and manufacturing method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103943548A (en) * 2013-01-23 2014-07-23 无锡华润上华半导体有限公司 Manufacturing method of semiconductor device of discrete field oxide structure
CN103489916A (en) * 2013-09-24 2014-01-01 无锡市晶源微电子有限公司 N type LDMOS of ladder gate oxide layer and active drift region structure and manufacturing method of N type LDMOS

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6468837B1 (en) * 1997-11-25 2002-10-22 Texas Instruments Incorporated Reduced surface field device having an extended field plate and method for forming the same
CN1755944A (en) * 2004-10-01 2006-04-05 恩益禧电子股份有限公司 Semiconductor device including an LDMOS transistor
CN102931089A (en) * 2011-08-10 2013-02-13 无锡华润上华半导体有限公司 LDMOS (Laterally Diffused Metal Oxide Semiconductor) and manufacturing method thereof
CN102709325A (en) * 2012-06-25 2012-10-03 电子科技大学 High-voltage lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS) device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113161422A (en) * 2021-05-19 2021-07-23 电子科技大学 Low-radiation leakage high-voltage LDMOS device structure
CN113161422B (en) * 2021-05-19 2022-11-04 电子科技大学 Low-radiation electric leakage high-voltage LDMOS device structure

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