CN113140617A - 一种大功率半导体器件及其制备方法 - Google Patents

一种大功率半导体器件及其制备方法 Download PDF

Info

Publication number
CN113140617A
CN113140617A CN202110280013.9A CN202110280013A CN113140617A CN 113140617 A CN113140617 A CN 113140617A CN 202110280013 A CN202110280013 A CN 202110280013A CN 113140617 A CN113140617 A CN 113140617A
Authority
CN
China
Prior art keywords
manufacturing
buried layer
semiconductor device
chip
laser
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202110280013.9A
Other languages
English (en)
Other versions
CN113140617B (zh
Inventor
田亮
施俊
刘昊
邱凯兵
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanruilianyan Semiconductor Co ltd
NARI Group Corp
Original Assignee
Nanruilianyan Semiconductor Co ltd
NARI Group Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanruilianyan Semiconductor Co ltd, NARI Group Corp filed Critical Nanruilianyan Semiconductor Co ltd
Priority to CN202110280013.9A priority Critical patent/CN113140617B/zh
Publication of CN113140617A publication Critical patent/CN113140617A/zh
Application granted granted Critical
Publication of CN113140617B publication Critical patent/CN113140617B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623Buried supplementary region, e.g. buried guard ring
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)

Abstract

本发明公开了半导体器件技术领域的一种大功率半导体器件及其制备方法,降低了裂片过程中出现碎片的几率,提高了产品的合格率和产量。包括:在芯片第一表面进行各功能模块的制作,然后在第一表面的划片道处制作第一埋层;在芯片第二表面进行各功能模块的制作,然后在第二表面上制作与第一埋层相对的第二埋层;对芯片进行裂片,使芯片沿第一埋层和第二埋层产生裂痕,进而分割成若干个独立的半导体器件。

Description

一种大功率半导体器件及其制备方法
技术领域
本发明属于半导体器件技术领域,具体涉及一种大功率半导体器件及其制备方法。
背景技术
当前,电力电子器件的使用条件越来越恶劣,要适应高频、大功率、耐高温、抗辐照等特殊环境。为了满足未来电子器件需求,必须采用新的材料,以便最大限度地提高电子元器件的内在性能。近年来,新发展起来的第三代半导体材料--宽禁带半导体材料,包括碳化硅和氮化镓,该类材料具有热导率高、电子饱和速度高、击穿电压高、介电常数低等特点,这就从理论上保证了其较宽的适用范围。目前在半导体功率器件后道的主要方式是以硬接触的方式进行磨片,磨片时受力不均匀会导致碎片,造成残次品率高,产量低等问题。
发明内容
为解决现有技术中的不足,本发明提供一种大功率半导体器件及其制备方法,降低了裂片过程中出现碎片的几率,提高了产品的合格率和产量。
为达到上述目的,本发明所采用的技术方案是:
第一方面,提供一种半导体器件的制备方法,包括:在芯片第一表面进行各功能模块的制作,然后在第一表面的划片道处制作第一埋层;在芯片第二表面进行各功能模块的制作,然后在第二表面上制作与第一埋层相对的第二埋层;对芯片进行裂片,使芯片沿第一埋层和第二埋层产生裂痕,进而分割成若干个独立的半导体器件。
进一步地,所述芯片包括衬底以及生长在衬底表面上的外延层。
进一步地,所述在芯片第一表面进行各功能模块的制作,包括在所述外延层的表面制作钝化层和金属电极。
进一步地,所述在芯片第二表面进行各功能模块的制作,包括采用减薄工艺,在衬底表面进行材料减薄;进行背面金属制备,形成欧姆接触金属;对背面金属及半导体接触面进行激光退火;背面金属加厚。
进一步地,所述衬底的材质包括碳化硅、氮化镓、金刚石、氧化镓、氮化铝、硅和砷化镓。
进一步地,所述第一埋层的深度是芯片厚度的1/2至1/8。
进一步地,制作所述第一埋层和/或所述第二埋层的方法包括刻蚀、激光划片、机械划片和激光改质埋层。
进一步地,所述激光划片中采用的激光包括紫外、深紫外激光光源或者红外激光光源,激光光源的波长小于等于355nm,或者大于620nm。
进一步地,所述半导体器件包括肖特基势垒二极管、金属氧化物场效应晶体管、金属半导体场效应晶体管、绝缘栅双极晶体管、高电子迁移率晶体管和发光二极管。
第二方面,提供一种半导体器件,所述半导体器件采用第一方面所述的半导体器件的制备方法制备而成。
与现有技术相比,本发明所达到的有益效果:
(1)本发明通过在芯片的第一表面制作第一埋层,在芯片的第二表面制作与第一埋层相对应的第二埋层,使得在裂片过程中,裂痕可以沿第一埋层和第二埋层延伸,降低了裂片过程中出现碎片的几率,提高了产品的合格率和产量;
(2)本发明通过采用激光划片的方式制作第一埋层和第二埋层,避免了传统制作工艺中以硬接触的方式进行磨片,磨片时受力不均匀导致碎片,造成残次品率高,产量低等问题。
附图说明
图1是本发明实施例中在芯片第一表面制作各功能模块后的局部状态示意图;
图2是本发明实施例中在芯片第一表面制作第一埋层的局部状态示意图;
图3是本发明实施例中在芯片第二表面制作各功能模块后的局部状态示意图;
图4是本发明实施例中在芯片第二表面制作第二埋层的局部状态示意图;
图5是本发明实施例中对芯片进行裂片的状态示意图;
图6是本发明实施例中对芯片扩片后的状态示意图。
具体实施方式
下面结合附图对本发明作进一步描述。以下实施例仅用于更加清楚地说明本发明的技术方案,而不能以此来限制本发明的保护范围。
实施例一:
如图1~图6所示,一种半导体器件的制备方法,包括:在芯片第一表面进行各功能模块的制作,然后在第一表面的划片道处制作第一埋层;在芯片第二表面进行各功能模块的制作,然后在第二表面上制作与第一埋层相对的第二埋层;对芯片进行裂片,使芯片沿第一埋层和第二埋层产生裂痕,进而分割成独立的半导体器件。
本实施例中,芯片包括衬底2以及生长在衬底2表面上的外延层1。在芯片第一表面进行各功能模块的制作,包括在外延层1的表面制作钝化层4和金属电极5。
本实施例是在正面器件(指芯片第一表面侧)主结构已经制备完毕的情况下进行的。正面工艺包括:标记制备、注入区域制备、正面保护层制备、金属电极5制备和钝化层4制备,预留划片道6等。
1、正面(指芯片第一表面侧)状态
背面(指芯片第二表面侧)加工前,正面需要进行第一埋层61制备,具体方式为:经过光刻(激光刻蚀),刻蚀划片道6,刻蚀出沟槽(即第一埋层61,图2~图4中,R表示激光照射方向)比划片道6窄,约为划片道6宽度的1/3-1/6,深度约为芯片厚度的1/2--1/8。1/2设置主要考虑正面挖槽时需要保持未挖槽材料的刚性,1/8是考虑挖槽效果,太浅不能体现挖槽带来的工艺效果。
2、背面加工
在背面进行背面金属7薄层沉积,并在正面贴蓝膜3,蓝膜3在样品加工时起承载、固定样品的作用,有张力。
采用减薄工艺,在衬底2表面进行材料减薄;进行背面金属7制备,磨片、抛光形成欧姆接触金属;对背面金属7及半导体接触面进行激光退火;背面金属加厚。将划片道6对应处的背面金属7去掉形成金属槽,在金属槽内进行激光划片或者隐形激光划片或者砂轮划片。
将芯片背面朝上放入激光切割机中,抽真空吸住蓝膜3从而固定住芯片。调整切割机的参数,进行激光退火并完成背面金属7沉积加厚,使用激光划片机完成背面对应划片道6处的金属去除,漏出碳化硅(衬底2的材料)界面,并在开槽处进行激光划片加工,即制作出与第一埋层61相对的第二埋层62。
3、裂片
对芯片进行裂片,使芯片沿第一埋层61和第二埋层62产生裂痕,进而分割成独立的半导体器件,如图5所示。
将芯片放入裂片机,沿着激光开槽和激光划片划痕(即第一埋层61和第二埋层62),对准裂片载台,裂片机上的裂片刀落到划痕上,裂片刀加压力将芯片裂开。
4、扩片
将裂片完成后的芯片放在扩片机上进行扩片,独立的芯片被彻底分开,如图6所示(图6中每个半导体器件在裂片、扩片前的不同阶段的状态如图1~图4所示)。
本实施例中,衬底的材质包括碳化硅、氮化镓、金刚石、氧化镓、氮化铝、硅和砷化镓。制作第一埋层和/或第二埋层的方法包括刻蚀、激光划片、机械划片和激光改质埋层。激光划片中采用的激光包括紫外、深紫外激光光源或者红外激光光源,激光光源的波长小于等于355nm,或者大于620nm,波长需要考虑材料本身吸收的问题,紫外和红外易于材料吸收能量。激光束所划的沟槽深度为1um至300um。本实施例所述方法可以适用于半导体器件包括肖特基势垒二极管、金属氧化物场效应晶体管、金属半导体场效应晶体管、绝缘栅双极晶体管、高电子迁移率晶体管和发光二极管等大功率电力电子器件的制作,大功率电力电子器件的厚度为80um至700um。
本实施例通过在芯片的第一表面制作第一埋层,在芯片的第二表面制作与第一埋层相对应的第二埋层,使得在裂片过程中,裂痕可以沿第一埋层和第二埋层延伸,降低了裂片过程中出现碎片的几率,提高了产品的合格率和产量;通过采用激光划片的方式制作第一埋层和第二埋层,避免了传统制作工艺中以硬接触的方式进行磨片,磨片时受力不均匀导致碎片,造成残次品率高,产量低等问题。
实施例二:
基于实施例一所述的半导体器件的制备方法,本实施例提供一种半导体器件,所述半导体器件采用实施例一所述的半导体器件的制备方法制备而成。
以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明技术原理的前提下,还可以做出若干改进和变形,这些改进和变形也应视为本发明的保护范围。

Claims (10)

1.一种半导体器件的制备方法,其特征是,包括:
在芯片第一表面进行各功能模块的制作,然后在第一表面的划片道处制作第一埋层;
在芯片第二表面进行各功能模块的制作,然后在第二表面上制作与第一埋层相对的第二埋层;
对芯片进行裂片,使芯片沿第一埋层和第二埋层产生裂痕,进而分割成若干个独立的半导体器件。
2.根据权利要求1所述的半导体器件的制备方法,其特征是,所述芯片包括衬底以及生长在衬底表面上的外延层。
3.根据权利要求2所述的半导体器件的制备方法,其特征是,所述在芯片第一表面进行各功能模块的制作,包括在所述外延层的表面制作钝化层和金属电极。
4.根据权利要求2所述的半导体器件的制备方法,其特征是,所述在芯片第二表面进行各功能模块的制作,包括采用减薄工艺,在衬底表面进行材料减薄;进行背面金属制备,形成欧姆接触金属;对背面金属及半导体接触面进行激光退火;背面金属加厚。
5.根据权利要求2所述的半导体器件的制备方法,其特征是,所述衬底的材质包括碳化硅、氮化镓、金刚石、氧化镓、氮化铝、硅和砷化镓。
6.根据权利要求1所述的半导体器件的制备方法,其特征是,所述第一埋层的深度是芯片厚度的1/2至1/8。
7.根据权利要求1所述的半导体器件的制备方法,其特征是,制作所述第一埋层和/或所述第二埋层的方法包括刻蚀、激光划片、机械划片和激光改质埋层。
8.根据权利要求7所述的半导体器件的制备方法,其特征是,所述激光划片中采用的激光包括紫外、深紫外激光光源或者红外激光光源,激光光源的波长小于等于355nm,或者大于620nm。
9.根据权利要求1所述的半导体器件的制备方法,其特征是,所述半导体器件包括肖特基势垒二极管、金属氧化物场效应晶体管、金属半导体场效应晶体管、绝缘栅双极晶体管、高电子迁移率晶体管和发光二极管。
10.一种半导体器件,其特征是,所述半导体器件采用权利要求1~9任一项所述的半导体器件的制备方法制备而成。
CN202110280013.9A 2021-03-16 2021-03-16 一种大功率半导体器件及其制备方法 Active CN113140617B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110280013.9A CN113140617B (zh) 2021-03-16 2021-03-16 一种大功率半导体器件及其制备方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110280013.9A CN113140617B (zh) 2021-03-16 2021-03-16 一种大功率半导体器件及其制备方法

Publications (2)

Publication Number Publication Date
CN113140617A true CN113140617A (zh) 2021-07-20
CN113140617B CN113140617B (zh) 2024-05-14

Family

ID=76811152

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110280013.9A Active CN113140617B (zh) 2021-03-16 2021-03-16 一种大功率半导体器件及其制备方法

Country Status (1)

Country Link
CN (1) CN113140617B (zh)

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101055908A (zh) * 2006-04-14 2007-10-17 大连路美芯片科技有限公司 一种蓝宝石衬底上的发光二极管芯片的制作方法
US20120329246A1 (en) * 2011-06-24 2012-12-27 Electro Scientific Industries, Inc. Etching a laser-cut semiconductor before dicing a die attach film (daf) or other material layer
CN102881783A (zh) * 2012-10-11 2013-01-16 施科特光电材料(昆山)有限公司 一种深刻蚀切割发光二极管芯片的方法
US20130337634A1 (en) * 2011-10-21 2013-12-19 Win Semiconductors Corp. Fabrication method for producing semiconductor chips with enhanced die strength
US8883614B1 (en) * 2013-05-22 2014-11-11 Applied Materials, Inc. Wafer dicing with wide kerf by laser scribing and plasma etching hybrid approach
CN104599960A (zh) * 2014-12-29 2015-05-06 国家电网公司 一种大功率电力电子器件晶圆激光切割方法
CN105226143A (zh) * 2015-09-29 2016-01-06 山东浪潮华光光电子股份有限公司 一种GaAs基LED芯片的切割方法
CN107464777A (zh) * 2016-06-02 2017-12-12 苏州能讯高能半导体有限公司 半导体晶圆及其制造方法
CN108381042A (zh) * 2018-03-23 2018-08-10 伊欧激光科技(苏州)有限公司 晶片加工系统及晶片加工方法
CN111009463A (zh) * 2019-11-22 2020-04-14 中国电子科技集团公司第五十五研究所 一种使SiC芯片激光划片后背面金属整齐分离的方法

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101055908A (zh) * 2006-04-14 2007-10-17 大连路美芯片科技有限公司 一种蓝宝石衬底上的发光二极管芯片的制作方法
US20120329246A1 (en) * 2011-06-24 2012-12-27 Electro Scientific Industries, Inc. Etching a laser-cut semiconductor before dicing a die attach film (daf) or other material layer
US20130337634A1 (en) * 2011-10-21 2013-12-19 Win Semiconductors Corp. Fabrication method for producing semiconductor chips with enhanced die strength
CN102881783A (zh) * 2012-10-11 2013-01-16 施科特光电材料(昆山)有限公司 一种深刻蚀切割发光二极管芯片的方法
US8883614B1 (en) * 2013-05-22 2014-11-11 Applied Materials, Inc. Wafer dicing with wide kerf by laser scribing and plasma etching hybrid approach
CN104599960A (zh) * 2014-12-29 2015-05-06 国家电网公司 一种大功率电力电子器件晶圆激光切割方法
CN105226143A (zh) * 2015-09-29 2016-01-06 山东浪潮华光光电子股份有限公司 一种GaAs基LED芯片的切割方法
CN107464777A (zh) * 2016-06-02 2017-12-12 苏州能讯高能半导体有限公司 半导体晶圆及其制造方法
CN108381042A (zh) * 2018-03-23 2018-08-10 伊欧激光科技(苏州)有限公司 晶片加工系统及晶片加工方法
CN111009463A (zh) * 2019-11-22 2020-04-14 中国电子科技集团公司第五十五研究所 一种使SiC芯片激光划片后背面金属整齐分离的方法

Also Published As

Publication number Publication date
CN113140617B (zh) 2024-05-14

Similar Documents

Publication Publication Date Title
JP3230572B2 (ja) 窒化物系化合物半導体素子の製造方法及び半導体発光素子
US8216867B2 (en) Front end scribing of light emitting diode (LED) wafers and resulting devices
CN1134827C (zh) 具有以锯法完成的台面结构的半导体芯片
JP2780618B2 (ja) 窒化ガリウム系化合物半導体チップの製造方法
JPH11163403A (ja) 窒化物半導体素子の製造方法
JP2009032970A (ja) 窒化物半導体素子の製造方法
CN104599960A (zh) 一种大功率电力电子器件晶圆激光切割方法
US11712749B2 (en) Parent substrate, wafer composite and methods of manufacturing crystalline substrates and semiconductor devices
JP2748355B2 (ja) 窒化ガリウム系化合物半導体チップの製造方法
JP2015146406A (ja) 縦型電子デバイスの製造方法および縦型電子デバイス
JP2003151921A (ja) 化合物半導体とその製造方法
JP2005236017A (ja) 太陽電池セルの製造方法
JPH10125958A (ja) 窒化ガリウム系化合物半導体チップの製造方法
JP3227287B2 (ja) 窒化ガリウム系化合物半導体チップの製造方法と窒化ガリウム系化合物半導体素子
CN109427563B (zh) 碳化硅器件和用于制造碳化硅器件的方法
JP2009224511A (ja) 半導体装置の製造方法
CN108788473B (zh) 化合物半导体装置及其制造方法以及树脂密封型半导体装置
CN104979161A (zh) 半导体器件的制作方法及ti-igbt的制作方法
CN113140617A (zh) 一种大功率半导体器件及其制备方法
CN114220740B (zh) 一种氮化镓衬底剥离方法
EP4057323B1 (en) Method for thinning a silicon carbide substrate
US7696068B2 (en) Method for manufacturing vertical light-emitting diode
US11302538B2 (en) Semiconductor device manufacturing method
KR101308127B1 (ko) 발광 다이오드의 제조 방법
JP2012039128A (ja) 窒化物半導体素子の製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant