CN113140564A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN113140564A
CN113140564A CN202011392773.0A CN202011392773A CN113140564A CN 113140564 A CN113140564 A CN 113140564A CN 202011392773 A CN202011392773 A CN 202011392773A CN 113140564 A CN113140564 A CN 113140564A
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Prior art keywords
layer
gate
dielectric layer
semiconductor
channel
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CN202011392773.0A
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Inventor
林大钧
潘国华
廖忠志
吴显扬
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN113140564A publication Critical patent/CN113140564A/zh
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    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
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    • H01—ELECTRIC ELEMENTS
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET

Abstract

半导体装置包括基板、输入/输出装置位于基板上、以及核心装置位于基板上。输入/输出装置包括第一栅极结构，其具有界面层；第一高介电常数的介电堆叠，位于界面层上；以及导电层，位于第一高介电常数的介电堆叠上并与其物理接触。核心装置包括第二栅极结构，其具有界面层；第二高介电常数的介电堆叠，位于界面层上，以及导电层，位于第二高介电常数的介电堆叠上并与其物理接触。第一高介电常数的介电堆叠包括第二高介电常数的介电堆叠与第三介电层。

Description

半导体装置
技术领域
本发明实施例涉及半导体装置如集成电路，更特别地涉及具有不同栅极介电层厚度的晶体管的半导体装置。
背景技术
半导体集成电路产业已经历指数成长。集成电路材料与设计的技术进展，使每一代比前一代具有更小且更复杂的电路。在集成电路演进中，功能密度(如单位芯片面积的内连线装置数目)通常随着几何尺寸(如采用的制作工艺所能产生的最小构件或线路)缩小而增加。尺寸缩小通常有利于增加产能与降低相关成本。尺寸缩小亦会增加处理与制造集成电路的复杂度。
举例来说，随着集成电路技术潮更小的技术节点发展，已导入多栅极装置以增加栅极-通道耦合、减少关闭状态电流、并减少短通道效应，进而改善栅极控制。多栅极装置通常视作栅极结构或其部分位于通道区的多侧上的装置。鳍状场效晶体管与全绕式栅极晶体管(均视作非平面晶体管)为多栅极装置的例子，其于高效能与低漏电流应用中越来越普及且越来越有前景。鳍状场效晶体管具有隆起的通道，且栅极覆盖通道的多侧(比如栅极位于自基板延伸的半导体材料的鳍状物的上表面与侧壁上)。与平面晶体管相较，这些设置可更加地控制通道并大幅减少短通道效应(特别是通过减少次临界漏电流，比如减少关闭状态中的鳍状场效晶体管的源极与漏极之间的耦合)。全绕式栅极晶体管的栅极结构可部分或完全延伸于通道区周围，以接触通道区的所有侧部。可自纳米线、纳米片、其他纳米结构、及/或其他合适结构形成全绕式栅极晶体管的通道区。在一些实施方式中，这些通道区包括垂直堆叠的多个纳米线(其水平延伸以提供水平取向的通道)。
集成电路装置包括的晶体管可用于不同功能，比如输入/输出功能与核心功能。这些不同功能需要不同结构的晶体管。以类似工艺与类似工艺容许范围制作不同晶体管，有利于降低成本并改善良率。虽然现存的全绕式栅极晶体管与工艺通常适用于其发展目的，但无法完全符合所有方面的需求。举例来说，相邻纳米线(或纳米片、其他纳米结构、及/或其他合适结构)之间的垂直空间会限制栅极介电层的厚度。为了此理由，全绕式栅极晶体管可能不适于需要厚栅极介电层的应用，比如用于输入/输出功能。此外，不同核心功能如高速应用与低功率(及/或低漏电流)应用，倾向于采用不同的栅极介电层厚度以用于全绕式栅极晶体管。如此一来，如何持续缩小栅极堆叠的尺寸以用于不同应用的输入/输出装置与核心装置(具有不同厚度的栅极介电层)，是半导体产业需面对的挑战。本发明实施例有助于解决上述问题与其他相关问题。
发明内容
本发明一例示性的例子关于半导体装置。半导体装置包括：基板，具有第一区与第二区；第一晶体管，位于第一区中，第一晶体管具有第一通道、第一栅极介电层位于第一通道上、以及第一栅极层位于第一栅极介电层上；第二晶体管，位于第一区中，第二晶体管具有第二通道、第二栅极介电层位于第二通道上、以及第二栅极层位于第二栅极介电层上；以及第三晶体管，位于第二区中，第三晶体管具有第三通道、第三栅极介电层位于第三通道上、以及第三栅极层位于第三栅极介电层上，其中第一栅极介电层的第一厚度小于第二栅极介电层的第二厚度，其中第二栅极介电层的第二厚度小于第三栅极介电层的第三厚度。
本发明另一例示性的例子关于半导体装置。半导体装置包括第一全绕式栅极晶体管，包括：多个第一通道膜，第一界面层包覆第一通道膜，第一高介电常数的介电层包覆第一界面层，以及第一栅极层包覆第一高介电常数的介电层；第二全绕式栅极晶体管，包括：多个第二通道膜，第二界面层包覆第二通道膜，第二高介电常数的介电层包覆第二界面层，以及第二栅极层包覆第二高介电常数的介电层；以及鳍状场效晶体管，包括：鳍状物通道，第三界面层位于鳍状物通道上；第三高介电常数的介电层位于第三界面层上，以及第三栅极层位于第三高介电常数的介电层上，其中第一界面层比第二界面层薄，而第二界面层比第三界面层薄。
本发明另一例示性的例子关于半导体装置的形成方法。方法包括提供结构，其具有多个第一通道膜、多个第二通道膜、与鳍状物，其中第一通道膜与第二通道膜位于集成电路的核心装置区中，而鳍状物位于集成电路的输入/输出装置区中；形成第一氧化物层以包覆第一通道膜与第二通道膜并位于鳍状物上；自第一通道膜与第二通道膜移除第一氧化物层；形成第二氧化物层以包覆第一通道膜与第二通道膜；形成高介电常数的介电层以包复核心装置区中的第二氧化物层并位于输入/输出装置区中的第一氧化物层上；形成厚度调整层以包覆之前包覆第一通道膜的高介电常数的介电层；进行退火工艺以调整包覆第一通道膜的第二氧化物层的厚度；移除厚度调整层的至少一部分；以及形成栅极层以包复核心装置区中的高介电常数的介电层并位于输入/输出装置区中的高介电常数的介电层上。
附图说明
图1A及图1B是本发明实施例中，半导体装置的方框图与输入/输出与核心装置所用的三种栅极堆叠的部分剖视图。
图2A、图2B、图2C、图2D、图2E、及图2F是本发明实施例中，形成图1A及图1B所示的装置的方法的流程图。
图3是本发明实施例中，半导体装置的透视图。
图4A、图4B、图5A、图5B、图6A、图6B、图7、图8、图9、图10、图11、图12、图13、图14、图15、图16、图17、图18、图19、图20、图21、及图22是本发明多种实施例中，图2A至图2F的方法的制作工艺时的半导体结构的剖视图。
附图标记说明:
A-A、B-B、C-C：剖面
TIL1、TIL2、TIL3：厚度
10、200：集成电路
12、202：核心区
14、204：输入/输出区
16、22：装置区
18、20：全绕式栅极装置
24：鳍状场效晶体管装置
26：通道膜
27、208：基板
28a、28b、28c、250、250a、250b、250c：栅极介电层
30a、30b、30c、230、252a、252b：界面层
32a、32b、32c、254、254a、254b、254c：高介电常数的介电层
34、212a、212b、212c：鳍状物
36、210：隔离结构
100：方法
102、104、106、108、110、112、114、116、118、120、122、124、126、128、130、132：步骤
206a、206b：全绕式栅极核心装置结构
206c：鳍状场效晶体管输入/输出装置结构
216：虚置栅极结构
220、222：半导体层
232：虚置栅极
234：第一栅极硬遮罩层
236：第二栅极硬遮罩层
238：栅极间隔物
240：源极/漏极结构
242：接点蚀刻停止层
244：层间介电层
246：栅极沟槽
248、266、282：遮罩层
260：厚度调整层
262：除氧层
264：盖层
270：退火工艺
271：部分
272：栅极层
274：氧原子的移动方向
276：非晶硅层
284：布植工艺
具体实施方式
下述详细描述可搭配附图说明，以利理解本发明的各方面。值得注意的是，各种结构仅用于说明目的而未按比例绘制，如本业常态。实际上为了清楚说明，可任意增加或减少各种结构的尺寸。
下述内容提供的不同实施例或例子可实施本发明实施例的不同结构。特定构件与排列的实施例是用以简化本公开而非局限本发明。举例来说，形成第一构件于第二构件上的叙述包含两者直接接触，或两者之间隔有其他额外构件而非直接接触。此外，本发明的多种实例可重复采用相同标号以求简洁，但多种实施例及/或设置中具有相同标号的元件并不必然具有相同的对应关系。
此外，空间性的相对用语如“下方”、“其下”、“下侧”、“上方”、“上侧”、或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件，而非局限于图示方向。元件亦可转动90°或其他角度，因此方向性用语仅用以说明图示中的方向。此外，当数值或数值范围的描述有“约”、“近似”、或类似用语时，除非特别说明否则其包含所述数值的+/-10％。举例来说，用语“约5nm”包含的尺寸范围为4.5nm至5.5nm。
本发明实施例一般关于半导体装置，更特别关于具有鳍状物(或堆叠鳍状物)的通道的输入/输出装置(或晶体管)与具有纳米线通道的核心装置(或晶体管)于相同基板上的集成电路。在一实施例中，将具有堆叠的纳米线通道的至少两个全绕式栅极装置(比如分别用于高速应用与低功率(及/或低漏电流)应用)置于集成电路的核心区中，并将鳍状场效晶体管(用于输入/输出应用，包括静电放电应用)置于集成电路的输入/输出区中。
输入/输出区所用的操作电压可与外部电压(比如外部/周边电路的电压等级)类似，并高于核心区的操作电压。为了容许较高的操作电压，输入/输出区中的晶体管的栅极介电层比核心区中的晶体管的栅极介电层厚。对输入/输出区中的全绕式栅极晶体管而言，较厚的栅极介电层可减少通道膜之间的空间，因此实质上减少或甚至消除形成金属栅极的多种层状物于通道膜周围的工艺容许范围，造成效能下降。鳍状场效晶体管装置的栅极介电层比全绕式栅极装置的栅极介电层厚，而不需考量通道膜之间的空间。
在核心区中，全绕式栅极装置的栅极介电层厚度，与电路速度及漏电能效能相关。栅极介电层较薄的全绕式栅极装置较适于高速应用。栅极介电层较厚的全绕式栅极装置较适于低功率(及/或低漏电流)的应用。在实施例中，高速应用的全绕式栅极装置的栅极介电层，比低功率(及/或低漏电流)应用的全绕式栅极装置的栅极介电层薄。本发明实施例提供弹性的设计整合方案，使相同集成电路中容纳不同电路。本发明实施例的制作方法可轻易整合至现有的半导体制造流程中。本发明多种实施例的细节将搭配图1A至22说明。
图1A及图1B是本发明一实施例中，半导体结构如集成电路10的方框图。集成电路10包括核心区12与输入/输出区14。核心区12包括逻辑电路、存储器电路、与其他核心电路。输入/输出区14包括输入/输出单元、静电放电单元、与其他电路。核心区12包括装置区16，其具有全绕式栅极装置18与全绕式栅极装置20。在一些实施例中，全绕式栅极装置18与全绕式栅极装置20彼此相邻或相接，如图1B所示。在一些实施例中，全绕式栅极装置18与全绕式栅极装置20分开，比如隔有其他全绕式栅极装置或在核心区12的不同装置区中。输入/输出区14包括装置区22，其具有鳍状场效晶体管装置24。
全绕式栅极装置18及20的每一者包括垂直堆叠的多个通道膜26于基板27上。每一全绕式栅极装置中的通道膜26的数目可为2至10。每一通道膜26包含硅或另一合适的半导体材料。栅极介电层28a包覆全绕式栅极装置18的通道膜26，且可包含界面层30a与高介电常数的介电层32a。栅极介电层28b包覆全绕式栅极装置20的通道膜26，且可包含界面层30b与高介电常数的介电层32b。鳍状场效晶体管装置24包含鳍状物34作为通道膜。鳍状物34自基板27延伸穿过隔离结构36(比如浅沟槽隔离结构)。栅极介电层28c覆盖鳍状物34，且可包含界面层30c与高介电常数的介电层32c。栅极(未图示)可包覆每一栅极介电层28a、28b、与28c，或位于每一栅极介电层28a、28b、与28c上。栅极可包含一或多个功函数金属层，与基体金属层。在所述实施例中，全绕式栅极装置18及20可共用相同栅极。
全绕式栅极装置18及20与鳍状场效晶体管装置24具有不同的栅极介电层厚度。举例来说，输入/输出区14中的鳍状场效晶体管装置24包含第一厚度(如电容等效厚度)的栅极介电层28c，其为最厚的栅极介电层以符合高电压应用。核心区12中的全绕式栅极装置20包含第二厚度的栅极介电层，其为中等厚度(中等的电容等效厚度)以符合低功率及/或低漏电流的应用。核心区12中的全绕式栅极装置18包含第三厚度的栅极介电层28a，其为最薄(最薄的电容等效厚度)的栅极介电层以符合高速应用。综上所述，集成电路10可称作三栅极晶体管装置。在此实施例中，栅极介电层28a、28b、及28c中的高介电常数的介电层32a、32b、及32c可具有实质上相同的物理厚度(比如约
Figure BDA0002811469260000071
至约
Figure BDA0002811469260000072
)，而界面层30a、30b、及30c具有不同的物理厚度。举例来说，界面层30b可比界面层30a厚约10％至约40％，而界面层30c可比界面层30a厚至少约50％。在具体例子中，界面层30a的厚度小于或等于约
Figure BDA0002811469260000073
界面层30b的厚度介于约
Figure BDA0002811469260000078
至约
Figure BDA0002811469260000077
之间，而界面层30c的厚度大于或等于约
Figure BDA0002811469260000074
(比如介于约
Figure BDA0002811469260000075
至约
Figure BDA0002811469260000076
之间)。
图2A至图2F是本发明多种实施例中，形成三栅极晶体管装置的方法100的流程图。图2A至图2F将搭配图3至图22说明如下，其为依据方法100的多种制作阶段中的工件的部分透视图与剖视图。方法100仅用于举例而非局限本发明实施例至权利要求未实际记载处。在方法100之前、之中、与之后可提供额外步骤，且方法100的额外实施例可调换、取代、或省略一些下述步骤。图3至图22所示的半导体装置可添加额外结构，且半导体装置的其他实施例可置换、调整、或省略一些下述结构。
在方法100的步骤102中(图2A)，提供半导体结构如集成电路200，其包括第一区与第二区，如图3所示。第一区与第二区的每一者包括装置区，其包括不同功能的晶体管。在一些实施例中，第一区为核心区202，而第二区为输入/输出区204。在这些实施例中，核心区指的是含有逻辑单元(比如逆变器、NAND、NOR、AND、OR、或触发器)以及存储器单元(比如静态随机存取存储器、动态随机存取存储器、或快闪存储器)的装置区。输入/输出区指的是交界于核心区与外部/周边电路之间的装置区，比如印刷电路板上的电路，其上安装有半导体装置如集成电路200。在所述实施例中，核心区202包括高速应用所用的全绕式栅极核心装置结构206a与低功率及/或低漏电流应用所用的全绕式栅极核心装置结构206b，而输入/输出区204包括鳍状场效晶体管输入/输出装置结构206c。
全绕式栅极核心装置结构206a、全绕式栅极核心装置结构206b、与鳍状场效晶体管输入/输出装置结构206c的每一者包括基板208、隔离结构210、堆叠的鳍状物212a、212b、或212c，以及接合堆叠的鳍状物212a、212b、或212c的虚置栅极结构216。
在一些实施例中，基板208包含硅。在其他或额外实施例中，基板208包含另一半导体元素(如锗)、半导体化合物(如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、及/或锑化铟)、半导体合金(如硅锗、磷砷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟、及/或磷砷化镓铟)、或上述的组合。在一些实施方式中，基板208包含一或多种III-V族材料、一或多种II-VI族材料、或上述的组合。在一些实施方式中，基板208为绝缘层上半导体基板，比如绝缘层上硅基板、绝缘层上硅锗基板、或绝缘层上锗基板。绝缘层上半导体基板的制作方法可采用分隔布植氧、晶圆接合、及/或其他合适方法。基板208可包含多种掺杂区，其设置依据半导体装置如集成电路200的设计需求。p型掺杂区可包含p型掺质，比如硼、铟、其他p型掺质、或上述的组合。n型掺杂区可包含n型掺质，比如磷、砷、其他n型掺质、或上述的组合。在一些实施例中，基板208包含的掺杂区具有p型掺质与n型掺质的组合。举例来说，多种掺杂区可直接形成于基板208之中及/或之上，以提供p型井结构、n型井结构、双井结构、隆起结构、或上述的组合。可进行离子布植工艺、扩散工艺、及/或其他合适掺杂工艺，以形成多种掺杂区。在一些实施例中，p型全绕式栅极装置与p型鳍状场效晶体管装置形成于n型井上，而n型全绕式栅极装置与n型鳍状场效晶体管装置形成于p型井上。全绕式栅极核心装置结构206a、全绕式栅极核心装置结构206b、与鳍状场效晶体管输入/输出装置结构206c的每一者可各自为n型装置或p型装置。
隔离结构210可包含氧化硅、氮化硅、氮氧化硅、掺杂氟的硅酸盐玻璃、低介电常数的介电材料、及/或其他合适的绝缘材料。隔离结构210可为浅沟槽隔离结构。其他隔离结构如场氧化物、局部氧化硅、及/或其他合适结构亦属可能。隔离结构210可包含多层结构，比如具有一或多个热氧化物衬垫层。
堆叠的鳍状物212a及212b各自具有交错堆叠的半导体层220及222。半导体层220中的第一半导体材料与半导体层222中的第二半导体材料的材料及/或组成不同。第一半导体材料与第二半导体材料的每一者可包含硅、锗、半导体化合物(如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、或锑化铟)、或半导体合金(如硅锗、磷砷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟、或磷砷化镓铟)。在此实施例中，半导体层220包括硅，且半导体层222包括锗或硅锗合金。堆叠的鳍状物212a及212b中的半导体层220及222可额外包含掺质(如磷、砷、硼、及/或铟)以改善将形成的全绕式栅极晶体管的效能。
堆叠的鳍状物212a及212b的形成方法可为外延成长半导体层220及222于基板208上，接着由任何合适方法图案化半导体层220及222形成个别的堆叠的鳍状物212a及212b。鳍状物212c的形成方法亦可由类似的图案化工艺图案化基板208。举例来说，堆叠的鳍状物212a及212b与鳍状物212c的每一者的图案化方法可采用一或多道光微影工艺，包含双重图案化或多重图案化工艺。一般而言，双重图案化或多重图案化工艺结合光微影与自对准工艺，其产生的图案间距小于采用单一的直接光微影工艺所得的图案间距。举例来说，一实施例形成牺牲层于基板上，并采用光微影工艺图案化牺牲层。采用自对准工艺，可沿着图案化的牺牲层的侧部形成间隔物。接着移除牺牲层，而保留的间隔物(或芯)之后可用于蚀刻初始的半导体层220及222与基板208，以图案化堆叠的鳍状物212a及212b与鳍状物212c。蚀刻工艺可包含干蚀刻、湿蚀刻、反应性离子蚀刻、及/或其他合适工艺。
虚置栅极结构216可保留金属栅极堆叠所用的区域，且可包含界面层230、虚置栅极232、第一栅极硬遮罩层234、与第二栅极硬遮罩层236。界面层230形成于每一堆叠的鳍状物212a及212b与鳍状物212c的上表面与侧壁表面上，以及隔离结构210的上表面上。界面层230可包含介电材料，比如氧化物层(如氧化硅)或氮氧化物层(如氮氧化硅)，且其沉积方法可为化学氧化、热氧化、原子层沉积、化学气相沉积、及/或其他合适方法。在沉积之后，可对界面层230进行后氧化物退火工艺，以改善栅极氧化物品质。在所述实施例中，界面层230的厚度适用于输入/输出应用，比如厚度大于或等于约
Figure BDA0002811469260000091
如后续附图所示，后续工艺中保留于鳍状物212c上的界面层230，可作为鳍状场效晶体管输入/输出装置结构206c所用的输入/输出氧化物层。可自堆叠的鳍状物212a与212b移除界面层230的其他部分。
虚置栅极232可包含多晶硅，且其形成方法可为合适的沉积工艺如低压化学气相沉积或等离子体辅助化学气相沉积。第一栅极硬遮罩层234与第二栅极硬遮罩层236可各自包含介电材料层，比如氧化硅及/或氮化硅，且其形成方法可为化学气相沉积或其他合适方法。举例来说，第一栅极硬遮罩层234可包含氧化硅层以与虚置栅极232相邻，而第二栅极硬遮罩层236可包含氮化硅层。界面层230、虚置栅极232、第一栅极硬遮罩层234、与第二栅极硬遮罩层236的图案化方法，可为光微影与蚀刻工艺。
为了使说明与附图清楚，图4A、图5A、及图6A包含全绕式栅极核心装置结构206a沿着图3所示的剖面A-A的部分剖面图，其沿着堆叠的鳍状物212a的长度方向穿过个别的通道区(在Y-Z平面中)。图4B、图5B、及图6B是鳍状场效晶体管输入/输出装置结构206c沿着图3所示的剖面B-B的部分剖视图，其沿着鳍状物212c的长度方向穿过个别的通道区(在Y-Z平面中)。图7至图22是半导体装置如集成电路200沿着图3所示的剖面C-C的剖视图，其沿着垂直于堆叠的鳍状物212a及212b与鳍状物212c的长度方向的方向穿过多个通道区(在X-Z平面中)。
在方法100的步骤104中(图2A)，形成栅极间隔物238于虚置栅极结构216的侧壁上，如图4A及图4B所示。栅极间隔物238可包含介电材料如氧化硅、氮化硅、氮氧化硅、碳化硅、其他介电材料、或上述的组合，且可包含一或多层的材料。栅极间隔物238的形成方法可为沉积间隔物材料如毯覆层于半导体装置如集成电路200上。接着以非等向蚀刻工艺蚀刻间隔物材料。虚置栅极结构216的侧壁上的间隔物材料的部分，可转变为栅极间隔物238。步骤104可进一步形成源极/漏极结构240于源极/漏极区中，如图5A及图5B所示。举例来说，步骤104可蚀刻凹陷至堆叠的鳍状物212a及212b与鳍状物212c中，并外延成长半导体材料于凹陷中。半导体材料可隆起高于个别鳍状物的上表面。步骤104可分开形成n型装置与p型装置所用的源极/漏极结构240。举例来说，步骤104可形成n型掺杂硅的源极/漏极结构240以用于n型装置，以及p型掺杂硅锗的源极/漏极结构240以用于p型装置。步骤104可进一步形成接点蚀刻停止层242于源极/漏极结构240上，并形成层间介电层244于接点蚀刻停止层242上。接点蚀刻停止层242可包含氮化硅、氮氧化硅、具有氧或碳元素的氮化硅、及/或其他材料，其形成方法可为化学气相沉积、物理气相沉积、原子层沉积、或其他合适方法。层间介电层244可包含四乙氧基硅烷的氧化物、未掺杂的硅酸盐玻璃、掺杂的氧化硅(如硼磷硅酸盐玻璃、掺杂氟的硅酸盐玻璃、磷硅酸盐玻璃、或硼硅酸盐玻璃)、及/或其他合适的介电材料。层间介电层244的形成方法可为等离子体辅助化学气相沉积、可流动的化学气相沉积、或其他合适方法。在步骤104之后可进行化学机械研磨工艺，以移除多余的介电材料。在一些实施例中，化学机械研磨工艺亦移除第一栅极硬遮罩层234与第二栅极硬遮罩层236，并露出虚置栅极232。
在方法100的步骤106中(图2A)，移除虚置栅极232以得栅极沟槽246，如图6A及图6B所示。步骤106可包含一或多道蚀刻工艺，其对虚置栅极232的材料具有选择性。通过选择蚀刻剂以避免蚀刻栅极间隔物238与层间介电层244，栅极沟槽246中所露出且与虚置栅极232相邻的栅极间隔物238与层间介电层244的部分实质上无蚀刻损失。这可增加光微影工艺的容许范围。蚀刻工艺可包任何合适的蚀刻技术，比如湿蚀刻、干蚀刻、反应性离子蚀刻、灰化、及/或其他蚀刻方法。在一例中，蚀刻工艺为采用氟为主的蚀刻剂(如四氟化碳、氟仿、二氟甲烷、或类似物)的干蚀刻工艺。在步骤106之后，栅极沟槽246中覆盖堆叠的鳍状物212a及212b与鳍状物212c的界面层230可露出，如图7所示。
在方法100的步骤108中(图2A)，形成遮罩层248于输入/输出区上，并自堆叠的鳍状物212a及212b移除界面层230，如图8所示。举例来说，界面层230的移除方法可为湿蚀刻、干蚀刻、反应性离子蚀刻、或其他合适蚀刻方法。举例来说，步骤108可采用氢氟酸为主的湿蚀刻剂以用于湿蚀刻，或氨与氢气的混合物以用于干蚀刻。在此步骤时，遮罩层248可覆盖鳍状物212c上的界面层230。在一些实施例中，遮罩层248为光刻胶层如底抗反射涂层。在步骤108之后，可移除遮罩层248，且移除方法可为蚀刻、灰化、或光刻胶剥除。
在方法100的步骤110中(图2A)，露出全绕式栅极核心装置结构206a及206b中的通道膜，如图9所示。在所述实施例中，通道膜为纳米线。此处所述的用语“纳米线”(或通道膜)指的是任何纳米等级(或微米尺寸)的材料部分，其具有伸长的形状，不论此部分的剖面形状为何。因此用语“纳米线”可为具有圆形剖面或实质上圆形剖面的伸长材料部分，以及包括圆柱状或实质上矩形的剖面的束状或棒状的材料部分。在步骤110之后，半导体层220将形成纳米线。在此实施例中，半导体层220包括硅，而半导体层222包含硅锗。可选择性移除多个半导体层222。在一些实施方式中，选择性移除工艺可采用合适的氧化剂如臭氧以氧化多个半导体层222。之后可选择性移除氧化的半导体层222。在此实施例中，步骤110包含干蚀刻工艺以选择性移除半导体层222，其可施加500℃至700℃的氯化氢气体，或施加四氟化碳、六氟化硫、与氟仿的气体混合物。界面层230在步骤110时，可保护鳍状场效晶体管输入/输出装置结构206c中的鳍状物212c免于实质上的蚀刻损失。
如图9所示，此时形成垂直堆叠的纳米线如半导体层220于全绕式栅极核心装置结构206a的通道区与全绕式栅极核心装置结构206b的通道区中。虽然图9显示每一全绕式栅极核心装置结构所用的四个纳米线如半导体层220，但多种实施例可具有更多或更少垂直堆叠的纳米线如半导体层220。举例来说，每一全绕式栅极核心装置结构中的纳米线如半导体层220的数目可为2至10。
在方法100的步骤112中(图2A)，分别形成栅极介电层250a、250b、及250c(一起视作栅极介电层250)于全绕式栅极核心装置结构206a、全绕式栅极核心装置结构206b、与鳍状场效晶体管输入/输出装置结构206c中。栅极介电层250a包括界面层252a以包覆全绕式栅极核心装置结构206a的纳米线如半导体层220，以及高介电常数的介电层254a以包覆界面层252a。栅极介电层250b包括界面层252b以包覆全绕式栅极核心装置结构206b的纳米线如半导体层220，以及高介电常数的介电层254b以包覆界面层252b。栅极介电层250c包括存在的界面层230(其覆盖鳍状物212c的上表面与侧壁表面)与高介电常数的介电层254c(其覆盖界面层230)。在所述实施例中，界面层252a及252b与高介电常数的介电层254a、254b、及254c(一起视作高介电常数的介电层254)沉积为实质上顺应性的层状物。
界面层252a及252b可包含介电材料，比如氧化物层(如氧化硅)或氮氧化物(如氮氧化硅)，其沉积方法可为化学氧化、热氧化、原子层沉积、化学气相沉积、及/或其他合适方法。在一些实施例中，界面层252a的厚度TIL1与界面层252b的厚度TIL2实质上相同，均小于界面层230的厚度TIL3。步骤112可消耗鳍状物212c的外侧表面上的多余硅，以进一步增加界面层230的厚度。在一些实施例中，厚度TIL3可增加约20％至约60％。在具体例子中，厚度TIL1及TIL2为约
Figure BDA0002811469260000131
至约
Figure BDA0002811469260000132
而厚度TIL3自大于约
Figure BDA0002811469260000133
增加至大于或等于约
Figure BDA0002811469260000134
(比如约
Figure BDA0002811469260000135
至约
Figure BDA0002811469260000136
)。
高介电常数的介电层254的沉积方法可采用任何合适技术，比如原子层沉积、化学气相沉积、有机金属化学气相沉积、物理气相沉积、热氧化、上述的组合、及/或其他合适技术。高介电常数的介电层254可包含金属氧化物(如氧化镧、氧化铝、氧化锆、氧化钛、氧化钽、氧化钇、钛酸锶、钛酸钡、氧化钡锆、氧化铪锆、氧化铪镧、氧化铪钽、氧化铪钛、钛酸钡锶、或类似物)、金属硅酸盐(如硅酸铪、硅酸镧、硅酸铝、或类似物)、金属或半导体的氮化物、金属或半导体的氮氧化物、上述的组合、及/或其他合适材料。在具体例子中，高介电常数的介电层254的厚度为约
Figure BDA0002811469260000137
至约
Figure BDA0002811469260000138
在方法100的步骤114中(图2B)，形成厚度调整层260以包复核心区中的栅极介电层250a及250b并覆盖输入/输出区中的栅极介电层250c，如图11所示。厚度调整层260可包含一或多个材料层。在所述实施例中，厚度调整层260包括除氧层262与盖层264。
除氧层262沉积于高介电常数的介电层254上。除氧层262对氧的亲和力，大于高介电常数的栅极介电层中的金属氧化物的金属与界面层中的硅对氧的亲和力。除氧层262可包含金属或金属化合物，比如钛、铪、锆、钽、铝、或上述的组合如钛铝。除氧层262的组成可为金属氮化物(如氮化钛、氮化钽、氮化钽硅、或氮化钛硅)，或金属合金的氮化物(如氮化钛铝)。在一些实施例中，除氧层262可为硅层。在具体例子中，除氧层262包含氮化钛硅，其富含金属(比如Ti:N的比例为约1.05:1至约2:1)。沉积方法可包含物理气相沉积、化学气相沉积、或原子层沉积。如后续附图所示，除氧层262在升温时可自界面层252a除氧。
在本发明一些实施例中，盖层264形成于除氧层262的顶部上，以避免在环境大气中氧化除氧层262，其中氧化可能发生在后续的除氧退火之前、之中、或之后。盖层264可包含金属或金属化合物，比如钛、钴、铝、锆、镧、镁、其他反应性金属、或上述的组合。除氧层262与盖层264的组成可为不同材料，但两者的一些材料选择可相同。在其他实施例中，未形成盖层。
在方法100的步骤116中(图2B)，形成遮罩层266以覆盖全绕式栅极核心装置结构206a，并自全绕式栅极核心装置结构206b与鳍状场效晶体管输入/输出装置结构206c移除厚度调整层260，如图12所示。举例来说，厚度调整层260的移除方法可为湿蚀刻、干蚀刻、反应性离子蚀刻、或其他合适的蚀刻方法。在此步骤中，遮罩层266覆盖栅极介电层250a上的厚度调整层260。在一些实施例中，遮罩层266为光刻胶层，比如底抗反射涂层。在步骤108之后可移除遮罩层248，且移除方法可为蚀刻、灰化、或光刻胶剥除。在另一实施例中，方法100(图2C)可跳过步骤114及116，但在步骤112之后进行步骤118。步骤118形成遮罩层(未图示)以覆盖全绕式栅极核心装置结构206b与鳍状场效晶体管输入/输出装置结构206c，并露出全绕式栅极核心装置结构206a。步骤120沉积厚度调整层260以包覆全绕式栅极核心装置结构206a的栅极介电层250a，其与上述的步骤114实质上类似。在步骤120之后，可移除遮罩层(未图示)，且移除方法可为蚀刻、灰化、或光刻胶剥除。在其他实施例中(图2B或图2C)，此时的厚度调整层260只保留于全绕式栅极核心装置结构206a的栅极介电层250a上，如图13所示。
在方法100的步骤122中(图2D)，进行退火工艺270(见图14)以除氧。除氧退火可采用峰值退火，其历时微秒(比如约10微秒至约500微秒之间)。个别晶圆的温度可介于约400℃至约1100℃之间。在一些例示性实施例中，温度介于约700℃至约1000℃之间。
除氧工艺至少可自界面层252a的底部夺氧，因此可保留界面层252a中的硅以形成额外硅层于纳米线如半导体层220的结晶硅层的顶部上。图14为部分271的放大图。除氧造成氧原子的移动方向274。综上所述，形成非晶硅层276。自界面层252a的底部除氧后，界面层252a所保留的硅可形成额外硅层。在除氧工艺之后，可保留界面层252a的中间部分。在除氧工艺之后，亦可不保留界面层252a。
在除氧退火工艺时，高介电常数的介电层254a可与界面层252a的顶部混合，并自界面层252a的底部除氧以形成混合化合物，其可为金属硅酸盐。混合化合物易于增加氧含量。举例来说，当高介电常数的介电层254a包括氧化铪，混合化合物包含硅酸铪。当高介电常数的介电层254a包括氧化锆，混合化合物包括硅酸锆。
除氧退火工艺之后，方法100的步骤124(图2D)的选择性蚀刻工艺中至少移除盖层264。亦可移除除氧层262，或保留而不移除除氧层262。蚀刻工艺可包含干蚀刻、湿蚀刻、反应性离子蚀刻、及/或其他合适工艺。在纳米线间距极小的实施例中(比如小于约10nm)，倾向移除除氧层262以改善后续栅极层的填充步骤，如图15所示。一些其他实施例不移除除氧层262，如图16所示。
除氧工艺可化学还原界面层252a，造成界面层252a的厚度减少或甚至消失(完全转换)。界面层252a的厚度TIL1可减少超过20％。在一些实施例中，除氧工艺后的厚度TIL1小于或等于约
Figure BDA0002811469260000151
而厚度TIL2维持实质上相同(比如约
Figure BDA0002811469260000152
至约
Figure BDA0002811469260000153
)，而厚度TIL3亦维持实质上相同(比如约
Figure BDA0002811469260000154
至约
Figure BDA0002811469260000155
)。高介电常数的介电层254的厚度可维持实质上相同，比如核心区与输入/输出区上的毯覆层。尽管如此，通过减少界面层252a的厚度并维持(及/或以步骤112增加)界面层230的初始厚度，栅极介电层250a的第一电容等效厚度最薄以符合高速应用，栅极介电层250b的第二电容等效厚度中等以符合低功率及/或低漏电流应用，而栅极介电层250c的第三电容等效厚度最厚以符合高电压应用。
在其他实施例中，厚度调整层260为不具有盖层264的单一层，且包覆全绕式栅极核心装置结构206b而非全绕式栅极核心装置结构206a的纳米线如半导体层220，比如通过保护遮罩层之下的鳍状场效晶体管输入/输出装置结构206c与全绕式栅极核心装置结构206a。在此实施例中，单一层为氧化物再成长辅助层，其可自环境大气中吸收氧，并将氧传输至下方的界面层252b。氧化物再成长辅助层可包含金属或金属化合物，其对氧的亲和力小于界面层252b中的硅对氧的亲和力。在一实施例中，氧化物再成长辅助层包含钨。接着进行退火工艺以活化辅助的氧化物再成长工艺，以增加界面层252b的厚度。在此实施例中，辅助的氧化物再成长工艺后的全绕式栅极核心装置结构206b的栅极介电层250b的厚度，大于全绕式栅极核心装置结构206a的栅极介电层250a的厚度，但小于鳍状场效晶体管输入/输出装置结构206c的栅极介电层的厚度。
在方法100的步骤126中(图2D)，形成栅极层272于栅极沟槽中，以包复核心区中的栅极介电层250a及250b，并位于输入/输出区中的栅极介电层250c的上表面与侧壁表面上。图17所示的一些实施例中，栅极层272直接接触栅极介电层250a。图18所示的一些其他实施例中，除氧层262保留于栅极层272与栅极介电层250a之间。在所述实施例中，全绕式栅极核心装置结构206a及206b相邻且共用相同的栅极层，而鳍状场效晶体管输入/输出装置结构206c具有分开的栅极层。栅极层272为导电层，其可包含一或多个金属层如功函数金属层、导电阻障层、与金属填充层。可分别形成n型晶体管与p型晶体管所用的栅极层272，其可采用不同金属层。功函数金属层可为p型或n型的功函数层。p型功函数层可包含有效功函数足够大的金属，其选自但不限于氮化钛、氮化钽、钌、钼、钨、铂、或上述的组合。n型功函数层包括有效功函数足够低的金属，其选自但不限于钛、铝、碳化钽、碳氮化钽、氮化钽硅、氮化钛硅、或上述的组合。栅极层272可包含多个功函数金属层，比如第一金属层与第二金属层。举例来说，第一金属层可包含氮化钛，而第二金属层可包含钛铝或钛、钽、碳、与铝的其他组合(比如碳化钛铝或碳化钽铝)。栅极层272亦可包含金属填充层。金属填充层可包含铝、钨、钴、及/或其他合适材料。在多种实施例中，栅极层272的金属填充层的形成方法可为电镀、原子层沉积、物理气相沉积、化学气相沉积、电子束蒸镀、或其他合适工艺。在多种实施例中，可进行化学机械研磨工艺，以自栅极堆叠的金属层移除多余金属，进而提供实质上平坦的上表面。
在方法100的步骤128中(图2D)，可对半导体装置如集成电路200进行后续工艺，以形成本技术领域已知的多种结构与区域。举例来说，后续工艺可形成接点开口、接点金属、以及多种接点/通孔/线路与多层内连线结构(比如金属层与层间介电层)，其设置以连接多种结构以形成含有一或多个多栅极装置的功能电路。在其他例子中，多层内连线可包含垂直内连线如通孔或接点，以及水平内连线如金属线路。多种内连线结构可采用多种导电材料，包括铜、钨、及/或硅化物。在一例中，采用镶嵌工艺及/或双镶嵌工艺以形成铜相关的多层内连线结构。此外，可在方法100之前、之中、与之后实施额外工艺步骤，且方法100的多种实施例可置换或省略一些上述工艺步骤。
图19显示半导体装置如集成电路200的另一实施例，其中鳍状物212c为堆叠的鳍状物，其包括交错堆叠的半导体层220及222。半导体层220及222的材料组成实质上类似于图3所示的上述层状物。可自外延成长的堆叠半导体层一起图案化堆叠的鳍状物212c、212a、及212b，而界面层230在步骤110时可保护堆叠的鳍状物212c免于露出纳米线的工艺。图20显示半导体装置如集成电路200的另一实施例，其中鳍状物212c亦为含有交错堆叠的半导体层220及222的堆叠鳍状物。与图19中的实施例的差别之一，是图20中的半导体层220及222沿着x轴的宽度可不同。在蚀刻工艺中可向下修整半导体层222的宽度，以露出更多半导体层220的表面积，进而露出更多硅层的<110>或<100>表面以增加载子移动率。
在方法100的另一实施例中，在步骤110(图2A)形成堆叠的纳米线如半导体层220于全绕式栅极核心装置结构206a及206b的栅极沟槽中之后，方法100可跳到步骤130(图2E)以对纳米线如半导体层220进行布植工艺，如图21所示。在步骤130中，先对全绕式栅极核心装置结构206b的纳米线如半导体层220进行布植工艺。具体而言，可由光微影与图案化工艺形成任何合适厚度的遮罩层282，以覆盖或保护基板的区域。如图21所示，形成遮罩层282于全绕式栅极核心装置结构206a与鳍状场效晶体管输入/输出装置结构206c的装置区上，以避免布植这些区域。遮罩层282可为光刻胶层及/或硬遮罩层。当全绕式栅极核心装置结构206a暴露至布植工艺284(见图21)，可布植掺质至栅极沟槽246中的全绕式栅极核心装置结构206a的纳米线如半导体层220中。布植工艺284可采用任何合适的掺杂物种，比如铟、氩、硅、及/或氟等掺杂物种。在所述实施例中，掺杂物种含氟。布植工艺284包含任何合适的布植剂量及/或能量。之后自全绕式栅极核心装置结构206a移除遮罩层282，并保留鳍状场效晶体管输入/输出装置结构206c上的遮罩层282，如图22所示。当全绕式栅极核心装置结构206a及206b均暴露至布植工艺284时，可布植掺质至栅极沟槽246中的全绕式栅极核心装置结构206a及206b的纳米线如半导体层220中。暴露至布植工艺284的时间越长，全绕式栅极核心装置结构206b的纳米线如半导体层220所接收的掺杂物种剂量，高于全绕式栅极核心装置结构206a的纳米线如半导体层220所接收的掺杂物种剂量。在所述实施例中，全绕式栅极核心装置结构206b的纳米线如半导体层220的氟浓度可大于全绕式栅极核心装置结构206a的纳米线如半导体层220的氟浓度，而鳍状物212c(或堆叠的鳍状物)实质上无掺杂物种。之后可移除遮罩层282。
布植工艺284可用于增加氧化速率，其可改变步骤132沉积栅极介电层的层状物成长。通过增加氧化速率，布植工艺可影响核心装置所用的界面层厚度，因此影响栅极介电层厚度。在此实施例中，布植工艺284增加氧化速率，因此在成长界面层于全绕式栅极核心装置结构206a及206b的纳米线如半导体层220上时，全绕式栅极核心装置结构206b的界面层厚度会大于全绕式栅极核心装置结构206a的界面层厚度。界面层厚度不同的原因可为布植掺质于通道膜中所增加的氧化速率。方法100的此实施例中，在方法100的步骤130及132之后(图2E)，可直接跳到步骤126以形成栅极层。在方法100的另一实施例中，方法100的步骤130及132(图2F)之后可进行步骤114(图2B)或步骤118(图2C)，以形成厚度调整层进而调整栅极介电层的厚度。
本发明的一或多个实施例可提供许多优点至半导体装置与其形成方法，但不局限于此。举例来说，本发明实施例提供全绕式栅极的高速装置、全绕式栅极的低功率及/或低漏电流装置、与鳍状场效晶体管高电压装置于相同的基板上与相同的集成电路中。全绕式栅极高速装置与全绕式栅极低功率/低漏电流装置(比如用于高速或低功率电路)置于集成电路的核心区中，而鳍状场效晶体管高电压装置(用于输入/输出电路或静电放电电路)置于集成电路的输入/输出区中。全绕式栅极高速装置、全绕式栅极低功率/低漏电流装置、与鳍状场效晶体管高电压装置可具有不同的栅极介电层厚度，使这三种装置具有不同效能。这些实施例可让电路设计者选择不同形态的装置，以最佳化集成电路的不同区域中的电路。
本发明一例示性的例子关于半导体装置。半导体装置包括：基板，具有第一区与第二区；第一晶体管，位于第一区中，第一晶体管具有第一通道、第一栅极介电层位于第一通道上、以及第一栅极层位于第一栅极介电层上；第二晶体管，位于第一区中，第二晶体管具有第二通道、第二栅极介电层位于第二通道上、以及第二栅极层位于第二栅极介电层上；以及第三晶体管，位于第二区中，第三晶体管具有第三通道、第三栅极介电层位于第三通道上、以及第三栅极层位于第三栅极介电层上，其中第一栅极介电层的第一厚度小于第二栅极介电层的第二厚度，其中第二栅极介电层的第二厚度小于第三栅极介电层的第三厚度。在一些实施例中，第一晶体管的第一通道包括多个第一通道膜，且第一栅极介电层包覆第一通道膜，其中第二晶体管的第二通道包括多个第二通道膜，且第二栅极介电层包覆第二通道膜，其中第三晶体管的第三通道包括鳍状物。在一些实施例中，第一区为核心装置区，而第二区为输入/输出装置区。在一些实施例中，第一栅极介电层包括第一界面层与第一高介电常数的介电层位于第一界面层上，其中第二栅极介电层包括第二界面层与第二高介电常数的介电层位于第二界面层上，其中第三栅极介电层包括第三界面层与第三高介电常数的介电层位于第三界面层上，其中第一界面层比第二界面层薄，且第二界面层比第三介电层薄。在一些实施例中，第二界面层比第一界面层厚约10％至约40％。在一些实施例中，第一晶体管包括除氧层于第一栅极介电层与第一栅极层之间，其中第二栅极介电层直接接触第二栅极层。在一些实施例中，除氧层包括的材料是钛、钽、硅、氮化钛、氮化钛硅、氮化钽、氮化钽硅、或上述的组合。在一些实施例中，第一晶体管包括非晶硅层于第一栅极介电层与第一通道之间，其中第二栅极介电层直接接触第二通道。在一些实施例中，第一栅极介电层包括高介电常数的介电材料，以及高介电常数的介电材料、硅、与氧的混合化合物。在一些实施例中，第一晶体管的第一通道包括第一浓度的氟，第二晶体管的第二通道包括第二浓度的氟，且第一浓度小于第二浓度。在一些实施例中，第三晶体管的第三通道实质上无氟。
本发明另一例示性的例子关于半导体装置。半导体装置包括第一全绕式栅极晶体管，包括：多个第一通道膜，第一界面层包覆第一通道膜，第一高介电常数的介电层包覆第一界面层，以及第一栅极层包覆第一高介电常数的介电层；第二全绕式栅极晶体管，包括：多个第二通道膜，第二界面层包覆第二通道膜，第二高介电常数的介电层包覆第二界面层，以及第二栅极层包覆第二高介电常数的介电层；以及鳍状场效晶体管，包括：鳍状物通道，第三界面层位于鳍状物通道上；第三高介电常数的介电层位于第三界面层上，以及第三栅极层位于第三高介电常数的介电层上，其中第一界面层比第二界面层薄，而第二界面层比第三界面层薄。在一些实施例中，第一全绕式栅极晶体管与第二全绕式栅极晶体管均位于核心装置区中，且鳍状场效晶体管位于输入/输出装置区中。在一些实施例中，第一界面层的厚度小于或等于约
Figure BDA0002811469260000201
Figure BDA0002811469260000202
第二界面层的厚度界于约
Figure BDA0002811469260000203
至约
Figure BDA0002811469260000204
之间，且第三界面层的厚度大于或等于约
Figure BDA0002811469260000205
在一些实施例中，第一高介电常数的介电层与第二高介电常数的介电层具有实质上相同的厚度。在一些实施例中，第一全绕式栅极晶体管包括除氧层于第一高介电常数的介电层与第一栅极层之间，且第二高介电常数的介电层直接接触第二栅极层。
本发明另一例示性的例子关于半导体装置的形成方法。方法包括提供结构，其具有多个第一通道膜、多个第二通道膜、与鳍状物，其中第一通道膜与第二通道膜位于集成电路的核心装置区中，而鳍状物位于集成电路的输入/输出装置区中；形成第一氧化物层以包覆第一通道膜与第二通道膜并位于鳍状物上；自第一通道膜与第二通道膜移除第一氧化物层；形成第二氧化物层以包覆第一通道膜与第二通道膜；形成高介电常数的介电层以包复核心装置区中的第二氧化物层并位于输入/输出装置区中的第一氧化物层上；形成厚度调整层以包覆之前包覆第一通道膜的高介电常数的介电层；进行退火工艺以调整包覆第一通道膜的第二氧化物层的厚度；移除厚度调整层的至少一部分；以及形成栅极层以包复核心装置区中的高介电常数的介电层并位于输入/输出装置区中的高介电常数的介电层上。在一些实施例中，厚度调整层为除氧层，且退火工艺减少第二氧化物层的部分的厚度。在一些实施例中，厚度调整层为氧化物再成长辅助层，且退火工艺增加第二氧化物层的部分的厚度。在一些实施例中，方法包括进行布植工艺于核心装置区上，其中第一通道膜接收的布植剂量小于第二通道膜接收的布植剂量。
上述实施例的特征有利于本技术领域中技术人员理解本发明。本技术领域中技术人员应理解可采用本发明作基础，设计并变化其他工艺与结构以完成上述实施例的相同目的及/或相同优点。本技术领域中技术人员亦应理解，这些等效置换并未脱离本发明精神与范围，并可在未脱离本发明的精神与范围的前提下进行改变、替换、或变动。

Claims (1)

1.一种半导体装置，包括：
一基板，具有一第一区与一第二区；
一第一晶体管，位于该第一区中，该第一晶体管具有一第一通道、一第一栅极介电层位于该第一通道上、以及一第一栅极层位于该第一栅极介电层上；
一第二晶体管，位于该第一区中，该第二晶体管具有一第二通道、一第二栅极介电层位于该第二通道上、以及一第二栅极层位于该第二栅极介电层上；以及
一第三晶体管，位于该第二区中，该第三晶体管具有一第三通道、一第三栅极介电层位于该第三通道上、以及一第三栅极层位于该第三栅极介电层上，
其中该第一栅极介电层的一第一厚度小于该第二栅极介电层的一第二厚度，
其中该第二栅极介电层的该第二厚度小于该第三栅极介电层的一第三厚度。
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