CN218351466U - 集成电路 - Google Patents

集成电路 Download PDF

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Publication number
CN218351466U
CN218351466U CN202222095836.7U CN202222095836U CN218351466U CN 218351466 U CN218351466 U CN 218351466U CN 202222095836 U CN202222095836 U CN 202222095836U CN 218351466 U CN218351466 U CN 218351466U
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layer
gate
region
thickness
integrated circuit
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李致葳
黄文宏
游国丰
陈建豪
陈学儒
陈昱璇
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种集成电路包含具有第一区和第二区的基底；位于第一区中的第一全绕式栅极装置，第一全绕式栅极装置包含沿第一方向纵向延伸的第一通道构件，以及包覆第一通道构件的通道区的第一栅极结构，第一栅极结构包含第一界面层；以及位于第二区中的第二全绕式栅极装置，第二全绕式栅极装置包含沿第一方向纵向延伸的第二通道构件，以及包覆第二通道构件的通道区的第二栅极结构，第二栅极结构包含第二界面层，第二界面层具有邻近第二通道构件的第一部分和在第一部分上方的第二部分，第一部分的密度小于第二部分的密度。

Description

集成电路
技术领域
本实用新型实施例关于半导体制造技术，特别关于半导体装置。
背景技术
半导体集成电路(integrated circuit，IC)产业已经历了指数型成长。集成电路材料和设计上的技术进展已产生了数个世代的集成电路，每一世代皆较前一世代具有更小且更复杂的电路。在集成电路演进的历程中，当几何尺寸(亦即使用生产制程可以产生的最小元件(或线))缩减时，功能密度(亦即单位芯片面积的互连装置数量)通常也增加。这种尺寸微缩制程通常借由提高生产效率及降低相关成本而提供一些效益。这样的尺寸微缩也增加了加工和制造集成电路的复杂度。
举例来说，随着集成电路技术向更小的技术节点发展，已经引入多栅极装置以借由增加栅极-通道耦合、减少截止状态电流和降低短通道效应(short-channel effects，SCEs)来改善栅极控制。多栅极(multiple gate或multi-gate)装置通常是指具有栅极结构或其部分的装置，其设置在通道区的多于一侧上方。纳米片晶体管，例如全绕式栅极(gate-all-around，GAA)晶体管，是多栅极装置的范例，其已成为高性能和低漏电应用的流行且有希望的候选装置。相较于平面晶体管，这样的配置提供更好的通道控制并大幅降低短通道效应(特别是借由降低次临界(sub-threshold)漏电)。纳米片晶体管具有可以部分或完全环绕通道区延伸的栅极结构，以在所有侧面上提供对通道区的进接。在一些实施方式中，纳米片晶体管的通道区包含垂直堆叠的多个纳米片(其水平延伸，借此提供水平定向的通道构件)。通道区也可以由其他合适的纳米结构形成，例如纳米线。
集成电路装置包含位于不同区(或区域)中的晶体管，其提供不同的功能，例如输入/输出(input/output，I/O)功能和核心功能。这些不同的功能要求晶体管具有不同的构造。同时，具有相似制程和相似制程宽裕度(process windows)来制造这些不同的晶体管以降低成本并提高产量是有利的。虽然现有的多栅极场效晶体管和制程通常足以满足其预期目的，但它们并非在各个面向都完全令人满意。举例来说，I/O功能和核心功能可能偏好不同的栅极氧化物层厚度，以分别支持高压和高速应用。因此，如何以适应不同应用的不同栅极氧化物层厚度持续缩减I/O装置和核心装置的栅极堆叠尺寸是半导体产业面临的挑战。本实用新型实施例是为了解决上述问题和其他相关问题。
实用新型内容
根据一些实施例提供集成电路。此集成电路包含具有第一区和第二区的基底；位于第一区中的第一全绕式栅极装置，第一全绕式栅极装置包含沿第一方向纵向延伸的第一通道构件，以及包覆第一通道构件的通道区的第一栅极结构，第一栅极结构包含第一界面层；以及位于第二区中的第二全绕式栅极装置，第二全绕式栅极装置包含沿第一方向纵向延伸的第二通道构件，以及包覆第二通道构件的通道区的第二栅极结构，第二栅极结构包含第二界面层，第二界面层具有邻近第二通道构件的第一部分和在第一部分上方的第二部分，第一部分的密度小于第二部分的密度。
优选地，该第二界面层的该第一部分具有在一第二方向上测量的一第一厚度，该第二方向垂直于该第一方向，该第二界面层的该第二部分具有在该第二方向上测量的一第二厚度，并且该第一界面层具有在该第二方向上测量的一第三厚度，并且其中该第二厚度等于该第三厚度。
优选地，该第一厚度为该第二厚度的30％至50％。
优选地，该第三厚度为
Figure BDA0003790738670000023
至
Figure BDA0003790738670000024
优选地，该第二界面层的该第一部分是氧化硅和硅的复合层。
优选地，该第二界面层的该第一部分的该密度为2.55g/cm3。
优选地，该第一区是核心区且该第二区是输入/输出(I/O)区。
优选地，该第一通道构件具有在一第二方向上测量的一第一厚度，该第二方向垂直于该第一方向，该第二通道构件具有在该第二方向上测量的一第二厚度，并且其中该第一厚度大于该第二厚度。
优选地，该第一厚度比该第二厚度大
Figure BDA0003790738670000021
至
Figure BDA0003790738670000022
优选地，该第一栅极结构更包含一第一高介电常数介电层包覆该第一界面层，该第二栅极结构更包含一第二高介电常数介电层包覆该第二界面层，并且其中该第一高介电常数介电层与该第二高介电常数介电层具有相同的厚度，该厚度系在垂直于该第一方向的一第二方向上测量。
附图说明
借由以下的详细描述配合所附图式，可以更加理解本实用新型实施例的面向。需强调的是，根据产业上的标准惯例，许多部件并未按照比例绘制。事实上，为了能清楚地讨论，各种部件的尺寸可能被任意地增加或减少。
图1A和图1B根据本实用新型实施例的面向绘示半导体装置的示意性方框图和核心和I/O区中的两个多栅极晶体管之相应的局部剖面图。
图2A和图2B根据本实用新型实施例的面向绘示形成图1A～图1B所示的多栅极晶体管的方法的流程图。
图3根据本实用新型实施例的面向绘示半导体装置的图解透视图。
图4、图5、图6、图7、图8、图9、图10、图11、图12、图13、图14、图15、图16、图17、图18、图19和图20根据本实用新型实施例的各种实施例绘示根据图2A和图2B的方法的制造制程期间的半导体结构的剖面图。
其中，附图标记说明如下：
10：集成电路
12：核心区
14：I/O区
20，24：全绕式栅极装置
26：通道构件
27，208：基底
28a，28b，252，252a，252b：栅极介电层
30a，30b：界面层
32a，32b，250，250a，250b：高介电常数介电层
100：方法
102，104，106，108，110，112，114，116，118，120，122，124：操作
126，128，130，132：操作
200：半导体结构
202：第一区
204：第二区
206a，206b：装置结构
210：隔离结构
212a，212b：鳍片
216：虚设栅极结构
220，222：半导体层
221：额外的氧化硅层
230：虚设界面层
232：虚设栅极电极
234：第一栅极硬遮罩层
236：第二栅极硬遮罩层
238：栅极间隔物
240：源极/漏极部件
242：接触蚀刻停止层
244：层间介电层
246：栅极沟槽
248，248a，248b，248b’：栅极氧化物层
260：厚度调制层
262：牺牲层
264：遮罩层
270：退火制程
272：区域
274：氧原子的移动
282：栅极电极层
A-A，B-B：剖面
d，D1，D2：距离
H1，H2：厚度
S：间距
W：宽度
具体实施方式
以下内容提供许多不同实施例或范例，用于实施本实用新型实施例的不同部件。组件和配置的具体范例描述如下，以简化本实用新型实施例。当然，这些仅仅是范例，而非用于限定本实用新型实施例。举例来说，叙述中提及第一部件形成于第二部件上或上方，可能包含形成第一部件和第二部件直接接触的实施例，也可能包含额外的部件形成于第一部件和第二部件之间，使得第一部件和第二部件不直接接触的实施例。此外，本实用新型实施例在不同范例中可重复使用参考标号及/或字母。此重复是为了简化和清楚的目的，而非代表所讨论的不同实施例及/或组态之间有特定的关系。
另外，本文可能使用空间相对用语，例如“在……之下”、“在……下方”、“下方的”、“在……上方”、“上方的”及类似的用词，这些空间相对用语是为了便于描述如图所示的一个(些)元件或部件与另一个(些)元件或部件之间的关系。这些空间相对用语涵盖使用中或操作中的装置的不同方位，以及图式中描绘的方位。当装置被转向不同方位时(旋转90度或其他方位)，则在此使用的空间相对形容词也将依转向后的方位来解释。更进一步，当用“约”、“近似”和类似的用语描述数字或数字范围时，此用语是为了涵盖所述数字的+/-10％内的数字，除非另有说明。举例来说，用语“约5nm”涵盖4.5nm至5.5nm的尺寸范围。
本实用新型实施例总体而言关于半导体装置，并且更具体地关于在同一基底上具有纳米片通道的具有输入/输出(I/O)装置(或晶体管)和核心装置(或晶体管)的集成电路(IC)。在一实施例中，在集成电路的核心区中放置至少一个具有堆叠纳米片通道的全绕式栅极(GAA)装置，例如用于实现高速应用，而在集成电路的I/O区放置至少一个全绕式栅极装置，用于实现I/O应用或静电放电(electrostatic discharge，ESD)应用。
用于I/O区的操作电压可以类似于外部电压(外部/外围电路的电压位准(voltagelevel))并高于核心区的操作电压。为了适应更高的操作电压，相较于核心区中的晶体管，I/O区中的晶体管可能具有较厚的栅极氧化物层。在核心区中，栅极氧化物层的厚度与晶体管的速度和漏电性能相关。由于栅极氧化物层较薄，全绕式栅极装置更适合高速应用。为了进一步实施实施例，I/O区中的全绕式栅极装置具有比核心区中的全绕式栅极装置厚的栅极氧化物层。本实用新型实施例提供灵活的设计整合方案以适应同一集成电路中的不同电路。根据本实用新型实施例的制造方法可以轻易地整合至现有的半导体制造流程中。参照图1A～图20描述本实用新型实施例中的各种实施例的细节。
共同参照图1A和图1B，其中显示根据本实用新型实施例的一实施例建构的半导体结构10(例如集成电路10)的示意性方框图。集成电路10包含核心区12和I/O区14。核心区12包含逻辑电路、存储器电路和其他核心电路。I/O区14包含I/O单元、静电放电单元和其他电路。核心区12包含至少形成全绕式栅极装置20的装置区。I/O区14包含至少形成全绕式栅极装置24的装置区。在一些实施例中，核心区12和I/O区14彼此相邻放置。在一些其他实施例中，核心区12和I/O区14是分开的，例如借由其间的其他核心区或I/O区。
全绕式栅极装置20和24各自包含在基底27之上垂直堆叠的多个通道构件26，如图1B所示，图1B是局部剖面图。每个全绕式栅极装置中的通道构件26的数量可以在2到10的范围。每个通道构件26包含硅或其他合适的半导体材料。栅极介电层28a包覆环绕全绕式栅极装置20的通道构件26，栅极介电层28a包含界面层(也称为栅极氧化物层)30a和高介电常数介电层32a。栅极介电层28b包覆环绕全绕式栅极装置24的通道构件26，栅极介电层28b包含界面层30b和高介电常数介电层32b。栅极电极(未绘示)包覆环绕每个栅极介电层28a和28b或在每个栅极介电层28a和28b上方。栅极电极可以包含一或多个功函数金属层和块体金属层。全绕式栅极装置20位于距全绕式栅极装置24至少间距“S”的位置。在绘示的实施例中，间距S为通道构件26的宽度“W”的约四(4)倍。将间距S设计为借由在将核心和I/O区中的装置区图案化时提供余裕来简化制造制程。
全绕式栅极装置20和24具有不同的栅极氧化物层厚度。举例来说，核心区12中的全绕式栅极装置20包含薄的栅极氧化物层30a，其适合高速应用；I/O区14中的全绕式栅极装置24包含厚的栅极氧化物层30b，其适合高压应用。作为范例，栅极氧化物层30b可以比栅极氧化物层30a厚约30％至约50％。在特定范例中，栅极氧化物层30a的厚度为约
Figure BDA0003790738670000071
至约
Figure BDA0003790738670000072
并且界面层30b的厚度与界面层30a的厚度的厚度比为约1.3：1至约1.5：1。如果栅极氧化物层30b比栅极氧化物层30a厚不到30％，则高压性能可能会降低；如果界面层30b比界面层30a厚超过50％，则I/O装置的栅极驱动能力可能由于相对大的栅极氧化物厚度而减弱。如下文进一步详细解释的，将通道构件26的结晶硅的顶部转化为I/O区14中的氧化硅的栅极氧化物再成长制程造成界面层30b的额外厚度。因此，核心区12中的通道构件26的厚度“H1”可以大于I/O区14中的通道构件26的厚度“H2”，在一些实施例中例如大约
Figure BDA0003790738670000073
至约
Figure BDA0003790738670000074
此外，在栅极介电层28a和28b内，高介电常数介电层32a和32b可以具有大致相同的厚度(例如约
Figure BDA0003790738670000075
至约
Figure BDA0003790738670000076
)，而栅极氧化物层30a比栅极氧化物层30b薄，使得栅极介电层28a比栅极介电层28b薄。为了进一步实施实施例，包覆全绕式栅极装置20的堆叠通道构件26的相邻栅极介电层28a之间的距离“D1”大于包覆全绕式栅极装置24的堆叠通道构件26的相邻栅极介电层28b之间的距离“D2”。
图2A和图2B根据本实用新型实施例的各个面向绘示形成多栅极晶体管的方法100的流程图。以下将结合图3～图20描述图2A和图2B，图3～图20是根据方法100的在制造的各个阶段的工件的局部透视图和剖面图。方法100仅是范例，而非用于将本实用新型实施例限制于超出权利要求书中明确记载的范围。可以在方法100之前、期间和之后提供额外的步骤，并且对于方法100的额外实施例，可以移动、替换或消除描述的一些步骤。可以在图3～图20中描绘的半导体装置中添加额外的部件，并且可以在半导体装置的其他实施例中替换、修改或消除下文描述的一些部件。
在操作102，方法100(图2A)提供包含第一区202和第二区204的半导体结构200(或半导体装置200)，如图3所示。第一区202和第二区204各自包含具有不同功能的晶体管的装置区。在一些实施例中，第一区202是核心区且第二区204是输入/输出(I/O)区。在那些实施例中，核心区(或核心区域)是指包含逻辑单元(例如反相器(inverter)、与非(NAND)、或非(NOR)、与(AND)、或(OR)和触发器(Flip-Flop))以及存储单元(例如静态随机存取存储器(static random access memory，SRAM)、动态随机存取存储器(dynamic random accessmemory，DRAM)和快闪存储器)的装置区。I/O区(或I/O区域)是指在核心装置区和外部/外围电路之间相接的装置区，例如安装半导体装置200的印刷电路板(printed circuit board，PCB)上的电路。在绘示的实施例中，核心区202包含全绕式栅极核心装置结构206a，用于形成第一全绕式栅极晶体管以用于高速应用；I/O区204包含全绕式栅极I/O装置结构206b，用于形成用于I/O或静电放电应用的第二全绕式栅极晶体管。
装置结构206a和206b各自包含基底208、隔离结构210、鳍片212a或212b，鳍片212a或212b包含垂直堆叠的交替半导体层220和222(也称为堆叠的鳍片212a或212b)，以及接合堆叠的鳍片212a或212b的虚设栅极结构216。
在一些实施例中，基底208包含硅。替代地或额外地，基底208包含其他元素半导体，例如锗；化合物半导体，例如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟及/或锑化铟；合金半导体，例如硅锗(SiGe)、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或前述的组合。在一些实施方式中，基底208包含一或多种III-V族材料、一或多种II-IV族材料或前述的组合。在一些实施方式中，基底208是绝缘体上覆半导体(semiconductor-on-insulator)基底，例如绝缘体上覆硅(silicon-on-insulator，SOI)基底、绝缘体上覆硅锗(silicongermanium-on-insulator，SGOI)基底或绝缘体上覆锗(germanium-on-insulator，GOI))基底。绝缘体上覆半导体基底的制造可以使用布植氧分离(separation by implantation ofoxygen，SIMOX)、晶圆接合及/或其他合适的方法。基底208可以包含根据半导体装置200的设计要求配置的各种掺杂区。P型掺杂区可以包含p型掺质，例如硼、铟、其他p型掺质或前述的组合。N型掺杂区可以包含n型掺质，例如磷、砷、其他n型掺质或前述的组合。在一些实施方式中，基底208包含由p型掺质和n型掺质的组合形成的掺杂区。可以在基底208上及/或基底208中直接形成各种掺杂区，例如提供p井结构、n井结构、双井(dual-well)结构、凸起结构或前述的组合。可以进行离子布植制程、扩散制程及/或其他合适的掺杂制程以形成各种掺杂区。在一些实施例中，在n型井上方形成p型全绕式栅极装置及/或p型鳍式场效晶体管(FinFET)装置，而在p型井上方形成n型全绕式栅极装置及/或n型鳍式场效晶体管装置。装置结构206a和206b各自可以单独地是n型或p型装置。
隔离结构210可以包含氧化硅、氮化硅、氮氧化硅、掺杂氟的硅酸盐玻璃(fluoride-doped silicate glass，FSG)、低介电常数介电材料及/或其他合适的绝缘材料。隔离结构210可以是浅沟槽隔离(shallow trench isolation，STI)部件。可能是其他隔离结构，例如场氧化物、硅局部氧化(Local Oxidation of Silicon，LOCOS)及/或其他合适的结构。隔离结构210可以包含多层结构，例如具有一或多个热氧化物衬层。
堆叠的鳍片212a和212b各自具有交替堆叠的半导体层220和222。半导体层220中的第一半导体材料与半导体层222中的第二半导体材料在材料及/或组成上不同。第一半导体材料和第二半导体材料各自可以包含硅、锗、化合物半导体，包含碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和锑化铟、合金半导体，包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和GaInAsP。在本实施例中，半导体层220包含硅，并且半导体层222包含锗或硅锗合金。堆叠的鳍片212a和212b中的半导体层220和222可以另外包含掺质(例如磷、砷、硼及/或铟)以提高待形成的全绕式栅极晶体管的性能。
堆叠的鳍片212a和212b的形成可以借由在基底208上方外延成长半导体层220和222，然后借由任何合适的方法图案化以形成单独的堆叠的鳍片212a和212b。举例来说，堆叠的鳍片212a和212b可以使用一或多个光微影制程来图案化，包含双重图案化或多重图案化制程。通常而言，双重图案或多重图案制程结合光微影和自对准制程，其允许产生的图案的例如节距(pitches)小于使用单一、直接光微影制程可获得的图案的节距。举例来说，在一实施例中，在基底上方形成牺牲层并使用光微影制程将牺牲层图案化。使用自对准制程在图案化的牺牲层旁边形成间隔物。然后移除牺牲层，接着可以使用剩余的间隔物或心轴(mandrels)借由蚀刻初始半导体层220、222和基底208来图案化堆叠的鳍片212a和212b。蚀刻制程可以包含干式蚀刻、湿式蚀刻、反应离子蚀刻(reactive ion etching，RIE)及/或其他合适的制程。在绘示的实施例中，堆叠的鳍片212a和212b在相同方向上纵向延伸(纵向轴线平行)。在一些实施例中，核心区202中的堆叠的鳍片212a在一方向(例如沿Y方向)上纵向延伸，而I/O区204中的堆叠的鳍片212b可以在不同方向上纵向延伸，例如在垂直方向(例如沿X方向)或其他方向。
虚设栅极结构216为金属栅极堆叠保留区并且包含虚设界面层230、虚设栅极电极232、第一栅极硬遮罩层234和第二栅极硬遮罩层236。在每个堆叠的鳍片212a和212b的顶部和侧壁表面上方以及隔离结构210的顶表面上方形成虚设界面层230。虚设界面层230可以包含介电材料，例如氧化物层(例如SiO2)或氮氧化物层(例如SiON)，并且可以借由化学氧化、热氧化、原子层沉积(atomic layer depositionALD)、化学气相沉积(chemical vapordeposition，CVD)及/或其他合适的方法来沉积。
虚设栅极电极232可以包含多晶硅(poly-Si)并且可以借由合适的沉积制程形成，例如低压化学气相沉积(low-pressure chemical vapor deposition，LPCVD)和等离子体辅助化学气相沉积(plasma-enhanced CVD，PECVD)。第一栅极硬遮罩层234和第二栅极硬遮罩层236各自可以包含一或多层介电材料，例如氧化硅及/或氮化硅，并且可以借由化学气相沉积或其他合适的方法形成。举例来说，第一栅极硬遮罩层234可以包含邻近虚设栅极电极232的氧化硅层，并且第二栅极硬遮罩层236可以包含氮化硅层。可以借由光微影和蚀刻制程将虚设界面层230、虚设栅极电极232、第一栅极硬遮罩层234和第二栅极硬遮罩层236图案化。
为了清楚地描述和说明，图4～图6包含沿图3所示的剖面A-A的全绕式栅极核心装置结构206a的部分剖面图，剖面A-A沿堆叠的鳍片212a的长度方向穿过相应的通道区(在Y-Z平面中)。全绕式栅极I/O装置结构206b在Y-Z平面中的剖面图与图4～图6所示的相似，并为了简化而省略。图7～图20包含半导体装置200沿图3所示的剖面B-B的局部剖面图，剖面B-B沿垂直于堆叠的鳍片212a和212b的长度方向的方向穿过多个通道区(在X-Z平面中)。
在操作104，方法100(图2A)在虚设栅极结构216的侧壁上方形成栅极间隔物238，如图4所示。栅极间隔物238可以包含介电材料，例如氧化硅、氮化硅、氮氧化硅、碳化硅、其他介电材料或前述的组合，并且可以包含一或多层材料。栅极间隔物238可以借由在半导体装置200上方沉积间隔物材料作为毯覆层来形成。然后借由非等向性蚀刻制程蚀刻间隔物材料。间隔物材料在虚设栅极结构216的侧壁上的部分成为栅极间隔物238。操作104进一步在源极/漏极(S/D)区中形成源极/漏极部件240，如图5所示。举例来说，操作104可以蚀刻凹槽进入堆叠的鳍片212a和212b，并在凹槽中外延成长半导体材料。半导体材料可以升高到相应鳍片的顶表面之上。操作104可以为n型和p型装置分别形成源极/漏极部件240。举例来说，操作104可以采用用于n型装置的n型掺杂硅和用于p型装置的p型掺杂硅锗形成源极/漏极部件240。操作104可以进一步在源极/漏极部件240上方形成接触蚀刻停止层(contactetch stop，CESL)242，并在接触蚀刻停止层242上方形成层间介电(inter-layerdielectric，ILD)层244。接触蚀刻停止层242可以包含具有氧(O)或碳(C)元素的氮化硅、氮氧化硅、氮化硅及/或其他材料；并且可以借由化学气相沉积、物理气相沉积(physicalvapor deposition，PVD)、原子层沉积或其他合适的方法形成。层间介电层244可以包含四乙氧基硅烷(tetraethylorthosilicate，TEOS)氧化物、未掺杂的硅酸盐玻璃或掺杂的氧化硅，例如硼磷硅酸盐玻璃(borophosphosilicate glass，BPSG)、熔融硅玻璃(fused silicaglass，FSG)、磷硅酸盐玻璃(phosphosilicate glass，PSG)、掺杂硼的硅玻璃(boron dopedsilicon glass，BSG)及/或其他合适的介电材料。层间介电层244的形成可以借由等离子体辅助化学气相沉积或可流动式化学气相沉积(flowable CVD，FCVD)或其他合适的方法。可以在操作104之后进行化学机械研磨(CMP)制程以移除过多的介电材料。在一些实施例中，化学机械研磨制程也移除栅极硬遮罩234和236并暴露出虚设栅极电极232。
在操作106，方法100(图2A)移除虚设栅极电极232和虚设界面层230，产生栅极沟槽246，如图6所示。操作106可以包含一或多个蚀刻制程，其对虚设栅极电极232和虚设界面层230中的材料有选择性。借由选择抗蚀刻栅极间隔物238和层间介电层244的蚀刻剂，栅极间隔物238和层间介电层244暴露在栅极沟槽246中的部分没有明显的蚀刻损失。这可能会增加光微影制程的耐受度(tolerance)。蚀刻制程可以包含任何合适的蚀刻技术，例如湿式蚀刻、干式蚀刻、反应离子蚀刻、灰化(ashing)及/或其他蚀刻方法。在一范例中，蚀刻制程是干式蚀刻制程，其使用以氟为主的蚀刻剂(例如CF4、CHF3、CH2F2等)。在操作106之后，堆叠的鳍片212a和212b暴露在栅极沟槽246中，如图7所示。
在操作108，方法100(图2A)从栅极沟槽246释放全绕式栅极装置结构206a和206b的通道区中的通道构件，如图8所示。在绘示的实施例中，通道构件是纳米片。用语纳米片在本文中用于表示具有纳米级或甚至微米级尺寸并具有细长形状的任何材料部分，与此部分的剖面形状无关。因此，此用语指代圆形和大致圆形剖面的细长材料部分，以及包含例如圆柱形或大致矩形剖面的梁状或棒状材料部分。为了简化和清楚，在操作108之后，半导体层220被表示为纳米片220。在本实施例中，半导体层220包含晶体硅，并且半导体层222包含硅锗。可以选择性地移除多个半导体层222。在一些实施方式中，选择性移除制程包含使用合适的氧化剂(例如臭氧(O3))来氧化多个半导体层222。此后，可以选择性地移除氧化的半导体层222。为了进一步实施此实施例，操作110包含干式蚀刻制程以选择性地移除半导体层222，例如借由在500℃至700℃的温度下施加HCl气体、或施加CF4、SF6和CHF3的气体混合物。此时，如图8所示，在全绕式栅极核心装置结构206a的通道区和全绕式栅极I/O装置结构206b的通道区形成垂直堆叠的纳米片220。虽然图8对每个堆叠绘示四个纳米片220，但在各种实施例中可以存在更少或更多垂直堆叠的纳米片220。举例来说，每个全绕式栅极装置结构中的纳米片220的数量可以在2至10的范围。
在操作110，方法100(图2A)在纳米片220上形成栅极氧化物层(或称为界面层)248并包覆所有纳米片220。栅极氧化物层248可以包含氧化硅(SiO2)，其可以借由等离子体辅助原子层沉积形成。或者，栅极氧化物层248的形成可以借由化学气相沉积、使用水蒸汽(H2O)或O2的热氧化、或使用例如过氧化氢(H2O2)或臭氧(O3)的氧化剂的气相或液相化学氧化。栅极氧化物层248具有适合核心应用的厚度，例如约
Figure BDA0003790738670000121
至约
Figure BDA0003790738670000122
的厚度。在此阶段，核心区202和I/O区204上的栅极氧化物层248的厚度大致相同。为了清楚，栅极氧化物层248包覆全绕式栅极核心装置结构206a的纳米片220的部分表示为栅极氧化物层248a；栅极氧化物层248包覆全绕式栅极I/O装置结构206b的纳米片220的其他部分表示为栅极氧化物层248b。
在操作112，方法100(图2A)在栅极沟槽246中形成高介电常数介电层250，如图10所示，借此分别在全绕式栅极核心装置结构206a和全绕式栅极I/O装置结构206b的通道区中形成栅极介电层252a和252b(统称为栅极介电层252)。为了清楚，高介电常数介电层250包覆全绕式栅极核心装置结构206a的栅极氧化物层248a的部分表示为高介电常数介电层250a；高介电常数介电层250包覆全绕式栅极I/O装置结构206b的栅极氧化物层248b的其他部分表示为高介电常数介电层250b。换言之，栅极介电层252a包含包覆全绕式栅极核心装置结构206a的纳米片220的栅极氧化物层248a以及包覆栅极氧化物层248a的高介电常数介电层250a，而栅极介电层252b包含包覆全绕式栅极I/O装置结构206b的纳米片220的栅极氧化物层248b以及包覆栅极氧化物层248b的高介电常数介电层250b。在绘示的实施例中，栅极氧化物层248a和248b以及高介电常数介电层250a和250b被沉积为大致共形的层。核心区202和I/O区204上方的高介电常数介电层250的厚度大致相同。高介电常数介电层250的沉积可以使用任何合适的技术，例如原子层沉积、化学气相沉积、金属有机化学气相沉积(metal-organic CVD，MOCVD)、物理气相沉积、热氧化、前述的组合及/或其他合适的技术。高介电常数介电层250可以包含金属氧化物(例如LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfZrO、HfLaO、HfTaO、HfTiO、(Ba，Sr)TiO3(BST)、Al2O3等)、金属硅酸盐(例如HfSiO、LaSiO、AlSiO等)、金属或半导体氮化物、金属或半导体氮氧化物、前述的组合及/或其他合适的材料。在具体范例中，高介电常数介电层250的厚度为约
Figure BDA0003790738670000131
至约
Figure BDA0003790738670000132
在操作114，方法100(图2A)在核心区202和I/O区204两者中沉积厚度调制层260，如图11所示。厚度调制层260包覆栅极介电层252a和252b，也被称为盖层260。厚度调制层260可以包含一或多个材料层。厚度调制层260包含对来自周围环境的氧具有更高亲和力的材料。如将在下文进一步详细解释的，厚度调制层260将有助于将氧从周围环境转移到栅极氧化物层248b下方的纳米片220的晶体硅的顶部，用于栅极氧化物再成长制程。厚度调制层260可以是金属层，其包含金属或金属化合物(例如金属氮化物)，例如TiN、AlN、WN或前述的组合，例如TiAlN或TiAlC。厚度调制层260也可以由金属氧化物形成，例如TiO、AlO或前述的组合。沉积方法包含物理气相沉积、化学气相沉积、原子层沉积或其他合适的方法。选择厚度调制层260的厚度，使得相邻包覆的通道构件之间的间隙(具有图11表示的垂直距离“d”)不闭合。在一些实施例中，垂直距离d至少为0.9nm，这使得厚度调制层260能够从所有方向吸收来自周围环境的氧并大致均匀地输送到下方的纳米片220。厚度调制层260的厚度可以为约
Figure BDA0003790738670000141
至约
Figure BDA0003790738670000142
厚度小于
Figure BDA0003790738670000143
可能无法提供足够的氧亲和性，而厚度大于
Figure BDA0003790738670000144
可能会关闭相邻包覆的通道构件之间的间隙、或者需要通道构件之间更大的距离来容纳如此厚的盖层，进而增加装置长宽比。
在操作116，方法100(图2B)沉积牺牲层262包覆厚度调制层260，如图12所示。在绘示的实施例中，牺牲层262填充相邻包覆的纳米片220之间的间隙，并在间隙外具有约
Figure BDA0003790738670000145
至约
Figure BDA0003790738670000146
的厚度。牺牲层262作为占位元件并保留相邻包覆的纳米片220之间的间隙，以防止在后续制程中使用的化学物质(例如光阻材料)泄漏到相对狭窄的间隙中并密封间隙。牺牲层262可以包含一或多个材料层。在绘示的实施例中，牺牲层262包含在填充窄间隙中表现出强间隙填充能力并在随后的选择性蚀刻制程中相对容易移除的良好蚀刻对比度的材料。在一些实施例中，牺牲层262是金属氧化物层。在进一步的实施例中，牺牲层262包含富含金属的AlO，例如约1.05：1或约2：1的Al：O比率。沉积方法包含物理气相沉积、化学气相沉积、原子层沉积或其他合适的方法。
在操作118，方法100(图2B)从全绕式栅极装置结构206a和206b的顶部和外侧壁表面部分地移除牺牲层262，其中保留牺牲层262堆叠在相邻包覆的纳米片220之间的部分，如图13所示。可以例如借由湿式蚀刻、干式蚀刻、反应离子蚀刻或其他合适的蚀刻方法移除牺牲层262。在一范例中，在非等向性蚀刻制程中部分地移除牺牲层262，使得堆叠在相邻包覆的纳米片220之间的牺牲层262的部分完好无损。在另一范例中，在湿式蚀刻制程中部分地移除牺牲层262。(例如借由计时器)控制蚀刻时间，使得牺牲层262堆叠在相邻包覆的纳米片220之间的部分由于负载效应(loading effect)而比暴露在间隙之外的其他部分蚀刻得更慢并大致保留。
在操作120，方法100(图2B)形成覆盖全绕式栅极I/O装置结构206b并暴露出全绕式栅极核心装置结构206a的图案化遮罩层264，如图14所示。在一些实施例中，遮罩层264是光阻层，例如底部抗反射涂层(bottom antireflective coating，BARC)层。牺牲层262堆叠在相邻包覆的纳米片220之间的剩余部分防止遮罩层264的光阻材料泄漏到间隙中，这是难以移除的。在形成遮罩层264时，操作120可以包含微影制程(例如光微影或电子束微影)，其可以更包含光阻涂层(例如旋转涂布)、软烘烤、遮罩对准、曝光、曝光后烘烤、光阻显影、冲洗、干燥(例如旋转干燥及/或硬烘烤)、其他合适的微影技术及/或前述的组合。
在操作122，方法100(图2B)在蚀刻制程中从全绕式栅极核心装置结构206a移除厚度调制层260和牺牲层262，如图15所示。蚀刻制程可以包含任何合适的蚀刻技术，例如湿式蚀刻、干式蚀刻、反应离子蚀刻、灰化及/或其他蚀刻方法。在一范例中，蚀刻制程是使用以氟为主的蚀刻剂(例如CF4、CHF3、CH2F2等)的干式蚀刻制程或使用以HF为主的湿式蚀刻剂的湿式蚀刻制程。在操作122之后，可以移除遮罩层264，例如借由蚀刻、灰化或光阻剥除。此时，仅保留全绕式栅极I/O装置结构206b中的厚度调制层260和牺牲层262，如图16所示。
在操作124中，从全绕式栅极I/O装置结构206b中移除堆叠在相邻包覆的纳米片220之间的间隙之间的牺牲层262的剩余部分，如图17所示。牺牲层262的移除可以例如借由湿式蚀刻制程。在一些实施例中，湿式蚀刻制程可以包含在稀氢氟酸(DHF)、氢氧化钾(KOH)溶液、氨、含有氢氟酸(HF)、硝酸(HNO3)及/或乙酸(CH3COOH)的溶液或其他合适的湿式蚀刻剂中蚀刻。此时，仅保留在全绕式栅极I/O装置结构206b中的包覆栅极介电层252b的厚度调制层260，并且此厚度调制层260完全被周围环境包围。
在操作126，方法100(图2B)进行退火制程(由图18中的箭头270所示)以在栅极氧化物层248b上启动氧化物再成长制程，使得全绕式栅极I/O装置结构206b中的纳米片220被消耗并化学转化为氧化硅。在一些实施例中，全绕式栅极I/O装置结构206b中的整个氧化物层的厚度可以增加约30％至约50％。退火制程包含具有含氧周围环境的尖波退火(spikeannealing)制程，初始温度在约500℃和约700℃之间，并且峰值温度在约700℃和约900℃之间。在升高的温度下，厚度调制层260从周围环境中吸收氧并经由扩散将氧输送到下方的层中。先前由牺牲层262保留的相邻包覆的通道构件之间的间隙允许厚度调制层260从所有方向大致均匀地吸收氧。
图18也绘示I/O区204中的区域272的放大图。箭头274被绘示以指示由于厚度调制层260的氧传输而导致的区域272中氧原子的移动。当氧原子到达栅极氧化物层248b和纳米片220之间的界面时，氧原子与纳米片220的硅原子发生化学反应并形成氧化硅。因此，在栅极氧化物层248b下方形成额外的氧化硅层221。额外的氧化硅层221是借由消耗纳米片220外部的晶体硅形成的，导致全绕式栅极I/O装置结构206b中纳米片220的宽度和高度尺寸都缩小。在一些实施例中，全绕式栅极I/O装置结构206b中的通道构件的宽度和高度(在X-Z平面中)各自变得比全绕式栅极核心装置结构206a中的宽度和高度小约
Figure BDA0003790738670000161
至约
Figure BDA0003790738670000162
相较于栅极氧化物层248b，额外氧化硅层221中的氧化物组成由于不同的成长制程可能具有较小的密度。举例来说，借由气相H2O2化学氧化制程形成的栅极氧化物层248b可以具有约2.65g/cm3的氧化硅密度，而借由在退火制程270下由硅消耗形成的额外氧化硅层221可以具有约2.55g/cm3的氧化硅密度。在一些实施例中，额外的氧化硅层221是氧化硅和硅的混合化合物，使得氧化硅在靠近栅极氧化物层248b处具有较高的莫耳百分比，并在远离栅极氧化物层248b处具有较低的莫耳百分比。在进一步的实施例中，额外的氧化硅层221是氧化硅和晶体硅的混合化合物。或者，氧原子侵入硅的晶格和尖波退火制程可能会破坏晶格并导致氧化硅和多晶硅或非晶硅的混合化合物。栅极氧化物层248b和额外的氧化硅层221统称为栅极氧化物层248b’，相较于核心区202中的栅极氧化物层248a具有增加的厚度。
退火制程也将氧从厚度调制层260输送至高介电常数介电层250b中。高介电常数介电层250b因此可以具有比高介电常数介电层250a中更高的氧浓度。此外，高介电常数介电层250b中氧的莫耳百分比可以具有梯度，当靠近厚度调制层260时较高，而当远离厚度调制层260时较低。在退火制程期间，厚度调制层260的底部中的金属元素也可以与高介电常数介电层250b的顶部混合以形成混合化合物。举例来说，当高介电常数介电层250b包含Hf且厚度调制层260包含Ti时，混合化合物可以包含合金氧化物HfTiO。此外，在退火制程期间，高介电常数介电层250b的底部可以与栅极氧化物层248b的顶部混合以形成金属硅酸盐。举例来说，当高介电常数介电层250b包含Hf时，金属硅酸盐为硅酸铪(HfSiO4)。在特定范例中，在退火制程之后，高介电常数介电层250b的顶部包含合金氧化物(例如HfTiO)、中间部分包含高介电常数金属氧化物(例如HfO2)以及底部包含金属硅酸盐(例如HfSiO4)。作为比较，核心区202中的高介电常数介电层250a包含大致均匀分布的高介电常数金属氧化物(例如HfO2)。
在操作128，方法100(图2B)在选择性蚀刻制程中移除厚度调制层260，暴露出栅极沟槽246中的栅极介电层252a和252b，如图19所示。选择性蚀刻制程可以包含干式蚀刻、湿式蚀刻、反应离子蚀刻(RIE)及/或其他合适的制程。由于栅极氧化物层248a和248b’的厚度不同，核心区202中的栅极介电层252a的厚度小于I/O区204中的栅极介电层252b的厚度。
在操作130，方法100(图2B)在栅极沟槽246中形成栅极电极层282，分别在核心区202和I/O区204中包覆栅极介电层252a和252b。栅极电极层282是包含一或多个金属层的导电层，例如一(些)功函数金属层、一(些)导电阻挡层和一(些)金属填充层。对于可以使用不同金属层的n型和p型晶体管，可以分别形成栅极电极层282。功函数金属层可以是p型或n型功函数层。p型功函数层包含有效功函数足够大的金属，选自但不限于氮化钛(TiN)、氮化钽(TaN)、钌(Ru)、钼(Mo)、钨(W)、铂(Pt)或前述的组合的群组。n型功函数层包含有效功函数足够低的金属，选自但不限于钛(Ti)、铝(Al)、碳化钽(TaC)、碳化钽(TaCN)、钽氮化硅(TaSiN)、钛硅氮化物(TiSiN)或前述的组合的群组。栅极电极层282可以包含多个功函数金属层，例如第一金属层和第二金属层。作为范例，第一金属层可以包含TiN，并且第二金属层可以包含TiAl或Ti、Ta、C、Al的其他组合，例如TiAlC或TaAlC。栅极电极层282也包含金属填充层。金属填充层可以包含铝(Al)、钨(W)、钴(Co)及/或其他合适的材料。在各种实施例中，栅极电极层282的金属填充层的形成可以借由电镀、原子层沉积、物理气相沉积、化学气相沉积、电子束蒸镀或其他合适的制程。在各种实施例中，可以进行化学机械研磨制程以从栅极堆叠的金属层移除过多的金属，借此提供大致平坦的顶表面。
在方法100(图2B)的操作132，半导体装置200可以经历进一步制程以形成本技术领域已知的各种部件和区域。举例来说，后续制程可以形成接触开口、接触金属以及各种接触件/导孔(vias)/线和多层互连部件(例如金属层和层间介电质)，其被配置以连接各种部件以形成功能电路，功能电路可以包含一或多个多栅极装置。在进一步范例中，多层互连可以包含例如导孔或接触件的垂直互连，以及例如金属线的水平互连。各种互连部件可以采用各种导电材料，包含铜、钨及/或硅化物。在一范例中，使用镶嵌及/或双镶嵌制程来形成铜相关的多层互连结构。此外，可以在方法100之前、期间和之后实施额外的制程步骤，并且可以根据方法100的各种实施例替换或消除上述的一些制程步骤。
本实用新型实施例的一或多个实施例为半导体装置及其形成提供许多益处，但并非用于限制。举例来说，本实用新型实施例在同一基底上和同一集成电路中提供多栅极高速晶体管和多栅极高压晶体管。多栅极高速晶体管，例如全绕式栅极高速晶体管，放置在集成电路的核心区中，用于实现高速电路或SRAM，而多栅极高压晶体管，例如全绕式栅极高压晶体管，放置在集成电路的I/O区中，用于实现I/O电路或静电放电电路。多栅极高速装置和多栅极高压装置具有不同的栅极氧化物层厚度，以在不同区域产生性能差异。本实施例使电路设计者能够借由选择不同的栅极氧化物厚度来最佳化集成电路不同区域中的电路。
在一例示性面向，本实用新型实施例关于一种方法。此方法包含一种方法。此方法包含在基底上方提供具有第一通道构件和第二通道构件的结构，其中第一通道构件位于结构的第一区中，并且第二通道构件位于结构的第二区中；在第一通道构件上方形成第一氧化物层并在第二通道构件上方形成第二氧化物层；在第一氧化物层上方形成第一介电层并在第二氧化物层上方形成第二介电层；在第二介电层上方而非第一介电层上方形成盖层；以及进行退火制程以增加盖层下方的第二氧化物层的厚度。在一些实施例中，盖层的形成包含在第一介电层和第二介电层上方沉积盖层；在第二介电层上方形成覆盖盖层的一部分之图案化遮罩；以及从第一介电层移除盖层的另一部分。在一些实施例中，此方法更包含在盖层上方沉积牺牲层；以及蚀刻牺牲层的多个垂直部分，而第一区中的牺牲层的第一水平部分和第二区中的牺牲层的第二水平部分保持大致完整。在一些实施例中，此方法更包含在蚀刻牺牲层的垂直部分之后，形成图案化遮罩覆盖牺牲层的第一水平部分和第二介电层上方的盖层；以及蚀刻牺牲层的第二水平部分。在一些实施例中，牺牲层是金属氧化物层。在一些实施例中，盖层是金属氮化物层。在一些实施例中，退火制程的进行包含尖波退火制程，其具有含氧周围环境、摄氏约500度至摄氏约700度的初始温度以及摄氏约700度至摄氏约900度的峰值温度。在一些实施例中，第一氧化物层和第二氧化物层的形成包含用H2O2处理第一通道构件和第二通道构件。在一些实施例中，第一区是结构的核心区且第二区是结构的输入/输出(I/O)区。在一些实施例中，在进行退火制程之后，第二氧化物层的厚度比第一氧化物层的厚度大约30％至约50％。
在另一例示性面向，本实用新型实施例关于一种方法。此方法包含在第一鳍片中形成多个第一悬浮层并在第二鳍片中形成多个第二悬浮层；形成包覆环绕第一鳍片中的第一悬浮层的第一界面层和包覆环绕第二鳍片中的第二悬浮层的第二界面层；形成包覆环绕第一界面层的第一高介电常数介电层和包覆环绕第二界面层的第二高介电常数介电层；沉积包覆环绕第一高介电常数介电层和第二高介电常数介电层的金属层；从第一高介电常数介电层移除金属层；进行退火制程，其中在退火制程期间，周围环境中的氧被驱动经过金属层、第二高介电常数介电层和第二界面层并到达第二悬浮层的外部，使得第二悬浮层的外部转化为氧化物层；以及沉积包覆环绕第一高介电常数介电层的第一栅极电极层和包覆环绕第二高介电常数介电层的第二栅极电极层。在一些实施例中，此方法更包含在进行退火制程之后，从第二高介电常数介电层移除金属层。在一些实施例中，此方法更包含在从第一高介电常数介电层移除金属层之前，沉积牺牲层填充相邻的第二悬浮层之间的间隙；以及形成图案化遮罩覆盖第二鳍片。在一些实施例中，在沉积牺牲层之后，牺牲层也填充相邻的第一悬浮层之间的间隙。在一些实施例中，金属层包含TiN、AlN、TiAlN、WN和TiAlC之一。在一些实施例中，从第二悬浮层的外部转化之氧化物层的厚度为第一界面层的厚度的约30％至约50％。
在另一例示性面向，本实用新型实施例关于一种集成电路。此集成电路包含具有第一区和第二区的基底；位于第一区中的第一全绕式栅极(GAA)装置，第一全绕式栅极装置包含沿第一方向纵向延伸的第一通道构件，以及包覆第一通道构件的通道区的第一栅极结构，第一栅极结构包含第一界面层；以及位于第二区中的第二全绕式栅极装置，第二全绕式栅极装置包含沿第一方向纵向延伸的第二通道构件，以及包覆第二通道构件的通道区的第二栅极结构，第二栅极结构包含第二界面层，第二界面层具有邻近第二通道构件的第一部分和在第一部分上方的第二部分，第一部分的密度小于第二部分的密度。在一些实施例中，第二界面层的第一部分具有在第二方向上测量的第一厚度，第二方向大致垂直于第一方向，第二界面层的第二部分具有在第二方向上测量的第二厚度，并且第一界面层具有在第二方向上测量的第三厚度，并且其中第二厚度大致等于第三厚度。在一些实施例中，第一厚度为第二厚度的约30％至约50％。在一些实施例中，第二界面层的第一部分是氧化硅和硅的复合层。
以上概述数个实施例的部件，使得本技术领域中具有通常知识者可以更加理解本实用新型实施例的多个面向。本技术领域中具有通常知识者应该理解，他们能轻易地以本实用新型实施例为基础，设计或修改其他制程和结构，以达到与本文介绍的实施例相同的目的及/或优点。本技术领域中具有通常知识者也应该理解，此类等效的结构未悖离本实用新型实施例的精神与范围，并且他们能在不违背本实用新型实施例的精神和范围下，做各式各样的改变、取代和调整。

Claims (10)

1.一种集成电路，其特征在于，
一基底，具有一第一区和一第二区；
一第一全绕式栅极装置，位于该第一区中，该第一全绕式栅极装置包含：
一第一通道构件，沿一第一方向纵向延伸，以及
一第一栅极结构，包覆该第一通道构件的通道区，该第一栅极结构包含一第一界面层；以及
一第二全绕式栅极装置，位于该第二区中，该第二全绕式栅极装置包含：
一第二通道构件，沿该第一方向纵向延伸，以及
一第二栅极结构，包覆该第二通道构件的通道区，该第二栅极结构包含一第二界面层，该第二界面层具有邻近该第二通道构件的一第一部分和在该第一部分上方的一第二部分，该第一部分的密度小于该第二部分的密度。
2.如权利要求1所述的集成电路，其特征在于，该第二界面层的该第一部分具有在一第二方向上测量的一第一厚度，该第二方向垂直于该第一方向，该第二界面层的该第二部分具有在该第二方向上测量的一第二厚度，并且该第一界面层具有在该第二方向上测量的一第三厚度，并且其中该第二厚度等于该第三厚度。
3.如权利要求2所述的集成电路，其特征在于，该第一厚度为该第二厚度的30％至50％。
4.如权利要求2或3所述的集成电路，其特征在于，该第三厚度为
Figure FDA0003790738660000011
至
Figure FDA0003790738660000012
5.如权利要求1至3中任一项所述的集成电路，其特征在于，该第二界面层的该第一部分是氧化硅和硅的复合层。
6.如权利要求1至3中任一项所述的集成电路，其特征在于，该第二界面层的该第一部分的该密度为2.55g/cm3。
7.如权利要求1至3中任一项所述的集成电路，其特征在于，该第一区是核心区且该第二区是输入/输出区。
8.如权利要求1所述的集成电路，其特征在于，该第一通道构件具有在一第二方向上测量的一第一厚度，该第二方向垂直于该第一方向，该第二通道构件具有在该第二方向上测量的一第二厚度，并且其中该第一厚度大于该第二厚度。
9.如权利要求8所述的集成电路，其特征在于，该第一厚度比该第二厚度大
Figure FDA0003790738660000021
至
Figure FDA0003790738660000022
10.如权利要求1至3中任一项所述的集成电路，其特征在于，该第一栅极结构更包含一第一高介电常数介电层包覆该第一界面层，该第二栅极结构更包含一第二高介电常数介电层包覆该第二界面层，并且其中该第一高介电常数介电层与该第二高介电常数介电层具有相同的厚度，该厚度系在垂直于该第一方向的一第二方向上测量。
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