CN114121947A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN114121947A
CN114121947A CN202110848839.0A CN202110848839A CN114121947A CN 114121947 A CN114121947 A CN 114121947A CN 202110848839 A CN202110848839 A CN 202110848839A CN 114121947 A CN114121947 A CN 114121947A
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China
Prior art keywords
source
layer
fin
fin structure
gate
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CN202110848839.0A
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Inventor
杨智铨
林京毅
苏信文
林士豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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Abstract

方法和装置提供设置在基底上的第一鳍片结构、第二鳍片结构和第三鳍片结构。介电鳍片是形成在第一鳍片结构与第二鳍片结构之间，且导线是形成在第二鳍片结构与第三鳍片结构之间。

Description

半导体装置
技术领域
本发明是有关于一种半导体装置及其制造方法，特别是有关于具有嵌入 式导线的半导体装置及其制造方法。
背景技术
半导体集成电路(integrated circuit，IC)产业已历经了指数式成长。集成电 路材料及设计的技术的进步造成集成电路世代的产生，每一世代的电路比前 一世代更小且更复杂。在集成电路的发展过程中，通常增加了功能密度(即每 芯片面积中互连的装置数量)，而降低了几何尺寸(即使用制程所能创造的最 小组件(或线路))。这种微缩化制程一般可通过增加生产效率及降低相关成本 以提供许多利益。这样的微缩化也增加了集成电路的生产和制程的复杂度。
举例而言，随着集成电路(IC)技术朝向更小的技术节点发展，开始导入 多栅极装置以增加栅极-通道耦合、降低关闭状态(off-state)的电流，以及降低 短通道效应(short-channel effect，SCE)。通常将多栅极装置视作具有栅极结 构或其部分设置于通道区的多侧上的装置。鳍式场效晶体管(fin-like field effect transistor，FinFET)是多栅极装置的一个范例，其已成为在高效能与低 漏电的应用中常见且有潜力的候选。鳍式场效晶体管具有由栅极包覆多侧的 抬升通道(例如栅极包覆从基底延伸的半导体材料的「鳍片(fin)」的顶部及侧 壁)。另一种多栅极装置类型包含环绕式栅极晶体管(surroundinggate transistor，SGT)或全绕式栅极(gate-all-around，GAA)晶体管，其栅极结构环 绕通道区。全绕式栅极晶体管的通道区可由纳米线(nanowire)、纳米片 (nanosheet)或其他纳米结构形成，因此，可将此晶体管称为纳米线晶体管或 纳米片晶体管。
缩小装置尺寸的一项挑战在于经由缩小尺寸的部件仍能维持足够的效 能。举例而言，随着制程规模的缩小，互连线路变得越来越小。较小的互连 线路会表现出较大的电阻，这会对装置效能产生冲击。因此，尽管形成装置 的传统方法对于它们原先预期的目标通常已足够，但它们仍未在各方面都完 全令人满意。
发明内容
在一示范态样中，本发明实施例是关于半导体装置。装置包含从基底延 伸的第一鳍片结构、第二鳍片结构和第三鳍片结构。第一源极/漏极部件是形 成在第一鳍片结构上。第二源极/漏极部件是形成在第二鳍片结构上。第三源 极/漏极部件是形成在第三鳍片结构上。介电分离结构在第一源极/漏极部件 与第二源极/漏极部件之间延伸。导线是设置在第二源极/漏极部件与第三源 极/漏极部件之间。
在另一较广的实施例中，半导体装置包含具有第一晶体管和第二晶体管 的存储器单元。第一晶体管的第一源极/漏极部件是形成在凹陷的第一鳍片结 构上。第二晶体管的第二源极/漏极部件是形成在凹陷的第二鳍片结构上。电 源线是设置在第一源极/漏极部件与第二源极/漏极部件之间。
在此处讨论的另一实施例中提供方法。方法包含提供设置在基底上的第 一鳍片结构、第二鳍片结构和第三鳍片结构。在第一鳍片结构与第二鳍片结 构之间形成介电鳍片。在第二鳍片结构与第三鳍片结构之间形成导线。方法 包含形成延伸至第二鳍片结构、导线和第三鳍片结构上的栅极结构。将第一 鳍片结构、第二鳍片结构和第三鳍片结构各自的源极/漏极区凹陷。分别在第 一鳍片结构、第二鳍片结构和第三鳍片结构上外延成长第一源极/漏极部件、 第二源极/漏极部件和第三源极/漏极部件。
附图说明
从以下的详述配合所附图式可更加理解本发明实施例。要强调的是，根 据工业上的标准做法，各个部件并未按照比例绘制，且仅用于说明的目的。 事实上，为了能清楚地讨论，可任意地放大或缩小各个部件的尺寸。
图1是根据本发明实施例的一或多个态样，显示半导体装置的形成方法 的流程图。
图2、图3、图4、图5、图6、图7、图8、图9A、图10B、图11、图 12A、图13A、图15A和图15B图是根据本发明实施例的一或多个态样，显 示在依照图1的方法的制程期间结构的部分剖面示意图。
图12B和图13C是根据本发明实施例的一或多个态样，显示在依照图1 的方法的制程期间结构的变化的部分剖面示意图。
图9B、图10C、图14B和图15C是根据本发明实施例的一或多个态样， 显示依照图1的方法，与制程相关的布局(layout)的部分俯视图。
图10A、图13B和图14A是根据本发明实施例的一或多个态样，显示依 照图1的方法，与制程相关的部分透视图。
图16是使用本发明实施例的态样，在一些实施例中可实施的装置示意 图。
其中，附图标记说明如下：
100：方法
102：方框
104：方框
106：方框
108：方框
110：方框
112：方框
114：方框
116：方框
118：方框
120：方框
122：方框
124：方框
126：方框
128：方框
130：方框
132：方框
200：半导体装置
202：基底
202A：基座部分
203：隔离部件
204：堆叠
206：牺牲层
208：通道层
210：硬遮罩层
212：鳍片结构
212-1：鳍片
212-2：鳍片
212-3：鳍片
212-4：鳍片
212-5：鳍片
402：包覆层
502：介电层
502’：剩余部分
602：介电层
702：导线
702-1：导线
702-2：导线
802：开口
902：盖层
904：介电鳍片
1002：虚设栅极结构
1004：沟槽
1004-1：沟槽
1004-2：沟槽
1004-3：沟槽
1004-4：沟槽
1004-5：沟槽
1102：遮罩元件
1104：开口
1302：源极/漏极部件
1302-1：源极/漏极部件
1302-2：源极/漏极部件
1302-3：源极/漏极部件
1302-4：源极/漏极部件
1302-5：源极/漏极部件
1304：导电衬层
1400：金属栅极结构
1400’：栅极结构
1404：虚设区
1406：接触蚀刻停止层
1408：导孔
1410：金属化物
1600：SRAM单元
PD-1：下拉晶体管
PD-2：下拉晶体管
PG-1：传送闸晶体管
PG-2：传送闸晶体管
PU-1：上拉晶体管
PU-2：上拉晶体管
具体实施方式
以下公开提供了许多不同的实施例或范例，用于实施提供的主题的不同 部件(feature)。组件和配置的具体范例描述如下，以简化本发明实施例。当 然，这些仅仅是范例，并非用以限定本发明的实施例。举例而言，以下叙述 中提及第一部件形成于第二部件上或上方，可能包含第一与第二部件直接接 触的实施例，也可能包含额外的部件形成于第一与第二部件之间，使得第一 与第二部件不直接接触的实施例。此外，本发明实施例在各种范例中可能重 复参考数字及/或字母，此重复是为了简化和清楚的目的，并非在讨论的各种 实施例及/或组态之间指定其关系。
再者，在此可使用空间相对用词，例如「在……下方」、「在……下」、 「下方的」、「在……上」、「上方的」及类似的用词以助于描述图中所示 的其中一个元件或部件相对于另一(些)元件或部件之间的关系。这些空间相 对用词是用以涵盖图式所描绘的方向以外，使用中或操作中的装置的不同方 向。设备可能被转向(旋转90度或其他方向)，且可与其相应地解释在此使用 的空间相对描述。再者，除非另有说明，当用「约」、「大约」及相似的用 词来描述一个数字或一个数字范围时，所述用词涵盖在所述数字的+/-10％内 的数字。举例而言，用词「约5nm」可涵盖4.5nm至5.5nm的尺寸范围。
如上所述，多栅极晶体管也可指鳍式场效晶体管(FinFET)、环绕式栅极 晶体管(SGT)、全绕式栅极(GAA)晶体管、纳米片晶体管或纳米线晶体管。它 们可为N型或P型。尽管在此讨论的实施方式为全绕式栅极晶体管，但重要 的是，要注意本发明实施例也适用于其他装置组态，包含但不限于鳍式场效 晶体管装置。举例而言，以下讨论的鳍片结构212是指具有通道和牺牲层交 替的堆叠的全绕式栅极装置，也可为鳍式场效晶体管装置的鳍片结构(例如硅 鳍片)。
本发明实施例大体上关于提供互连线路在主动区之间的区域且延伸至基 底上的装置和方法，互连线路例如在源极/漏极部件之间并与源极/漏极部件 共平面，以及在栅极结构之间及/或与栅极结构共平面。这是指将导线嵌入于 装置中。
本发明实施例认为当装置缩小时，传送信号及/或电力往返晶体管或前述 的组件的金属化层变得越来越小，因此增加电阻。对于一些装置类型，这种 增加的电阻有害于装置效能。举例而言，缩小静态随机存取存储器(static random access memory；SRAM)单元(cell)意味着增加SRAM电源线的电阻。 对于SRAM装置，Vccmin为维持SRAM运行所需的最低电压。随着金属化 层(包含传送Vcc的电源线)的缩小，线路的电阻也随之增加。由于IR压降较 大的缘故，如此增加的电阻可能冲击电压Vcc。可能因此增加Vccmin及/或 使SRAM的运行(例如读取或写入)失败。举例而言，一些实施例中，离单元 最远的金属化线路可能大幅下降，导致SRAM的运行(例如写入)失败。
本发明实施例的制程和结构能够改善装置结构的效能，例如包含缩小及/ 或改善标准单元的效能。如上所讨论，在此讨论的某些实施例是以全绕式栅 极(GAA)晶体管的方式呈现，然而，可理解在此讨论的方法和结构也可应用 于其他结构，例如鳍式场效晶体管的鳍片结构。再者，以下讨论的内容为本 发明实施例关于SRAM装置的某些态样的实施方式(例如见图15A-图15C)， 然而，其他装置类型也可从本发明实施例的态样中受益。
本文讨论的嵌入式金属化线路适合传送电力或其他信号往返基底上的装 置，且金属化线路可形成于基底上的一或多个位置。在一些以下讨论的实施 例中，形成金属化线路使得在晶体管的源极/漏极区形成装置的接触。在一些 以下讨论的实施例中，形成金属化线路使得在IC的虚设区中形成栅极结构 或相邻于栅极结构的接触。虚设区中的栅极结构可提供对金属化线路的连接 的传导路径，但并非功能性晶体管的功能性栅极。如此对于晶体管的源极/ 漏极和虚设装置的栅极的配置可一起用于布线横跨晶圆的单一金属化线路 (例如Vdd或Vss)，或用于布线横跨晶圆的这些金属化线路中的单一者以及 此单一金属化线路的多个接触。换言之，可独立实施在源极/漏极部件之间且 与源极/漏极部件耦接的金属化线路。可独立实施在虚设区中栅极结构之间且 与栅极结构耦接的金属化线路。
现在参见图1，显示制造半导体装置200的方法100，半导体装置200 的部分剖面示意图显示于图2、图3、图4、图5、图6、图7、图8、图9A、 图10B、图11、图12A、图12B、图13A、图13C、图15A和图15B中，半 导体装置200的部分透视图显示于图10A、图13B和图14A中，且与半导体 装置200相关的布局部分俯视图显示于图9B、图10C、图14B和图15C中。 方法100仅为例示，并非用以将本发明实施例限定于本文明确显示出的内容。 可在方法100的前、中、后提供额外的步骤，且可取代、消除或移动方法的 额外实施例中的一些叙述的步骤。为了简化，本文并未详细描述所有的步骤。 除了在本发明实施例的图式中明确显示出的内容的外，半导体装置200可包 含额外的晶体管、双极性接面晶体管、电阻、电容、二极管、熔丝等。除非 另有说明或描述，否则本发明实施例通篇使用相似的参考数字来表示相似的 部件。
方法100始于方框102，在此步骤中接收基底。参见图2的范例，提供 基底202。在一实施例中，基底202可为硅(Si)基底。一些其他的实施例中， 基底202可包含其他半导体，例如锗(Ge)、硅锗(SiGe)或III-V族半导体材料。III-V族半导体材料的范例可包含砷化镓(GaAs)、磷化铟(InP)、磷化镓(GaP)、 氮化镓(GaN)、磷化镓砷(GaAsP)、砷化铝铟(AlInAs)、砷化铝镓(AlGaAs)、 磷化镓铟(GaInP)和砷化铟镓(InGaAs)。基底202也可包含绝缘层，例如氧化 硅层，以具有绝缘层上覆硅(silicon-on-insulator，SOI)结构或绝缘层上覆锗(germanium-on-insulator，GOI)结构。一些实施例中，基底202可包含一或多 个井区，例如掺杂N型掺质(即磷(P)或砷(As))的N型井区或掺杂P型掺质(即 硼(B))的P型井区，以形成不同类型的装置。可使用离子植入或热扩散以形 成N型井区和P型井区的掺杂。
依然参见图2，可在基底202上设置堆叠204。堆叠204可包含由多个牺 牲层206交错的多个通道层208。通道层208和牺牲层206可具有不同的半 导体成分。牺牲层206和通道层208是一个接着一个交替沉积以形成堆叠 204。一些实施方式中，通道层208是由硅(Si)形成，且牺牲层206是由硅锗 (SiGe)形成。一些实施方式中，牺牲层206中额外的锗含量得以在实质上不 损害通道层208的情况下，选择性地移除或凹陷牺牲层206，如下所讨论。 一些实施例中，可使用外延制程来沉积材料，以形成包含牺牲层206和通道 层208的堆叠204。示范的技术包含化学气相沉积(chemical vapor deposition； CVD)沉积技术(例如气相外延(vapor-phase epitaxy；VPE)及/或超高真空 CVD(ultra-high vacuum CVD；UHV-CVD)、分子束外延(molecular beam epitaxy；MBE)及/或其他合适的制程，但不限于此。注意在图2中显示四(4) 层牺牲层206和三(3)层通道层208交替且垂直地配置。然而，这仅出于说明的目的，并非用以限定权利要求中具体记载的内容。层的数量取决于半导体 装置200的通道构件的期望数量。一些实施例中，通道层208的数量在2与 10之间。为了图案化的目的，可在堆叠204上设置硬遮罩层210。硬遮罩层 210可为单层或多层。在一实施方式中，硬遮罩层210包含氧化硅层和氮化 硅层。
方法100接着进行方框104，在此步骤中形成多个鳍片结构。一些实施 方式中，形成介于鳍片结构之间的隔离部件，例如在鳍片结构的下部分。每 一个鳍片结构定义在基底上的一个主动区。参见图3的范例，形成鳍片结构 212。尽管显示了五(5)个鳍片结构，但这仅出于说明的目的，并非用以限定 权利要求中具体记载的内容。可使用包含光学微影和蚀刻制程的合适的制程 来制造鳍片结构212。光学微影制程可包含在基底202上形成光阻层，将光 阻层对图案进行曝光，实施曝光后烘烤(post-exposure bake)制程，以及对光 阻层进行显影以形成包含光阻层的遮罩元件。一些实施例中，遮罩元件更包 含硬遮罩层210。一些实施例中，可使用电子束(e-beam)微影制程对光阻层进 行图案化以形成遮罩元件。随着技术节点的降低，可使用包含双重图案化或 多重图案化制程的合适的制程以将鳍片结构212图案化。一般而言，双重图 案化或多重图案化制程结合光学微影和自对准制程，得以形成例如具有间距 小于使用单一、直接地光学微影制程可获得的间距的图案。举例而言，在一 实施例中，在基底上形成材料层，并使用光学微影制程将材料层图案化。使 用自对准制程在图案化的材料层旁形成间隙物。然后移除材料层，并使用剩 余的间隙物或心轴(mandrel)将鳍片结构图案化。
上述的遮罩元件可接着在蚀刻鳍片结构212时用于保护基底202及/或堆 叠204的区域。可使用干式蚀刻(例如化学氧化物移除)、湿式蚀刻、反应式 离子蚀刻(reactive ionetching，RIE)及/或其他合适的制程来蚀刻凹陷。也可 使用方法的许多其他实施例以在基底202上形成鳍片结构212。
鳍片结构212在基底202上垂直地(Y方向)延伸，且其长度从基底202 沿着Z方向延伸(例如延伸进入图3的页面中)。每一个鳍片结构212包含从 基底202形成的基座部分，标示为202A，以及从堆叠204的材料形成的上 覆部分。每一个鳍片结构212与邻近的鳍片结构在X方向上间隔一段距离。 在一实施例中，第一个鳍片212-1是用以形成NFET装置，接下来的两个鳍 片212-2和212-3是用以形成PFET装置，以及随后的两个鳍片212-4和212-5 是用以形成NFET装置。然而，其他配置也是可能的。
继续参见图3的范例，形成介于鳍片结构212之间的隔离部件203，也 称为浅沟槽隔离(shallow trench isolation；STI)部件。隔离部件203介于鳍片 结构的底部区域之间。隔离部件203可包含先在基底202上沉积的介电材料， 并以介电材料填充鳍片结构212之间的沟槽。一些实施例中，介电材料可包 含SiO2、氮化硅、氮氧化硅、掺氟硅酸盐玻璃(fluorine-doped silicate glass； FSG)、低介电常数(low-k)的介电质、前述的组合及/或其他本技术领域中已 知合适的材料。在各种范例中，介电材料的沉积可通过CVD制程、次大气 压CVD(subatmospheric CVD；SACVD)制程、流动式CVD制程、原子层沉 积(atomiclayer deposition；ALD)制程、物理气相沉积(physical vapor deposition；PVD)制程或其他合适的制程。隔离部件203可包含多层结构。 在沉积隔离部件203的绝缘材料之后，可实施化学机械平坦化制程以及随后 的回蚀刻(etch back)制程，以提供在隔离部件203顶面上延伸的鳍片结构212 的上部分。一些实施例中，可在基底上及/或在基底内，额外地或替代地形成 场氧化物(field oxide)、局部硅氧化(local oxidation of silicon；LOCOS)部件及 /或其他合适的隔离部件。
方法100接着进行方框106，于此步骤中在鳍片结构上形成包覆层。可 在每一个鳍片结构上形成包覆层。参见图4的范例，在每一个鳍片结构212 上形成包覆层402。一些实施例中，包覆层402可具有与牺牲层206相似的 成分。一些实施方式中，包覆层402同样是牺牲层。在一实施例中，由硅锗 (SiGe)形成包覆层402。一些实施方式中，包覆层402和牺牲层206包含的 成分，在随后制程中通过单一蚀刻剂来露出(release)通道层208的期间，可 选择性地移除牺牲层206和包覆层402，如下所述。在一实施例中，包覆层 402的外延成长可使用气相外延(vapor-phase epitaxy；VPE)、分子束外延 (molecular beam epitaxy；MBE)或其他合适的制程。在一实施例中，包覆层 402的形成可使用沉积制程，例如CVD制程、次大气压CVD(SACVD)制程、 流动式CVD制程、ALD制程、PVD制程或其他合适的制程。在沉积之后，一些实施例中，方框106的操作可包含回蚀刻制程以移除包覆层402的材料， 例如共形地(conformally)沉积在隔离部件203上的包覆层402的材料。一些 实施例中，包覆层402的厚度在大约9nm与大约12nm之间。
方法100接着进行方框108，于此步骤中在鳍片结构上沉积第一介电层， 藉此内衬相邻的鳍片结构之间的开口。第一介电层为形成分离结构的多层中 的一者，分离结构也称为介电鳍片，在相邻的主动区之间，以下会进一步讨 论。参见图5的范例，沉积第一介电层502。一些实施例中，第一介电层502 可包含高介电常数(high-k)的介电质。在一实施例中，第一介电层502可为氮 化硅、碳氮化硅(SiCN)、碳氮氧化硅(SiOCN)或前述的组合。一些实施例中， 介电层502包含HfO2、HfSiO、HfSiO4、HfSiON、HfLaO、HfTaO、HfTiO、 HfZrO、HfAlOx、ZrO、ZrO2、ZrSiO2、AlO、AlSiO、Al2O3、TiO、TiO2、 LaO、LaSiO、Ta2O3、Ta2O5、Y2O3、SrTiO3、BaZrO、BaTiO3、(Ba,Sr)TiO3、HfO2-Al2O3、其他合适的高介电常数介电材料或前述的组合。第一介电层502 的沉积可使用CVD、ALD或其他合适的制程。
方法100接着进行方框110，于此步骤中在第一介电层上形成介于第一 组鳍片结构之间的第二介电层。参见图6的范例，形成介于鳍片212-1与212-2 之间，且也介于鳍片212-3与212-4之间的介电层602。可自相邻的鳍片212-2 与212-3之间，以及相邻的鳍片212-4与212-5之间省略介电层602。在一实 施例中，鳍片212-2和212-3提供第一装置类型(例如PFET)，且鳍片212-4 和212-5提供第二装置(例如NFET)。
一些实施例中，介电层602可为氧化物成分。使用流动式(flowable)化学 气相沉积(chemical vapor deposition；CVD)制程及/或其他制程，提供像是高 深宽比沉积制程(high aspect ratio deposition process；HARP)的合适的间隙填 充技术，以形成介电层602。一些实施方式中，可沉积液态的可流动氧化物 材料，使其流入鳍片212之间的沟槽。一些实施例中，氧化物包含含有硅和 氧的合适材料。可例如通过退火及/或UV辐射来固化氧化物材料。一些实施 方式中，沉积制程过度填充显示的沟槽。在沉积之后，可实施像是化学机械 研磨(chemical mechanical polish，CMP)的平坦化制程。在一实施例中，包覆 层402为这样的平坦化提供合适的蚀刻停止层。
一些实施方式中，在形成介电层602的期间，以遮罩层(未绘示)来覆盖 邻近鳍片212-2与212-3之间以及邻近鳍片212-4与212-5之间的间隔，以避 免介电层602形成在选定的空间内。随后可移除遮罩层。在另一实施方式中， 一开始可将介电层602沉积在邻近鳍片212-2与212-3之间以及邻近鳍片 212-4与212-5之间，随后通过合适的蚀刻制程将其移除。
方法100接着进行方框112，于此步骤中形成介于第二组鳍片结构之间 的导线。在一实施例中，可在为同类型晶体管(例如NFET或PFET)的各主动 区设计的两个鳍片结构之间形成导线。可在鳍片之间的开口内，未形成方框 110的第二介电层的位置形成导线。一些实施例中，在方框110的步骤的前 先实施方框112的步骤，例如将导线图案化于第二组鳍片结构之间，随后在 剩余的鳍片结构之间形成方框110的介电层。
参见图7的范例，在第一介电层502上，分别在鳍片212-2与212-3之 间以及鳍片212-4与212-5之间形成导线702。导线702可包含钨、钌、钴、 钽、钛、铜、前述的组合及/或其他合适的材料。导线702可包含多层结构。 一些实施例中，形成导线702的导电材料是沉积在基底上，且过度填充鳍片 (鳍片结构212)之间的间隔。在沉积之后，可将装置平坦化以移除鳍片(鳍片 结构212)上的导电材料。可通过ALD、电镀、CVD及/或其他合适的制程来 沉积导电材料。
如以下关于图14A和图14B所讨论的，一些实施例中，可在虚设区中(例 如装置200的布局无功能性装置的区域)，在第一个鳍片结构212与第二个鳍 片结构212之间沉积导电材料。可将导电材料定位在虚设区中前述的第一个 鳍片结构212与第二个鳍片结构212之间的位置，使得随后在导线702上且 相邻于导线702形成两个鳍片之间的栅极线路，如下所讨论。
方法100接着进行方框114，于此步骤中修整先前形成在鳍片之间的层， 且在第二介电层和导线上形成第三介电层。一些实施例中，方框114包含选 择性蚀刻第二介电层及/或导线以形成开口，其中第三介电层将形成于前述的 开口中。参见第8图的范例，形成开口802。一些实施例中，蚀刻制程是用 以选择性移除部分的第二介电层602及/或导线702。一些实施例中，并未蚀 刻第一介电层502。一些实施例中，在同时或分开实施第二介电层602和导 线702的蚀刻的情况下，使用遮罩元件来保护部分的装置200。蚀刻制程为 干式蚀刻制程、湿式蚀刻制程或前述的组合。
参见图9A的范例，在第一介电层502和第二介电层602上，且在开口 802内沉积介电层或盖层902。一些实施例中，盖层902可包含高介电常数 的介电材料，例如金属氧化物。高介电常数的介电材料是指与二氧化硅的介 电常数(～3.9)相比，具有较高的介电常数的介电材料。合适的高介电常数的 介电材料可包含氧化铪、氧化锆、氧化钛、氧化钽或氧化铝。一些实施例中， 盖层902可具有与第一介电层502相同的成分。一些实施例中，盖层902的 沉积可使用CVD、流动式CVD及/或其他合适的沉积方法，随后可通过像是 CMP制程的平坦化制程以提供图9A中显示的平坦顶面。
第一介电层502、第二介电层602和第三介电层902在选定的鳍片结构 之间形成分离结构，也称为介电鳍片904。在所示的实施方式中，介电鳍片 904是显示在鳍片212-1与212-2之间，以及在鳍片212-3与212-4之间。
第三介电层902也形成在导线702上，且位于选定的鳍片结构之间。介 电层902可适当地将导线702与上方的结构绝缘，上方的结构包含例如随后 形成的栅极结构。
图9B显示装置200的一部分的实施例的俯视图，包含鳍片212-1至 212-5、介电鳍片904和导线702。图9B的布局进一步显示装置200的额外 的部分，在一些实施例中为第二单元，且此第二单元实质上相似于第8图显 示的装置200。一些实施例中，这些单元为SRAM单元。在进一步的实施例 中，导线702-1提供Vdd连接。在进一步的实施例中，导线702-2提供Vss 连接。要注意的是，导线702是配置为与鳍片结构212平行延伸。
方法100接着进行方框116，于此步骤中，方法在鳍片结构各自的通道 区上提供多个栅极结构。在一实施例中，方法100提供替代栅极制程，且在 方框116的步骤中形成的栅极结构为随后将由金属栅极结构取代的牺牲或虚 设栅极，如下关于方框130所讨论的部分。可将虚设栅极放置在鳍片结构的 通道区上，介于鳍片结构的两个源极/漏极区之间的区域。当实施更进一步的 制程时，虚设栅极可保护鳍片结构的通道区，随后再以下面讨论的功能性栅 极取代虚设栅极。然而其他制程和组态也可能用于形成装置200。参见图10A和图10C的范例，形成虚设栅极结构1002。要注意的是，虚设栅极出现在 图10B包含的剖面示意图的平面外，图10B是提供鳍片结构212的源极/漏 极区的剖面示意图。虽然在一些实施方式中，虚设栅极(虚设栅极结构1002) 是显示为长度沿着X方向延伸的连续结构，然而虚设栅极1002可包含不只 一个栅极区段。
每一个虚设栅极结构1002可包含虚设介电层和虚设栅极电极。一些实施 例中，虚设栅极结构1002的形成可通过各种制程步骤，例如层的沉积、图 案化、蚀刻和其他合适的制程步骤。示范的层的沉积制程包含低压CVD、 CVD、等离子体辅助CVD(plasma-enhancedCVD；PECVD)、PVD、ALD、 加热氧化、电子束蒸镀或其他合适的沉积技术，或者前述的组合。图案化制 程可包含微影制程(例如光学微影或电子束微影)，微影制程可进一步包含光 阻涂布(例如旋转涂布)、软烤、遮罩对准、曝光、曝光后烘烤、光阻显影、 清洗、烘干(例如旋转烘干及/或硬烤)、其他合适的微影技术及/或前述的组合。 一些实施例中，蚀刻制程可包含干式蚀刻(例如RIE蚀刻)、湿式蚀刻及/或其 他蚀刻方法。一些实施例中，虚设介电层可包含氧化硅，且虚设电极层可包 含多晶硅(polysilicon)。虚设栅极结构1002可包含沿其侧壁沉积的一或多个 栅极间隙物。
方法100接着进行方框118，于此步骤中，将相邻于虚设栅极结构的鳍 片结构的源极/漏极区凹陷。蚀刻鳍片结构以形成沟槽或开口，其中源极/漏 极部件将形成于前述的沟槽或开口中，如下参见方框126所讨论的部分。参 见图10A和图10B范例，通过将鳍片结构212的源极/漏极区凹陷以形成沟 槽1004。沟槽1004分别标记为1004-1、1004-2、1004-3、1004-4和1004-5。 可通过干式蚀刻制程及/或其他合适的蚀刻制程来形成沟槽1004。举例而言， 干式蚀刻制程可实施含氧气体、氢、含氟气体(例如CF4、SF6、CH2F2、CHF3及/或C2F6)、含氯气体(例如Cl2、CHCl3、CCl4及/或BCl3)、含溴气体(例如 HBr及/或CHBR3)、含碘气体、其他合适的气体及/或等离子体，及/或前述 的组合。一些实施例中，在形成鳍片结构212的源极/漏极区的凹陷期间，同 时也从鳍片结构212的源极/漏极区移除包覆层402。沟槽1004暴露出凹陷 的鳍片结构212的顶面，以及隔离部件203的顶面的相邻区域。
图10C显示装置200的的布局俯视图的实施例。如图所示，虚设栅极结 构1002垂直延伸至主动区、鳍片结构212和导线702。
方法100接着进行方框120，于此步骤中在装置上形成遮罩元件。当在 上述方框112的步骤形成的导线上提供一或多个开口时，遮罩元件可用来保 护装置的区域。参见图11的范例，在装置200上形成遮罩元件1102，且遮 罩元件1102具有在导线702上的开口1104。遮罩元件1102的形成可通过合 适的光学微影制程。光学微影制程可包含在基底202上形成光阻层，将光阻 层对图案进行曝光，实施曝光后烘烤制程，以及对光阻层进行显影以形成包 含光阻层的遮罩元件1102。一些实施例中，遮罩元件包含硬遮罩材料。一些 实施例中，可使用电子束(e-beam)微影制程对光阻层进行图案化以形成遮罩 元件。开口1104可与鳍片212的主动区平行延伸。一些实施例中，开口1104 具有宽度(垂直于鳍片212延伸的方向，例如在图11的X方向上的宽度)，此 开口的宽度实质上等于隔离部件203在鳍片结构212之间延伸的宽度。
方法100接着进行方框122，于此步骤中移除相邻于导线的第一介电层。 一些实施例中，在方框120的遮罩元件中提供的开口内移除第一介电层。可 通过选择性蚀刻移除第一介电层，同时保留导线。一些实施例中，此蚀刻提 供SiN、SiCN的第一介电层对于导线的导线材料的选择性蚀刻。此蚀刻可采 用合适的氮化物蚀刻剂，例如碳-氟成分。此蚀刻可为湿式蚀刻、干式蚀刻及 /或其他合适的蚀刻制程。一些实施例中，此蚀刻为湿式蚀刻和干式蚀刻的组 合。参见图12A的范例，移除在遮罩元件1102的开口1104中的第一介电层 502。一些实施例中，保留在导线702正下方的介电层502。
举例而言，一些实施例中，在完成蚀刻制程之后，保留在导线702下方 的第一介电层502的剩余部分502’。这部分显示于图12B中。
方法100接着进行方框124，于此步骤中形成相邻于导线的导电衬层。 一些实施例中，导电衬层为硅化物层，例如TiSi。一些实施例中，导电衬层 可为其他的导电成分。参见图13A、图13B和图13C的范例，形成导电衬层 1304。一些实施例中，导电衬层1304可为TiSi。图13C提供接续图12B的 实施例和剩余部分502’。
方法100接着进行方框126，于此步骤中，在凹陷的鳍片结构上成长源 极和漏极部件。可在包含凹陷的鳍片结构顶面的晶种区域上外延成长源极/ 漏极部件。一些实施例中，外延制程可为气相外延(VPE)、超高真空 CVD(UHV-CVD)、分子束外延(MBE)及/或其他合适的制程。参见图13A和 图13B的范例，在相应的凹陷的鳍片结构212上分别形成标记为1302-1、 1302-2、1302-3、1302-4和1302-5的源极/漏极部件1302。可外延成长源极/ 漏极部件1302并对其适度地掺杂以提供相关的导电类型(N型或P型)。在各 种实施例中，成长源极/漏极部件1302的半导体材料层可包含Ge、Si、GaAs、 AlGaAs、SiGe、GaAsP、SiP、SiC及/或其他合适的材料。可通过一或多个 外延制程来形成源极/漏极部件1302。一些实施例中，可在外延制程期间对 源极/漏极部件1302进行原位(in-situ)掺杂。举例而言，一些实施例中，可对 外延成长的SiGe源极/漏极部件掺杂硼。一些例子中，可对外延成长的Si外 延源极/漏极部件掺杂碳以形成Si：C源极/漏极部件，掺杂磷以形成Si：P 源极/漏极部件，或者掺杂碳和磷两者以形成SiCP源极/漏极部件。一些实施 例中，并未对源极/漏极部件1302进行原位掺杂，取而代之的是，实施植入 制程以掺杂源极/漏极部件1302。一些实施例中，可在分开的制程系列中分 别形成N型和P型源极/漏极部件，以实施源极/漏极部件1302的形成。
在一实施例中，源极/漏极部件1302-2和1302-3为第一类型的装置(例如PFET)的源极/漏极部件。在进一步的实施例中，源极/漏极部件1302-1、1302-4 和1302-5为第二类型的装置(例如NFET)的源极/漏极部件。或者，其他组态 的装置类型也是可能的。由于某些源极/漏极部件1302与其他的源极/漏极部 件1302不同，它们可使用遮罩层以分别形成。
要注意在一些实施例中，相邻于通道区形成内间隙物。举例而言，使用 第10A图的范例，可稍微凹陷邻接沟槽1004的暴露的牺牲层206，并形成 内间隙物(例如介电材料，未绘示)。
一些实施例中，在方框126的步骤后至少实施部分的方框124。一些实 施例中，导电衬层为硅化物层，且通过源极/漏极部件1302的半导体材料与 相邻的导线702相互作用而形成。举例而言，一些实施例中，在源极/漏极部 件1302上沉积含钛层(或其他金属)。实施退火以提供硅钛化合物。
方法100接着进行方框128，于此步骤中移除虚设栅极，并露出通道层。 方法100接着进行方框128，于此步骤中移除虚设栅极，并在鳍片结构的通 道区内露出堆叠的通道层。虚设栅极的移除及/或通道层的露出可包含一或多 个蚀刻步骤。一些实施例中，选择性湿式蚀刻包含APM蚀刻(例如氢氧化铵 -过氧化氢-水的混合物)。一些实施例中，牺牲层206和包覆层402是由硅锗 形成，在包含对硅锗进行氧化的选择性移除后，接着移除硅锗氧化物。举例 而言，可通过臭氧清洗来实施前述的氧化，然后通过像是NH4OH的蚀刻剂 来移除硅锗氧化物。
方法100接着进行方框130，于此步骤中形成金属栅极结构。金属栅极 结构是形成在鳍片结构的通道区上。参见图14A和图14B的范例，在装置上 形成金属栅极结构1400。
参见图14A和图14B的范例，在鳍片结构212的通道区上形成取代虚设 栅极结构1002的金属栅极结构1400。
一些实施例中，金属栅极结构包含栅极介电层和形成在栅极介电层上的 栅极电极。一些实施例中，栅极介电层可包含界面层和高介电常数的介电层。 在此使用和描述的高介电常数的栅极介电质包含具有高介电常数的介电材 料，例如高于热氧化硅的介电常数(～3.9)。界面层可包含像是氧化硅、铪硅 酸盐或氮氧化硅的介电材料。界面层的沉积可使用化学氧化、加热氧化、原 子层沉积(atomic layer deposition；ALD)、化学气相沉积(chemical vapor deposition；CVD)及/或其他合适的方法。高介电常数的介电层可包含像是氧 化铪的高介电常数介电层。或者，高介电常数的介电层可包含其他高介电常 数的介电质，例如氧化铪(HfO)、氧化钛(TiO2)、氧化铪锆(HfZrO)、氧化钽 (Ta2O5)、氧化铪硅(HfSiO4)、氧化锆(ZrO2)、氧化锆硅(ZrSiO2)、氧化镧(La2O3)、 氧化铝(Al2O3)、氧化锆(ZrO)、氧化钇(Y2O3)、SrTiO3(STO)、BaTiO3(BTO)、 BaZrO、氧化铪镧(HfLaO)、氧化镧硅(LaSiO)、氧化铝硅(AlSiO)、氧化铪钽 (HfTaO)、氧化铪钛(HfTiO)、(Ba,Sr)TiO3(BST)、氮化硅(SiN)、氮氧化硅(SiON)、 前述的组合或其他合适的材料。可通过ALD、物理气相沉积(physical vapor deposition；PVD)、CVD、氧化及/或其他合适的方法来形成高介电常数的介 电层。
金属栅极结构1400的栅极电极可包含多层结构，例如具有选定功函数以 增加装置效能的金属层(功函数金属层)、衬层、润湿层、粘着层、金属合金 或金属硅化物的各种组合。举例来说，栅极电极可为氮化钛(TiN)、钛铝(TiAl)、 氮化钛铝(TiAlN)、氮化钽(TaN)、钽铝(TaAl)、氮化钽铝(TaAlN)、碳化铝钽 (TaAlC)、碳氮化钽(TaCN)、铝(Al)、钨(W)、镍(Ni)、钛(Ti)、钌(Ru)、钴(Co)、 铂(Pt)、碳化钽(TaC)、氮化硅钽(TaSiN)、铜(Cu)、其他耐火金属或其他合适 的金属材料，或者前述的组合。在各种实施例中，栅极结构的栅极电极的形 成可通过ALD、PVD、CVD、电子束蒸镀或其他合适的制程。在各种实施例 中，可实施平坦化制程，例如CMP制程，移除过量的材料以提供栅极结构 实质上平坦的顶面。某些金属栅极结构是耦接在一起。介电鳍片904可作为 相邻金属栅极结构之间的分离结构。这也显示在图15A的剖面示意图中。导 线702可例如通过介电层902与金属栅极结构1400绝缘。
一些实施例中，装置的虚设区中的栅极结构并非结果形成的IC(包含装置 200)中的功能性栅极结构，可形成与导线702相邻的栅极结构1400’。图15B 是关于某些栅极结构的说明，在这种情况下导线702可介于栅极之间且与栅 极电性耦接。图15C显示包含栅极结构1400’的虚设区1404的布局俯视图。 栅极结构1400’可与导线702接合。在一实施例中，将导孔1408形成至栅极 结构1400’以及导线702。一些实施例中，此处的导线702是提供电源线或电 源线的一部分的布线，例如Vss或Vdd。
图15B显示的配置具有从一个鳍片延伸至另一个鳍片的栅极结构1400’， 以及介于两个鳍片之间的导线702(即顶部区域耦接延伸至导线702上的栅极 结构)，导线702可提供在相同的鳍片212上源极/漏极区邻接导线(即鳍片 212-2和212-3，或者鳍片212-4和212-5)的地方或可为装置200的不同部分。
方法100接着进行方框132，于此步骤中进一步实施后续的制程。后续 的制程可例如包含沉积额外的接触蚀刻停止层(contact etch stop layer； CESL)，沉积额外的层间介电(interlayer dielectric；ILD)层和上覆的导电部件， 导电部件例如接触导孔和金属化线路。一些实施例中，由图15A和图15B 的介电层1406来显示中间的接触蚀刻停止层。接触蚀刻停止层可包含氮化 硅、氧化硅、氮氧化硅及/或其他本技术领域中已知的材料。接触蚀刻停止层 1406的沉积可使用ALD、等离子体辅助CVD(PECVD)及/或其他合适的沉积 或氧化制程。一些实施例中，可在与图15B的金属化物1410相邻的接触蚀 刻停止层上沉积层间介电层。一些实施例中，层间介电层包含的材料例如为 正硅酸四乙酯(tetraethylorthosilicate；TEOS)氧化物、未经掺杂的硅酸盐玻璃 或经掺杂的氧化硅，像是硼磷硅酸盐玻璃(borophosphosilicate glass；BPSG)、 熔融硅石玻璃(fused silicaglass；FSG)、磷硅酸盐玻璃(phosphosilicate glass； PSG)、掺硼硅玻璃(boron dopedsilicon glass；BSG)及/或其他合适的介电材料。 可在随后的制程中提供穿过介电层的接触部件，包含含有图15A和图15B 的接触导孔1408的接触部件。导孔1408互连至金属化物1410，金属化物 1410可称为M0。
注意在上述的方法100的实施例中，导线702是在源极/漏极部件之前形 成。或者在一些实施方式中，介电鳍片904是形成在每一个源极/漏极部件 1302之间，包含例如在源极/漏极部件1302-2与1302-3之间。在成长源极/ 漏极部件之后，形成遮罩元件以在设置于源极/漏极部件之间的某些介电鳍片 904上提供开口，例如在源极/漏极部件1302-2与1302-3之间的开口，以及 源极/漏极部件1302-4与源极/漏极部件1302-5上的开口。然后从这些区域移 除介电鳍片904，并在因介电鳍片904的移除而形成的开口中形成实质上与 导线702相似的导线702和导电衬层1304。一些实施方式中，结果形成的装 置实质上与第13A图相似，且方法由此继续。
一些实施例中，上述的导电层702提供IC或IC的一部分的信号或电源 线。除了在随后的权利要求中具体记载的内容的外，半导体装置200的确切 功能不限于现在描述的主题。然而，作为一个范例，在某些实施方式中，可 提供导线702于与SRAM装置相关的线路。举例而言，在一实施方式中，半 导体装置200包含SRAM，其可包含许多SRAM单元，例如图16所示的六 晶体管(6T)单端(SP)SRAM单元1600。参见图16，六晶体管单端SRAM单 元1600包含两个PMOSFET(例如上述的P型GAA晶体管或P型FinFET)， 作为上拉(pull-up)晶体管PU-1和PU-2；两个NMOSFET(例如上述的N型 GAA晶体管或N型FinFET)，作为下拉(pull-down)晶体管PD-1和PD-2；以 及两个NMOSFET(例如N型FinFET或N型GAA晶体管)，作为传送闸 (pass-gate)晶体管PG-1和PG-2。上拉晶体管PU-1与下拉晶体管PD-1耦接 以形成反向器(inverter)。上拉晶体管PU-2与下拉晶体管PD-2耦接以形成另 一反向器。这两个反向器跨越耦接在一起以形成储存单元。图16进一步显 示字元线(word line；WL)、位元线(bitline；BL)和反位元线(bit line bar，BLB)， 用以存取SRAM单元1600的储存单元。图中也显示电源线Vss和Vdd(Vcc)。 在一实施例中，形成分别包含鳍片212-4与212-5的主动区的下拉晶体管 PD-1与PD-2。在一实施例中，下拉晶体管PD-1与PD-2耦接至Vss，在一 些实施方式中例如像是导线702-2的导线702。在一实施例中，上拉晶体管 PU-1与PU-2分别包含鳍片212-2与212-3的主动区。在一实施例中，上拉 晶体管PU-1与PU-2耦接至Vcc/Vdd，在一些实施方式中例如像是导线 702-1。
上述形成金属化线路的实施例可用于Vcc或Vdd的连接。然而，如图16 所示，像是SRAM单元1600的装置具有额外的信号线。在某些设计中，其 他线路也可使用上述的方法和结构来形成，包含但不限于位元线。举例而言， 若信号线要与主动区(例如鳍片结构)平行延伸，则适合提供嵌入主动区之间 的金属化物，如本文所提供的。再者，SRAM的实施方式仅为例示，其他装 置类型也能适用。
在一示范态样中，本发明实施例是关于半导体装置。装置包含从基底延 伸的第一鳍片结构、第二鳍片结构和第三鳍片结构。第一源极/漏极部件是形 成在第一鳍片结构上。第二源极/漏极部件是形成在第二鳍片结构上。第三源 极/漏极部件是形成在第三鳍片结构上。介电分离结构在第一源极/漏极部件 与第二源极/漏极部件之间延伸。导线是设置在第二源极/漏极部件与第三源 极/漏极部件之间。
在进一步的实施例中，在第一鳍片结构与第二鳍片结构之间提供第一浅 沟槽隔离(shallow trench isolation；STI)部件。第二浅沟槽隔离部件在第二鳍 片结构与第三鳍片结构之间延伸。在一实施例中，介电分离结构是设置在第 一浅沟槽隔离部件上。在一实施例中，导线是设置在第二浅沟槽隔离部件上。 一些实施方式中，第一源极/漏极部件为第一导电类型，且第二源极/漏极部 件和第三源极/漏极部件为第二导电类型。
在一实施例中，导线分别与第一鳍片结构、第二鳍片结构和第三鳍片结 构平行延伸。一些实施方式中，导线包含导电衬层。导电衬层可为硅化物成 分。在一实施例中，在第一鳍片结构、第二鳍片结构和第三鳍片结构中的至 少两者上形成金属栅极结构，金属栅极结构可延伸至导线上。
在另一较广的实施例中，半导体装置包含具有第一晶体管和第二晶体管 的存储器单元。第一晶体管的第一源极/漏极部件是形成在凹陷的第一鳍片结 构上。第二晶体管的第二源极/漏极部件是形成在凹陷的第二鳍片结构上。电 源线是设置在第一源极/漏极部件与第二源极/漏极部件之间。
一些实施方式中，第一源极/漏极部件和第二源极/漏极部件分别包含外延 成长的硅。在一实施例中，第一晶体管和第二晶体管为相同的导电类型(例如 N型或P型)。在一实施例中，电源线传送Vcc。在一实施例中，电源线传送 Vss。一些实施方式中，装置更包含虚设区，具有第一虚设栅极和连接至第 一虚设栅极的第二虚设栅极，以及另一电源线，设置在第一虚设栅极与第二 虚设栅极之间。
在此处讨论的另一实施例中提供方法。方法包含提供设置在基底上的第 一鳍片结构、第二鳍片结构和第三鳍片结构。在第一鳍片结构与第二鳍片结 构之间形成介电鳍片。在第二鳍片结构与第三鳍片结构之间形成导线。方法 包含形成延伸至第二鳍片结构、导线和第三鳍片结构上的栅极结构。将第一 鳍片结构、第二鳍片结构和第三鳍片结构各自的源极/漏极区凹陷。分别在第 一鳍片结构、第二鳍片结构和第三鳍片结构上外延成长第一源极/漏极部件、 第二源极/漏极部件和第三源极/漏极部件。
在进一步的实施例中，在方法的外延成长部分之后，移除栅极结构并形 成金属栅极结构。在一实施例中，形成介电鳍片包含：沉积第一介电层；沉 积第二介电层；回蚀刻第二介电层的一部分；以及在第一介电层和第二介电 层上沉积高介电常数的介电层。
一些实施例中，方法更包含在第一鳍片结构与第二鳍片结构之间，且在 第二鳍片结构与第三鳍片结构之间形成多个浅沟槽隔离(STI)部件。介电鳍片 可形成在这些浅沟槽隔离部件的其中一者上，且导线是形成在这些浅沟槽隔 离部件的另一者上。一些实施方式中，方法包含在形成栅极结构之后，在导 线与外延成长的第二源极/漏极部件上形成硅化物层。
前述内文概述了许多实施例的部件，以使本技术领域中具有通常知识者 可以更佳地了解本发明实施例的各种态样。本技术领域中具有通常知识者应 可理解他们可使用本发明实施例为基础来设计或修改其他制程及结构，以达 到相同的目的及/或达到与在此介绍的实施例相同的优点。本技术领域中具有 通常知识者也应了解这些相等的架构并未背离本发明实施例的精神与范围。 而在不背离本发明实施例的精神与范围的前提下，他们可对本文进行各种改 变、替换或变更。

Claims (1)

1.一种半导体装置，包括：
一第一鳍片结构、一第二鳍片结构和一第三鳍片结构，从一基底延伸；
一第一源极/漏极部件，在该第一鳍片结构上；
一第二源极/漏极部件，在该第二鳍片结构上；
一第三源极/漏极部件，在该第三鳍片结构上；
一介电分离结构，在该第一源极/漏极部件与该第二源极/漏极部件之间延伸；以及
一导线，在该第二源极/漏极部件与该第三源极/漏极部件之间。
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