CN113140445A - Cleaning method after back-end etching - Google Patents
Cleaning method after back-end etching Download PDFInfo
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- CN113140445A CN113140445A CN202110292312.4A CN202110292312A CN113140445A CN 113140445 A CN113140445 A CN 113140445A CN 202110292312 A CN202110292312 A CN 202110292312A CN 113140445 A CN113140445 A CN 113140445A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02082—Cleaning product to be cleaned
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
- H01L2221/1015—Forming openings in dielectrics for dual damascene structures
Abstract
The invention discloses a cleaning method after back-end etching, which comprises the following steps: step one, providing a wafer, finishing back-end etching on a first surface of the wafer, wherein the back surface of the first surface is a second surface; step two, pre-cleaning the first surface and the second surface of the wafer, wherein the pre-cleaning is static electricity removing cleaning to remove static electricity on the first surface and the second surface of the wafer; and step three, carrying out main cleaning on the first surface of the wafer by adopting a uDHF solution so as to remove etching residues of the back-stage etching. The invention can effectively remove the residue after the back-end etching, and particularly has no polymer residue.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a back end of line (BEOL) post-etch cleaning method.
Background
The back-end process is used for forming a metal interconnection structure, the metal interconnection structure comprises metal lines and through holes positioned between the metal lines of each upper adjacent layer and the metal lines of each lower adjacent layer, and the through holes need to penetrate through the interlayer film, so that the interlayer film needs to be etched to form openings of the through holes. In a copper interconnection structure, a damascene process, including single damascene and dual damascene, is required, and the dual damascene process integrally etches an opening of a through hole and a groove of a metal line (all in one). The etching process in the back-end process is back-end etching, and etching residues are often generated on the wafer after the back-end etching, so that the etching residues need to be removed by adopting a cleaning process.
An existing cleaning method for the post-etching of the back section adopts EKC cleaning, EKC cleaning needs an EKC cleaning solution, but the EKC cleaning can reduce the yield of products.
In the existing improved cleaning method after back-end etching, a uDHF solution is adopted for cleaning, and the uDHF solution is a mixed solution of DHF and H2SO 4. The uDHF solution cleaning can effectively remove Ti, SiO2 and Cu by-products (bi-products) without loss of wafer materials.
As shown in fig. 1A, it is a structure diagram of an integrated etched device of a damascene process in the existing back-end etching process; as shown in fig. 1B, is a device structure diagram after cleaning the structure shown in fig. 1A by using the existing post-etching cleaning method; FIG. 2 is a schematic diagram of a conventional post-etch cleaning method; as shown in fig. 1A, copper lines and vias are formed using a damascene process; when the damascene process is a dual damascene process, the opening 104 of the through hole and the trench 105 of the copper wire are formed by integrated etching. The back-end etching is the integrated etching.
The bottom of the opening 104 of the through hole exposes the surface of the copper wire 101 at the bottom layer, and the top of the opening 104 of the through hole is communicated with the groove 105 of the copper wire.
The opening 104 of the via hole and the trench 105 of the copper wire pass through the interlayer film 102.
The material of the interlayer film 102 includes a low-K dielectric layer.
And a copper diffusion barrier layer is also isolated between the low-K dielectric layer and the bottom copper wire 101. Preferably, the copper diffusion barrier layer is a nitrogen-doped silicon carbide (NDC) layer.
A metal hard mask layer 103 is further formed on the surface of the interlayer film 102, and the metal hard mask layer 103 defines a formation region of the trench 105 of the copper wire. The metal hard mask layer 103 is made of TiN.
As shown in fig. 1A, after the post-etching, which is exemplified by the integral etching, is completed, etching residues 106a are formed on the side surfaces of the opening 104 of the through hole and the trench 105 of the copper wire, and etching residues 106b are formed on the bottom surface of the opening 104 of the through hole, and are etchedThe etching residue comprises Ti, SiO2And Cu formation by-products; the residue 106b is CuO.
As shown in fig. 2, in the conventional method, after the back-end etching, the surface of the wafer 108 is directly cleaned by using a DHF solution, SO as to remove etching residues of the back-end etching, where the DHF solution is a mixed solution of DHF and H2SO 4. In the uDHF solution, the solubility of HF of DHF is 10 ppm-50 ppm; the solubility of H2SO4 is 1% -10%.
In the cleaning, the uDHF is sprayed to the surface of the wafer 108 by using a nozzle. In fig. 2, reference numeral 109 denotes the DICO to be injected2。
As shown in fig. 1B, the dotted circles 107a and 107B are schematic diagrams after cleaning the etching residues 106a and 106B, respectively. Wherein, the etching residue 106b is CuO, and the chemical reaction process of the dhf for removing CuO is shown as the following chemical reaction formula:
CuO+H2SO4→CuO(s)+2H+→Cu2+ (ag)+H2O。
compared with EKC cleaning, uDHF solution cleaning can improve the product yield. However, as shown in fig. 3A, it is a residual test chart on the wafer after being cleaned by the conventional post-etching cleaning method shown in fig. 2; the conventional uDHF solution cleaning method shown in FIG. 2 is prone to have residues in the center of the wafer, which is marked by the mark 108a alone in FIG. 3A, and the residues in the center of the wafer 108a are marked by the mark 110a alone; also illustrated in fig. 2 is a residue 110 that appears in the center of the wafer 108.
Further analysis revealed that the residue 110a was a polymer (polymer), and as shown in FIG. 3B, it is a photograph of the residue obtained from the test in FIG. 3A; the residue is indicated by reference numeral 110b alone.
Disclosure of Invention
The invention aims to provide a cleaning method after back-end etching, which can effectively remove residues after back-end etching, in particular polymer residues which are difficult to remove.
In order to solve the technical problem, the cleaning method after the back-end etching provided by the invention comprises the following steps:
step one, providing a wafer, wherein the back-end etching is finished on the first surface of the wafer, and the back surface of the first surface is the second surface.
And secondly, pre-cleaning the first surface and the second surface of the wafer, wherein the pre-cleaning is static electricity removing cleaning to remove static electricity on the first surface and the second surface of the wafer.
And step three, carrying out main cleaning on the first surface of the wafer by adopting a uDHF solution to remove etching residues of the back-stage etching, wherein the uDHF solution is a mixed solution of DHF and H2SO 4.
In a further improvement, the cleaning solution for removing the pre-cleaning adopts DICO2Said DICO2Deionized water mixed with carbon dioxide.
The further improvement is that in the uDHF solution, the solubility of HF of DHF is 10 ppm-50 ppm; the solubility of H2SO4 is 1% -10%.
In a further refinement, the wafer comprises a silicon wafer.
In a further improvement, in the step one, the back-end etching includes opening etching of a through hole.
The further improvement is that a copper interconnection structure is adopted in the back-end process of the wafer, the copper interconnection structure comprises a plurality of layers of copper wires and through holes are arranged among the copper wires, and the back-end etching also comprises the groove etching of the copper wires.
The further improvement is that the copper wire and the through hole are formed by adopting a Damascus process; the Damascus process comprises a single Damascus process and a dual Damascus process.
When a dual damascene process is adopted, the opening of the through hole and the groove of the copper wire are formed by integrated etching, and the back-end etching in the step one is the integrated etching;
the first surface of the wafer is the front surface of the wafer.
In a further improvement, the bottom of the opening of the through hole exposes the surface of the copper wire on the bottom layer, and the top of the opening of the through hole is communicated with the groove of the copper wire.
In a further refinement, the opening of the via and the trench of the copper line pass through an interlayer film.
In a further refinement, the material of the interlayer film comprises a low-K dielectric layer.
In a further improvement, a copper diffusion barrier layer is isolated between the low-K dielectric layer and the bottom copper wire.
In a further improvement, the copper diffusion barrier layer is a nitrogen-doped silicon carbide layer.
In a further improvement, a metal hard mask layer is further formed on the surface of the interlayer film, and the metal hard mask layer defines a formation region of the trench of the copper wire.
In a further improvement, the metal hard mask layer is made of TiN.
In a further improvement, in the third step, a nozzle is adopted to spray the uDHF to the first surface of the wafer in the main cleaning.
In a further improvement, in the third step, the dhf is sprayed to the first surface of the wafer in a scanning manner from the edge of the wafer in the main cleaning.
In a further improvement, in step two, the DICO is pre-cleaned by using a nozzle2And spraying the first surface and the second surface of the wafer.
According to the invention, after the back-end etching is finished and before the wafer is subjected to main cleaning by adopting the uDHF solution, the pre-cleaning for removing static electricity on the first surface and the second surface, namely the front surface and the back surface of the wafer is added, so that residues after the back-end etching can be effectively removed after the main cleaning is finished, particularly polymer residues which are difficult to remove can be removed, for example, the polymer residues in the center of the wafer can be prevented, and finally, the performance and the yield of the product can be improved.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1A is a diagram of a structure of an integrated etched device of a damascene process in a conventional back-end etching process;
FIG. 1B is a diagram of a device structure after cleaning the structure shown in FIG. 1A by a conventional post-etch cleaning method;
FIG. 2 is a schematic diagram of a conventional post-etch cleaning method during cleaning;
FIG. 3A is a graph of a test of residue on a wafer after being cleaned using the prior art post etch cleaning method shown in FIG. 2;
FIG. 3B is a photograph of the residue from the test of FIG. 3A;
FIG. 4 is a flow chart of a method for post etch cleaning in accordance with an embodiment of the present invention;
FIG. 5A is a schematic diagram of a post-etch cleaning method for pre-cleaning in accordance with an embodiment of the present invention;
FIG. 5B is a schematic diagram of a post-etch cleaning method for performing a main cleaning in accordance with an embodiment of the present invention;
FIG. 6 is a graph illustrating the testing of the residue on the wafer after the post-etch cleaning method according to the embodiment of the present invention.
Detailed Description
FIG. 4 is a flow chart of a post-etch cleaning method according to an embodiment of the present invention; FIG. 5A is a schematic diagram illustrating a pre-cleaning process performed by the post-etch cleaning method according to an embodiment of the present invention; FIG. 5B is a schematic diagram illustrating a main cleaning process performed by the post-etch cleaning method according to an embodiment of the present invention; the cleaning method after the back-end etching of the embodiment of the invention comprises the following steps:
step one, providing a wafer 201, wherein the back-end etching is completed on a first surface of the wafer 201, and the back surface of the first surface is a second surface.
In the embodiment of the present invention, the wafer 201 includes a silicon wafer 201.
The back-end etch includes an opening 104 etch of a via.
A copper interconnection structure is adopted in the back-end process of the wafer 201, the copper interconnection structure comprises a plurality of layers of copper wires and through holes are formed among the copper wires, and the back-end etching further comprises etching of grooves 105 of the copper wires.
The copper wire and the through hole are formed by adopting a Damascus process, and the Damascus process comprises a single Damascus process and a dual Damascus process. When a dual damascene process is adopted, the opening of the through hole and the groove of the copper wire are formed by integrated etching, and the back-end etching in the step one is the integrated etching;
the first surface of the wafer is the front surface of the wafer.
The opening 104 of the through hole and the groove 105 of the copper wire are formed by integrated etching, and the back-end etching in the first step is the integrated etching. The integrated etching is also shown with reference to fig. 1A.
The first surface of the wafer 201 is a front surface of the wafer 201.
The bottom of the opening 104 of the through hole exposes the surface of the copper wire 101 at the bottom layer, and the top of the opening 104 of the through hole is communicated with the groove 105 of the copper wire.
The opening 104 of the via hole and the trench 105 of the copper wire pass through the interlayer film 102.
The material of the interlayer film 102 includes a low-K dielectric layer.
And a copper diffusion barrier layer is also isolated between the low-K dielectric layer and the bottom copper wire 101. Preferably, the copper diffusion barrier layer is a nitrogen-doped silicon carbide layer.
A metal hard mask layer 103 is further formed on the surface of the interlayer film 102, and the metal hard mask layer 103 defines a formation region of the trench 105 of the copper wire. The metal hard mask layer 103 is made of TiN.
As shown in fig. 1A, after the post-etching, which is exemplified by the integration etching, is completed, etching residues 106a are formed on the side surfaces of the opening 104 of the through hole and the trench 105 of the copper wire, and etching residues 106b are formed on the bottom surface of the opening 104 of the through hole, where the etching residues include Ti and SiO2And Cu formation by-products; residue 106b is CuO。
Step two, as shown in fig. 5A, performing a pre-cleaning on the first surface and the second surface of the wafer 201, where the pre-cleaning is a static electricity removing cleaning to remove static electricity from the first surface and the second surface of the wafer 201, and the static electricity is shown as + in fig. 5A.
In the embodiment of the invention, the cleaning liquid for pre-cleaning adopts DICO2Said DICO2Deionized water mixed with carbon dioxide.
The pre-cleaning employs nozzles to pre-clean the DICO2To the first and second surfaces of the wafer 201. In fig. 5A, reference numeral 202 denotes the DICO injected2。
Step three, as shown in fig. 5B, performing main cleaning on the first surface of the wafer 201 by using a DHF solution to remove the etching residues of the post-stage etching, where the DHF solution is a mixed solution of DHF and H2SO 4.
In the embodiment of the invention, in the uDHF solution, the solubility of HF of DHF is 10 ppm-50 ppm; the solubility of H2SO4 is 1% -10%.
In the main cleaning, the uDHF is sprayed to the first surface of the wafer 201 by using a nozzle. Preferably, in the main cleaning, the dhf is sprayed to the first surface of the wafer 201 by scanning from the edge of the wafer 201. In fig. 5B, reference numeral 203 denotes the DICO to be injected2。
The main cleaning process is also shown in fig. 1B, and the dotted circles 107a and 107B are schematic diagrams of the main cleaning process after the main cleaning process is performed on the etching residues 106a and 106B, respectively.
As shown in fig. 6, which is a residual test chart of the wafer 201a after the post-etching cleaning method according to the embodiment of the present invention is completed, it can be seen that no etching residue, especially no polymer residue, is left on the surface of the wafer 201 a.
According to the embodiment of the invention, after the back-end etching is finished and before the wafer 201 is subjected to main cleaning by adopting the uDHF solution, the pre-cleaning for removing static electricity on the first surface and the second surface, namely the front surface and the back surface of the wafer 201 is added, so that residues after the back-end etching can be effectively removed after the main cleaning is finished, particularly polymer-free residues which are difficult to remove can be removed, for example, the embodiment of the invention can prevent the polymer residues from appearing in the center of the wafer, and finally, the invention can improve the performance and yield of products.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (17)
1. A cleaning method after back-end etching is characterized by comprising the following steps:
step one, providing a wafer, wherein the back-end etching is finished on a first surface of the wafer, and the back surface of the first surface is a second surface;
secondly, pre-cleaning the first surface and the second surface of the wafer, wherein the pre-cleaning is static electricity removing cleaning to remove static electricity on the first surface and the second surface of the wafer;
and step three, carrying out main cleaning on the first surface of the wafer by adopting a uDHF solution to remove etching residues of the back-stage etching, wherein the uDHF solution is a mixed solution of DHF and H2SO 4.
2. The post-etch cleaning method of claim 1, wherein: the cleaning solution for removing the pre-cleaning adopts DICO2Said DICO2Deionized water mixed with carbon dioxide.
3. The post-etch cleaning method of claim 1, wherein: in the uDHF solution, the solubility of HF of DHF is 10 ppm-50 ppm; the solubility of H2SO4 is 1% -10%.
4. The post-etch cleaning method of claim 1, wherein: the wafer comprises a silicon wafer.
5. The back end post etch cleaning method of claim 4, wherein: in the first step, the back-end etching includes opening etching of a through hole.
6. The back end post etch cleaning method of claim 5, wherein: the back end technology of the wafer adopts a copper interconnection structure, the copper interconnection structure comprises a plurality of layers of copper wires and through holes are formed among the copper wires, and the back end etching further comprises groove etching of the copper wires.
7. The back end post etch cleaning method of claim 6, wherein: the copper wire and the through hole are formed by adopting a Damascus process; the Damascus process comprises a single Damascus process and a dual Damascus process;
when a dual damascene process is adopted, the opening of the through hole and the groove of the copper wire are formed by integrated etching, and the back-end etching in the step one is the integrated etching;
the first surface of the wafer is the front surface of the wafer.
8. The back end post etch cleaning method of claim 7, wherein: the bottom of the opening of the through hole exposes the surface of the bottom copper wire, and the top of the opening of the through hole is communicated with the groove of the copper wire.
9. The back end post etch cleaning method of claim 8, wherein: the opening of the via and the trench of the copper line pass through an interlayer film.
10. The back end post etch cleaning method of claim 9, wherein: the material of the interlayer film comprises a low-K dielectric layer.
11. The back end post etch cleaning method of claim 10, wherein: and a copper diffusion barrier layer is isolated between the low-K dielectric layer and the bottom copper wire.
12. The back end post etch cleaning method of claim 11, wherein: the copper diffusion impervious layer adopts a nitrogen-doped silicon carbide layer.
13. The back end post etch cleaning method of claim 10, wherein: and a metal hard mask layer is also formed on the surface of the interlayer film, and defines a forming area of the groove of the copper wire.
14. The back end post etch cleaning method of claim 13, wherein: the metal hard mask layer is made of TiN.
15. The post-etch cleaning method of claim 1, wherein: and in the third step, spraying the uDHF to the first surface of the wafer by adopting a nozzle in the main cleaning.
16. The post-etch cleaning method of claim 1, wherein: in the third step, the uDHF is sprayed to the first surface of the wafer in a scanning manner from the edge of the wafer in the main cleaning.
17. The back end post etch cleaning method of claim 2, wherein: in step two, the DICO is pre-cleaned by using a nozzle2And spraying the first surface and the second surface of the wafer.
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| CN109722351A (en) * | 2018-12-29 | 2019-05-07 | 上海华力集成电路制造有限公司 | Back segment cleaning process chemical mixing solution and the back segment cleaning process for applying it |
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