KR100657760B1 - Fabricating method of metal line in semiconductor device - Google Patents

Abstract

A method for forming a metal line of a semiconductor device is provided to improve quality of the semiconductor device by minimizing the damage of a low-k dielectric film using an ashing process and an organic cleaning process. An etch stop layer and an interlayer dielectric made of a low-k material are formed on a substrate. A buffer layer(16) is formed on the interlayer dielectric. A via hole is formed on the resultant structure by etching selectively the buffer layer and the interlayer dielectric until the etch stop layer is exposed to the outside. An ashing process is performed on the resultant structure by using H2O. An organic cleaning process is then performed thereon. A metal line(18) for filling the via hole is formed on the resultant structure.

Description

Fabrication method of metal line in semiconductor device

1 is a cross-sectional view showing metal wiring of a semiconductor device according to the present invention.

2 is a cross-sectional view at an intermediate step of forming metal wirings of a semiconductor device according to the present invention.

3 is a SEM photograph of the pad and the edge of the via chain after via formation.

4 is a TEM photograph when washed with HF diluted to 100: 1 according to the prior art.

5 is a TEM photograph of the case of cleaning with NE14 according to the present invention.

6A is a FTIR spectrum result after O ₂ ashing post-cleaning according to the prior art.

6B is a FTIR spectrum result after O ₂ + CO ashing post-cleaning according to the prior art.

Figure 6c is the result of the FTIR spectrum after cleaning after H ₂ O ashing according to the present invention.

7A is a SIMS depth profile along the depth direction of carbon atoms.

7B is a SIMS depth profile along the depth direction of the oxygen atom.

8 is a cross-sectional view in an intermediate step of forming a metal wiring of a semiconductor device according to the present invention.

9A is an optical photograph of a substrate when no plasma treatment is performed according to the prior art.

9B is an optical photograph of the substrate when the plasma treatment according to the present invention is performed.

TECHNICAL FIELD This invention relates to the metal wiring formation method of a semiconductor device. Specifically, It is related with the semiconductor device containing a copper wiring.

Conventionally, aluminum wiring is mainly used due to low contact resistance and ease of process progress, but the width of metal wiring is narrowed due to miniaturization and high integration of semiconductor devices, resulting in signal delay due to resistance and capacitance of metal wiring. do. Therefore, copper wiring with lower resistance than aluminum wiring is used.

On the other hand, the insulating film between metal wirings also uses a low dielectric constant film to reduce signal delay and the like. However, ammonia generated during the process reacts with the photoresist to cause photoresist poisoning (PR poisoning) that is not patterned, and carbon depletion of the low dielectric constant film occurs after ashing to remove the photoresist. Due to these phenomena, the photoresist pattern is not properly formed, so that the low dielectric constant film is not properly etched, and the dielectric constant of the low dielectric constant film is also increased.

Accordingly, an aspect of the present invention is to provide a method for forming metal wirings in a semiconductor device in which photoresist pattern poisoning and carbon depletion do not occur when a semiconductor device including an interlayer insulating film made of a low dielectric constant material is manufactured.

A method of manufacturing a semiconductor device according to the present invention for achieving the above object is to form an interlayer insulating film with an etch stop film and a low dielectric constant material on the substrate, to form a buffer film on the interlayer insulating film, until the etch stop film is exposed Etching the buffer film and the interlayer insulating film to form a via, ashing with H ₂ O to remove the photosensitive film, organic cleaning the substrate, and forming a metal wiring to form the via on the substrate. Include.

The method may further include plasma treating the substrate with He after forming the interlayer insulating film.

The method may further include forming a trench that exposes the via, wherein the trench may include etching using a photoresist film, ashing H ₂ O to remove the photoresist film, and organic cleaning the substrate.

The organic cleaning can be wet cleaning with a fluorine series or an amine series.

The buffer film may be USG formed of TEOS as a source gas.

The change in the thickness ratio of the interlayer insulating film after ashing may be Δ35.4, and the change in the refractive index of the interlayer insulating film after ashing may be Δ0.009.

The thickness change of the interlayer insulating film after the organic cleaning may be Δ74.9, and the change of the refractive index of the interlayer insulating film after the organic cleaning may be Δ0.008.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A copper wiring of a semiconductor device and a method of manufacturing the same will now be described with reference to the accompanying drawings.

1 is a cross-sectional view showing metal wiring of a semiconductor device according to the present invention.

As shown in FIG. 1, an etch stop film 12 is formed on the substrate 10, and an interlayer insulating film 14 is formed on the etch stop film 12. The substrate 10 may include individual elements (not shown) or metal conductors (not shown). The etch stop film 12 is made of SiCN or the like, and the interlayer insulating film 14 is made of a low dielectric constant material having a dielectric constant of 3.1 or less.

The buffer film 16 is formed on the interlayer insulating film 14.

Vias V are formed in the interlayer insulating layer 14 and the etch stop layer 12 to expose lower conductors or individual elements, and vias V are exposed in the interlayer insulating layer 14 and the buffer layer 16. Trench T is formed.

In the exposed vias V and the trenches T, metal wirings 18 are formed. The metal wiring 18 includes a diffusion barrier film 18a formed along the inner walls of the vias V and the trench T, and a metal layer 18b filling the vias and trenches defined by the diffusion barrier film. The diffusion barrier 18a is formed in a double structure of tantalum nitride (TaN) / tantalum (Ta). The metal layer 18b is made of a conductive material such as copper (Cu), which is a low resistance metal.

A method of forming the metal wiring of the semiconductor device will be described with reference to FIGS. 2 to 9B and FIG. 1 described above.

2 and 8 are cross-sectional views in an intermediate step of forming metal wirings of a semiconductor device according to the present invention.

As shown in FIG. 2, an etch stop film 12 and an interlayer insulating film 14 are formed on the substrate 10. The etch stop layer 12 may be formed of SiCN, and the interlayer insulating layer 14 may be formed of black diamond having a dielectric constant of 2.95 as a low dielectric constant material.

Subsequently, the He plasma treatment is performed on the substrate, and the buffer layer 16 is formed of USG (un-doped silicate glass) on the interlayer insulating layer 14. In this case, the buffer membrane 16 uses a tetraethylorthosilicate (TEOS) gas as a source gas so that nitrogen is not included in the membrane. Since nitrogen is not included in the buffer film 16, the interlayer insulating film 14 is not contaminated by nitrogen.

Next, after the photoresist is formed on the buffer layer 16, the buffer layer 16 and the interlayer insulating layer 14 are etched until the etch stop layer 12 is exposed to form vias V, and the H ₂ O gas ( Or steam) to remove the photosensitive film.

In this case, since the interlayer insulating layer 14 is not contaminated by nitrogen or the like, the photoresist poisoning phenomenon does not occur, and thus, the via V having the correct size may be formed.

FIG. 3 is an SEM photograph of the edge of the pad and via chain after via formation. As shown in FIG. 3, it can be seen that vias V having a clean and uniform size are formed without leaving a photosensitive film on top of the vias.

Table 1 is a table showing the thickness change and the refractive index change of the interlayer insulating film according to each case of ashing with conventional O ₂ , O ₂ + CO and H ₂ O of the present invention.

Table 1

Looking at Table 1, the change in thickness ratio is Δ50.5 for O ₂ , Δ 105.7 for O ₂ + CO, and Δ35.4 for H ₂ O, which is thicker than for O ₂ and O ₂ + CO. You can see that there is much less change.

And the refractive index gradient Δ0.011 case of O _2, O ₂ + CO In the case of it can be seen that greater than Δ0.009 of the present invention to Δ0.019. This indicates that the ashing according to the present invention causes less damage to the interlayer insulating film than ashing with conventional oxygen or O ₂ + CO ₂ gas.

On the other hand, O ₂ or CO according to the prior art increases the dielectric constant of the interlayer insulating film so that the characteristics of the low dielectric constant film does not appear properly. This is because oxygen contained in O ₂ or CO easily falls off, and the released oxygen is easily substituted with carbon included in the low dielectric constant film to deplete the carbon of the interlayer insulating film 14 and increase the dielectric constant. However, using the H ₂ O gas as in the present invention, it is possible to prevent the dielectric constant from increasing because oxygen is not easily released.

Next, impurities and the like on the substrate 10 are removed by washing. At this time, the cleaning is wet cleaning using a fluorine-based or amine-based organic material. Such organic cleaners include NE14 from Ashland, EcoPeeler KF3000 series from KISHIMOTO, ST-250 / ST-255 from ATMI, ACT from Air products, and EKC652 / EKC5800 from advanced semi aqueous chemistry.

4 is a case of washing with HF diluted to 100: 1 according to the prior art, and FIG. 5 is a TEM photograph of each case of washing with NE14 in the organic detergent according to the present invention.

Referring to FIG. 4, the sidewalls of the vias are damaged, but in FIG. 5, the damaged portions of the sidewalls of the vias cannot be found. Therefore, it can be seen that the cleaning according to the present invention causes less damage to the vias as compared to the prior art.

This can also be confirmed through the thickness change and the refractive index change of the interlayer insulating film shown in Table 2.

Table 2 shows the thickness change and the refractive index change of the interlayer insulating film according to each case using post-O ₂ ashing cleaning, O ₂ + CO ashing cleaning, and H ₂ O ashing cleaning according to the present invention. to be.

[Table 2]

Looking at Table 2, the change in thickness ratio is Δ112.7 for O ₂ , Δ 150.5 for O ₂ + CO, and Δ74.9 for H ₂ O, which is thicker than conventional O ₂ and O ₂ + CO. You can see that there is much less change.

In addition, the refractive index change of the present invention is Δ0.008, which is similar to Δ0.008 of O _{2 in} the prior art, but is much smaller than Δ0.020 in the case of O ₂ and O ₂ + CO in the prior art.

It can be seen from this that the ashing and cleaning according to the present invention causes less damage to the interlayer insulating film than the ashing and cleaning according to the prior art.

In addition, this effect can also be confirmed through FIGS. 6A to 6C. FIG. 6A is a FTIR (Fourier Transform Infrared Spectrometer) spectrum result after O ₂ ashing and cleaning according to the prior art, and FIG. 6B is a FTIR spectrum result after O ₂ + CO ashing and cleaning according to the prior art, and FIG. 6C. Is the FTIR spectrum result after performing the post-H ₂ O ashing cleaning according to the present invention.

6A and 6B, new peaks are seen after ashing and cleaning. However, no new peak is observed in FIG. 6C. It appears that oxygen of O ₂ or CO penetrates not only into the surface but also into the interlayer insulating film and bonds with the carbon of the interlayer insulating film to change properties and cause a change in dielectric constant. However, in the present invention, since no new peak is observed, the dielectric constant does not change because there is no change in the interlayer insulating film.

This can be more clearly seen by examining the change in the amount of carbon and oxygen in the depth direction of FIGS. 7A and 7B. FIG. 7A is a secondary ion mass spectrometry (SIMS) depth profile in a depth direction of a carbon atom, and FIG. 7B is a SIMS depth profile in a depth direction of an oxygen atom.

7A and 7B, it can be seen that in each case of ashing with the prior art O ₂ , O ₂ + CO and the present invention H ₂ O, the carbon on the surface decreases rapidly. However, the oxygen content does not increase rapidly. In the case of cleaning after O ₂ and CO + O ₂ ashing, carbon was further reduced and oxygen content was increased. However, when ashing and cleaning were performed with H ₂ O of the present invention, the original carbon and oxygen contained in the interlayer insulating film It shows almost the same profile. From this, it can be seen that ashing and cleaning according to the present invention minimize damage to the interlayer insulating film.

Next, as shown in FIG. 8, after forming the photoresist film exposing the vias V on the buffer film 16, the buffer film 16, a part of the interlayer insulating film 14, and the etch stop film 12 are removed. A trench T exposing the vias V is formed. And ashed with H ₂ O and organic washed. In this case, the cleaning is wet cleaning using a fluorine-based or amine-based organic material, as described above.

The metal is deposited on the inner walls of the vias V and the trenches T to form a thin first metal film 18a. A second metal film 18b is then formed to fill the vias and trenches defined by the first metal film 18a. The second metal film 18b uses copper, which is a low resistance metal.

As shown in FIG. 1, the metal lines 18 filling the vias V and the trenches T are formed by chemical mechanical polishing until the upper surface of the buffer layer 16 is exposed.

At this time, in the embodiment of the present invention, since He plasma treatment is performed before the buffer film 16 is formed, delamination is reduced during polishing.

9A is an optical photograph of a substrate when no plasma treatment is performed according to the prior art, and FIG. 9B is an optical photograph of a substrate when the plasma treatment according to the present invention is performed.

As shown in FIGS. 9A and 9B, in both cases, the substrate was cracked. However, in the case of the present invention it can be seen that the splitting range does not spread as widely as in the prior art.

As described above, when the semiconductor device is formed by ashing and cleaning according to the present invention, damage to the low dielectric constant film can be minimized, thereby providing a high quality semiconductor device.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (7)

Forming an interlayer insulating film on the substrate with an etch stop film and a low dielectric constant material, Forming a buffer film on the interlayer insulating film, Etching the buffer layer and the interlayer insulating layer until the etch stop layer is exposed to form vias; Ashing with H ₂ O to remove the photoresist, Organic cleaning the substrate, and Forming a metal interconnection filling the via on the substrate Metal wiring forming method of a semiconductor device comprising a. In claim 1, And plasma treating the substrate with He after forming the interlayer insulating film. The method of claim 1 or 2, Forming a trench that exposes the via; Etching the trench using a photosensitive film; Ashing with H ₂ O to remove the photoresist, and And organic cleaning the substrate. In claim 3, The organic cleaning is a method for forming a metal wiring of a semiconductor device wet cleaning with a fluorine-based or amine-based cleaning liquid. In claim 3, The buffer film is a method for forming a metal wiring of a semiconductor device, which is a USG in which TEOS is formed of a source gas. In claim 3, The thickness ratio change of the interlayer insulating film after the ashing is Δ35.4, The refractive index change of the interlayer insulating film after the ashing is Δ0.009. In claim 3, After the organic cleaning, the thickness ratio change of the interlayer insulating film is Δ74.9, The refractive index change of the interlayer insulating film after the organic cleaning is Δ0.008.

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