TWI553739B - Method for fabricating an aperture - Google Patents

Description

Method for forming an opening

SUMMARY OF THE INVENTION The present invention is directed to a method of making an opening, and more particularly to a method of making a contact hole-like opening in a hard mask and avoiding an arcuate profile of the sidewall of the contact hole during fabrication.

With the advancement of semiconductor processes, the miniaturization of microelectronic components has entered the deep sub-micron level, and the greater the density of semiconductor components on a single wafer, the smaller the spacing between components, which makes the production of contact holes more The more difficult it is. At present, it is still the direction of the industry to successfully dig high-aspect ratio contact holes in the dielectric layer to expose a conductive area with a sufficient area below.

Conventionally, a method of making a contact hole is generally provided by first providing a semiconductor substrate provided with a plurality of semiconductor elements, wherein the semiconductor element may comprise a metal oxide semiconductor (MOS) transistor or a resistor or the like. Forming at least one dielectric layer and a hard mask on the semiconductor substrate and covering the completed semiconductor component, and performing a series of pattern transfer processes on the hard mask and the dielectric layer by using a patterned photoresist layer. A contact hole is formed in the hard mask and the dielectric layer.

However, it is conventionally practiced to carry out the above-described pattern transfer process using an etching gas containing oxygen atoms, and when the etching gas is bombarded by a plasma to a hard mask, the side walls of the hard mask are often severely eroded to form an approximately arc-shaped outline. (bowing profile). The metal material which is subsequently filled in the contact hole for connecting the semiconductor element is likely to be completely sealed by the expansion of the contact hole, and the hole is first sealed, so that a seam is formed in the center of the contact hole filled with the metal material. And cause poor contact of components and affect the operational efficiency of the entire component.

SUMMARY OF THE INVENTION It is therefore a primary object of the present invention to provide a method of making openings such as contact holes to solve the problem of arcing contours in subsequent contact holes due to etching gases in current processes.

A preferred embodiment of the invention discloses a method of forming an opening. First, a carbon-containing hard mask is formed on the surface of a semiconductor substrate, and then the hard mask is etched by a gas containing no oxygen atoms to form a first opening in the hard mask.

Another embodiment of the invention is directed to a method of forming an opening. First forming a hard mask and a dielectric anti-reflective layer on a semiconductor substrate, and then forming a first bottom anti-reflective layer on the dielectric anti-reflective layer, the first bottom anti-reflective layer and a portion of the dielectric anti-reflective layer Forming a first opening, forming a second bottom anti-reflective layer on the dielectric anti-reflective layer and filling the first opening, forming a second opening in the second anti-reflective layer and the partial dielectric anti-reflective layer, and utilizing A gas containing no oxygen atoms performs an etching process on the hard mask, and the first opening and the second opening are transferred into the hard mask to form a plurality of third openings.

Yet another embodiment of the present invention is directed to a method of forming an opening. Forming a hard mask and a dielectric anti-reflective layer on a semiconductor substrate, then forming a first bottom anti-reflective layer on the dielectric anti-reflective layer, etching the first bottom anti-reflective layer, and dielectric anti-reflective layer And a hard mask for forming a first opening in the hard mask, forming a second bottom anti-reflective layer on the dielectric anti-reflective layer and filling the opening; and etching the second bottom anti-reflective layer, the dielectric anti-reflective layer and The hard mask forms a second opening in the hard mask, wherein the etching of the hard mask utilizes an etching gas that does not contain oxygen atoms.

Please refer to FIG. 1 to FIG. 3 . FIG. 1 to FIG. 3 are schematic diagrams showing a process for forming an opening according to a preferred embodiment of the present invention. As shown in Fig. 1, a semiconductor substrate 60 is first provided, such as a substrate composed of monocrystalline silicon, gallium arsenide (GaAs) or other semiconductor materials well known in the art. Then, at least one MOS transistor (not shown) is formed on the surface of the semiconductor substrate 60 according to a standard MOS transistor process, such as a P-type metal oxide semiconductor (PMOS) transistor or an N-type gold oxide semiconductor (NMOS) transistor. Or a complementary metal oxide semiconductor (CMOS) transistor, or other various semiconductor components. The MOS transistors may each have a standard transistor structure such as a gate structure, a sidewall spacer, a lightly doped source drain, a source/drain region, and a deuterated metal layer, and the gate structure may include a polysilicon gate. Or a metal gate completed by a high-k first process or a high-k last process. Since these processes are well known to those skilled in the art, no further details are provided herein.

A contact etching stop layer (CESL) 34 of nitride is then overlaid on the MOS transistor, wherein the contact etch stop layer 34 has a thickness of about 850 angstroms. The contact hole etch stop layer 34 can be selectively present, and the contact hole etch stop layer 34 can selectively provide stress to the underlying components. For example, for the case of NMOS underneath, a contact hole etch stop layer SiC having tensile stress can be used. For the case where the PMOS is below, a contact hole etch stop layer SiN having a compressive stress can be used. In the case of an STI or non-transistor element region below, the contact hole etch stop layer may be a composite contact hole etch stop layer combined with a tensile stress contact hole etch stop layer and a compressive stress contact hole etch stop layer, and the composite contact hole A buffer layer composed of an oxide is formed between the etch stop layers.

An interlayer dielectric (ILD) 36 is then formed and covers the surface of the contact hole etch stop layer 34. In this embodiment, the interlayer dielectric layer 36 may be composed of three material layers, including a dielectric layer formed by a sub-atmospheric pressure chemical vapor deposition (SACVD) process. A layer of phosphosilicate glass (PSG) and a layer of tetraethylorthosilicate (TEOS). The thickness of the entire interlayer dielectric layer 36 is about several thousand angstroms, preferably about 3150 angstroms; the thickness of the dielectric layer is about several hundred angstroms, and preferably 250 angstroms; the phosphosilicate glass (PSG) layer The thickness is about 1000 angstroms to 3,000 angstroms, and preferably 1900 angstroms; and the tetraethyl oxydecane layer has a thickness of about 100 angstroms to 2000 angstroms, and preferably 1000 angstroms. The interlayer dielectric layer 36 may be a single material layer in addition to the composite material layer; the interlayer dielectric layer 36 may include undoped bismuth glass (USG), borophosphosilicate glass (BPSG), and low in addition to the above materials. A dielectric constant dielectric material such as a porous dielectric material, tantalum carbide (SiC), bismuth oxynitride (SiON), or any combination thereof.

A hard mask 44 is then formed over the surface of the interlayer dielectric layer 36. According to a preferred embodiment of the present invention, the hard mask 44 is made of a carbonaceous material such as amorphous carbon, and is preferably selected from an advanced pattern film (APF) obtained from an American application material. (trade name) having a thickness of about 1000 angstroms to 5,000 angstroms, and preferably 2,000 angstroms. Then, a dielectric anti-reflective coating (DARC) 46 and a bottom anti-reflective coating (BARC) 48 are sequentially formed on the surface of the hard mask 44. In the present embodiment, the dielectric anti-reflective layer 46 may be a composite structure of a silicon oxynitride (SiON) layer together with an oxide layer, but is not limited thereto. The thickness of the dielectric anti-reflective layer 46 is about 250 angstroms, and the thickness of the bottom anti-reflective layer 48 is about 1020 angstroms. The dielectric anti-reflective layer 46 and the bottom anti-reflective layer 48 may be selectively present, and in addition to the inorganic material, the above two anti-reflective layers may further use an organic material formed by spin coating.

Then, the stacked film formed above is subjected to a plurality of pattern transfer processes to form an opening through the bottom anti-reflection layer 48, the dielectric anti-reflection layer 46, the hard mask 44, the interlayer dielectric layer 36, and the contact hole etch stop layer 34. Etc. and expose the underlying MOS transistor, such as the source/drain region of the transistor. For example, a patterned photoresist layer 54 suitable for a wavelength of about 193 nm is formed on the stacked film and exposes a portion of the upper surface of the bottom anti-reflective layer 48, wherein the patterned photoresist layer 54 has a thickness of about 1800 angstroms. . The patterned photoresist layer 54 is then selectively subjected to a descum step using a mixed etching gas of CO and O ₂ to remove excess residue that may result from poor development during exposure and development of the photoresist.

Next, as shown in FIG. 2, a patterned transfer process is performed on the bottom anti-reflective layer 48 by using the patterned photoresist layer 54 as a mask, for example, a mixed etching gas of CF ₄ and CH ₂ F ₂ is used to remove a portion of the bottom reactance. The reflective layer 48 and the dielectric anti-reflective layer 46 thereby transfer the opening pattern of the patterned photoresist layer 54 into the bottom anti-reflective layer 48 and the dielectric anti-reflective layer 46 and expose the underlying hard mask 44.

Then, as shown in FIG. 3, another pattern transfer process is performed by using the patterned photoresist layer 54 as a mask, for example, using an etching gas containing no oxygen atoms to remove a portion of the hard mask 44, thereby The openings in reflective layer 48 and dielectric anti-reflective layer 46 are continuously transferred into hard mask 44 to form a patterned hard mask. In this embodiment, the gas containing no oxygen atoms is preferably selected from the group consisting of H ₂ , N ₂ , He, NH ₃ , CH ₄ and C ₂ H ₄ . In addition, in the process of patterning the hard mask 44 by using an etching gas containing no oxygen atoms, the patterned photoresist layer 54 and the bottom anti-reflective layer 48 disposed above the hard mask 44 are simultaneously removed. An opening 56 is formed in the hard mask 44.

The patterned hard mask 44 can then be used as a mask to etch the interlayer dielectric layer 36 and the contact hole etch stop layer 34, for example, by using a mixed gas containing C ₄ F ₆ , O and Ar to remove a portion of the interlayer dielectric. The electrical layer 36, in turn, transfers the pattern of openings 56 in the hard mask 44 to the interlayer dielectric layer 36 and the contact hole etch stop layer 34 to accomplish the method of making an opening in accordance with a preferred embodiment of the present invention.

As the line width becomes smaller and smaller, since the current process cannot define the desired opening pattern from the hard mask by only one pattern transfer process, it is currently common to use two exposures in combination with two development methods to obtain the desired The opening pattern. Next, please refer to FIG. 4 to FIG. 5 , which are schematic diagrams showing the method of forming the opening to the double exposure and the two development processes according to an embodiment of the invention.

As shown in FIG. 4, following the opening 56 formed in the hard mask 44 in the foregoing FIG. 3, the present invention can sequentially form another bottom anti-reflection layer 62 and a patterned photoresist layer 64 on the dielectric anti-reflection layer. At 46, the bottom anti-reflective layer 62 preferably fills the opening 56 in the dielectric anti-reflective layer 46.

Next, as shown in FIG. 5, another etching process is first performed using the patterned photoresist layer 64 as a mask to remove portions of the bottom anti-reflective layer 62 and the dielectric anti-reflective layer 46 and expose the underlying hard mask 44. A portion of the hard mask 44 is then etched using an etching gas that does not contain oxygen atoms, thereby continuously transferring the openings in the bottom anti-reflective layer 62 and the dielectric anti-reflective layer 46 into the hard mask 44 to form a pattern. Hard cover. The patterned photoresist layer 64, the bottom anti-reflective layer 62 and the dielectric anti-reflective layer 46 can then be removed, and then the patterned hard mask 44 is directly used as a mask to etch the underlying interlayer dielectric layer 36 as in the first embodiment described above. The contact stop layer 34 is etched with the contact hole to complete the process of fabricating the opening of the present embodiment.

Next, please refer to FIG. 6 to FIG. 11 , which are schematic diagrams showing the method of forming the opening described above to the double exposure and two development processes according to another embodiment of the present invention. As shown in FIG. 6, a semiconductor substrate 80 is first provided, wherein at least one MOS transistor (not shown), such as a P-type MOS, can be formed according to the process requirements in the first embodiment. A crystal, an N-type metal oxide semiconductor (NMOS) transistor, or a complementary metal oxide semiconductor (CMOS) transistor, or other various semiconductor components.

Then, the semiconductor element is sequentially covered with a contact hole etch stop layer 82, an interlayer dielectric layer 84, a hard mask 86, a dielectric anti-reflection layer 88, a first bottom anti-reflection layer 90, and a patterned light. Resistive layer 92. The materials of the contact hole etch stop layer 82, the interlayer dielectric layer 84, the hard mask 86, the dielectric anti-reflective layer 88, and the first bottom anti-reflective layer 90 may be equivalent to the foregoing embodiments, and are not described herein.

Then, the first bottom anti-reflective layer 90 and the dielectric anti-reflective layer 88 are patterned by a patterned photoresist layer 92 as a mask, for example, by using a mixed etching gas of CF ₄ and CH ₂ F ₂ to remove a portion. The first bottom anti-reflective layer 90 and the portion of the dielectric anti-reflective layer 88. In this embodiment, the etching step preferably removes only about half of the thickness of the dielectric anti-reflective layer 88 and does not expose the underlying hard mask 86. Subsequently, as shown in FIG. 7, the patterned photoresist layer 92 is removed. The remaining first bottom anti-reflective layer 90 forms a first opening 94 in the dielectric anti-reflective layer 88.

Then, as shown in FIG. 8, a second bottom anti-reflective layer 96 and a patterned photoresist layer 98 are sequentially formed on the dielectric anti-reflective layer 88, wherein the second bottom anti-reflective layer 96 is preferably filled with dielectric. The first opening 94 in the anti-reflective layer 88. Next, as shown in FIG. 9, the second bottom anti-reflective layer 96 and the dielectric anti-reflective layer 88 are first patterned by using the patterned photoresist layer 98 as a mask to remove a portion of the second bottom anti-reflective layer. The dielectric anti-reflective layer 88 is 90 and half thick and does not expose the underlying hard mask 86. The patterned photoresist layer 98 and the remaining second bottom anti-reflective layer 96 are then removed to form a second opening 100 in the dielectric anti-reflective layer 88.

As shown in FIG. 10, the first anti-reflective layer 88 remaining at the bottom of the first opening 94 and the second opening 100 is removed by an etching process and the hard mask 86 is exposed, and then the remaining dielectric anti-reflective layer 88 is removed. Another etching process is performed as a mask to form a plurality of third openings 102 in the hard mask 86. As in the first embodiment of the method of etching the hard mask 86, the present embodiment preferably removes a portion of the hard mask 86 by an etching gas containing no oxygen atoms to form a third opening 102 and does not contain oxygen atoms. The gas is preferably selected from the group consisting of H ₂ , N ₂ , He, NH ₃ , CH ₄ and C ₂ H ₄ .

Then, as shown in FIG. 11, the remaining dielectric anti-reflective layer 88 is used as a mask, or the remaining dielectric anti-reflective layer 88 is removed first, and the patterned hard mask 86 is used as a mask to the interlayer dielectric layer. 84 and the contact hole etch stop layer 82 perform an etching process to transfer the third opening 102 pattern in the hard mask 86 to the interlayer dielectric layer 84 and the contact hole etch stop layer 82 to complete another embodiment of the present invention. The method of making an opening. It should be noted that the opening formed by the above method is not limited to a circular shape, and may be formed along the horizontal axis of the gate to form an approximately rectangular groove according to the process disclosed in the above embodiments. The slot contact opening is then filled with the desired metal material to form a rectangular contact plug. This embodiment is also within the scope of the present invention.

In summary, the present invention mainly etches the hard mask in the stacked film with an etching gas containing no oxygen atoms when etching the opening pattern in a stacked film to form a desired opening pattern in the hard mask. According to a preferred embodiment of the present invention, the hard mask is preferably selected from the APF film obtained from the U.S. application materials, and the etching gas containing no oxygen atoms is preferably selected from the group consisting of H ₂ , N ₂ , He, NH ₃ , CH ₄ and C ₂ H ₄ . Conventional etching gases based on CO/O ₂ /CO ₂ and the like often cause side etch of the hard mask, and the opening is short in addition to the local critical line width variation. Therefore, etching with a gas containing no oxygen atoms maintains a good hard mask profile, resulting in excellent critical dimension uniformity. Secondly, when the critical line width is reduced downward, etching the hard mask with a gas containing no oxygen atoms not only maintains good opening perpendicularity, but also avoids irregular openings caused by etching with oxygen atoms. Hole distortion problem.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

34. . . Contact hole etch stop layer

36. . . Interlayer dielectric layer

44. . . Hard mask

46. . . Dielectric anti-reflection layer

48. . . Bottom anti-reflection layer

54. . . Patterned photoresist layer

56. . . Opening

60. . . Semiconductor substrate

62. . . Bottom anti-reflection layer

64. . . Patterned photoresist layer

80. . . Semiconductor substrate

82. . . Contact hole etch stop layer

84. . . Interlayer dielectric layer

86. . . Hard mask

88. . . Dielectric anti-reflection layer

90. . . First bottom anti-reflection layer

92. . . Patterned photoresist layer

94. . . First opening

96. . . Second bottom anti-reflection layer

98. . . Patterned photoresist layer

100. . . Second opening

102. . . Third opening

1 to 3 are schematic views showing a process for forming an opening in accordance with a preferred embodiment of the present invention.

4 to 5 are schematic views showing a process for forming an opening according to another embodiment of the present invention.

6 to 11 are schematic views showing a process for forming an opening according to another embodiment of the present invention.

34. . . Contact hole etch stop layer

36. . . Interlayer dielectric layer

44. . . Hard mask

46. . . Dielectric anti-reflection layer

48. . . Bottom anti-reflection layer

54. . . Patterned photoresist layer

56. . . Opening

60. . . Semiconductor substrate

Claims (14)

A method of forming an opening, comprising: forming a hard mask and a dielectric anti-reflective layer on a semiconductor substrate; forming a first bottom anti-reflective layer on the dielectric anti-reflective layer; Forming a first opening in the dielectric anti-reflective layer; forming a second bottom anti-reflective layer on the dielectric anti-reflective layer and filling the first opening; and the second anti-reflective layer and the portion Forming a second opening in the dielectric anti-reflective layer; and performing an etching process on the hard mask by using a gas containing no oxygen atoms, transferring the first opening and the second opening into the hard mask to form A plurality of third openings. The method of claim 1, wherein the hard mask comprises amorphous carbon. The method of claim 1, wherein the oxygen-free gas is selected from the group consisting of H ₂ , N ₂ , He, NH ₃ , CH ₄ and C ₂ H ₄ . The method of claim 1, wherein the forming of the hard mask further comprises forming a gate structure on the surface of the semiconductor substrate, the gate structure being provided with a contact hole etch stop layer and a dielectric layer. The method of claim 4, wherein the gate structure comprises a polysilicon gate or a metal gate. The method of claim 1, wherein the forming the second opening further comprises: removing the portion of the first anti-reflective layer under the first opening and the second opening to expose the hard mask; The etching process is performed using the remaining dielectric anti-reflective layer to form the third openings in the hard mask. The method of claim 1, further comprising defining a rectangular groove on the horizontal axis of the gate structure by using the third openings. A method of forming an opening, comprising: forming a hard mask and a dielectric anti-reflective layer on a semiconductor substrate; forming a first bottom anti-reflective layer on the dielectric anti-reflective layer; etching the first bottom anti-reflection a layer, the dielectric anti-reflective layer and the hard mask to form a first opening in the hard mask; forming a second bottom anti-reflective layer on the dielectric anti-reflective layer and filling the first opening; And etching the second bottom anti-reflective layer, the dielectric anti-reflective layer and the hard mask to form a second opening in the hard mask, wherein the hard mask is etched An etching gas that does not contain oxygen atoms. The method of claim 8, wherein the hard mask comprises amorphous carbon. The method of claim 8, wherein the oxygen-free gas is selected from the group consisting of H ₂ , N ₂ , He, NH ₃ , CH ₄ and C ₂ H ₄ . The method of claim 8, wherein the forming of the hard mask further comprises forming a gate structure on the surface of the semiconductor substrate, the gate structure being provided with a contact hole etch stop layer and a dielectric layer. The method of claim 11, wherein the gate structure comprises a polysilicon gate or a metal gate. The method of claim 8, wherein the forming the second opening further comprises performing an etching process using the remaining dielectric anti-reflective layer to form a plurality of third openings in the hard mask. The method of claim 11, further comprising defining a rectangular groove on the horizontal axis of the gate structure by using the first opening.