201044459 六、發明說明： 【發明所屬之技術領域】 本發明是關於-種製作開口的方法，尤指—種於介電層 中製作出接觸洞般的開口且可避免在製作過程中使接觸洞 側壁產生弧狀輪廓的方法。 〇 【先前技術】 隨著半導體製㈣進步，微電子元件的微小化已進入到 深次微米等級，而單―晶片上的半導㈣件的密度越大表示 疋件之間的間隔也就越小’這使得接觸洞的製作越來越困 難。目前’要在介電層中順利挖出高深寬比接觸洞，以暴露 出下方足夠面積的導電區域，仍是業界努力的方向。 月參照第1圖’第！圖為習知製作一接觸洞的方法示奇 圖。如圖中所示’首先提供—設置有複數個半導體元件㈣ :體基底(圖未示)’其中半導體元件可包含金氧半導體_S) 電晶體或電阻等元件。錢形成至少—介電層以半導體 基底上並覆蓋所完成的半導體元件。接著形成一圖案化遮 罩，例如一圖案化光阻層14在介電層12上並暴露出部分介 ^層12表面’然後以圖案化光阻層14當作遮罩進行一餘刻 製程，利用含有蝕刻氣體的電漿去除部分介電層12,以於介 電層12中形成一接觸洞16並暴露出半導體基底上的半導體 201044459 元件，例如金氧半導體電晶體的源極/汲極等。 習知以電漿在介電層12中形成接觸洞16等開口的時 候，触刻氣體中的分子會先被電漿内的高能量電子轟擊而產 生各種離子，並藉此轟擊介電層12而產生揮發性的化合物。 需注意的是，由於圖案化光阻層14是設置在所欲形成的接 觸洞16開口周圍，電漿離子在轟擊未被圖案化光阻層14所 〇覆蓋的介電層12表面時常常因角度的轉折而轟擊至接觸洞 16的介電層12側壁’使介電層12靠近接觸洞16入口的側 』嚴重钕蝕而形成一約略弧狀的輪廓(b〇wing pr〇file)l8。後 續填入接觸洞16中用來連接半導體元件的金屬材料容易因 接觸洞16内部的擴張而無法完全填滿整個接觸洞16便先封 住洞口，使填入金屬材料的接觸洞16中央部位形成縫隙 (seam)並造成元件接觸不良而影響整個元件的運作效能。 〇 【發明内容】 因此本發明之主要目的是提供—種製作如接觸洞等開口 的方法’以解決現行製程中容易雜子過度㈣介電層的側 J而使製作出的接觸洞產生圓弧輪廓等問題。 本發明較佳實_是揭露—種形賴σ的方法，包含有 2下步驟：沈積-介電層與—硬遮罩層於—半導體基底表 ，圖案化該硬遮罩層以於該硬遮罩層_形成—開口；利用 201044459 一包含有CaXb及CdHXe的氣體對該圖案化之硬遮罩層及該 介電層進行一預處理製程，其中該a、b、d及e各代表一整 數而X則代表一鹵素原子(halogen atom);以及進行一餘刻 製程以將該開口轉移至該介電層。 【實施方式】 請參照第2圖至第3圖，第2圖至第3圖為本發明較佳 〇 實施例形成一開口之製程示意圖。如第2圖所示，首先提供 一半導體基底60，例如一由單晶石夕(monocrystalline silicon)、坤化鎵(gallium arsenide, GaAs)或其他習知技藝所 熟知之半導體材質所構成的基底。然後依據標準金氧半導體 電晶體製程於半導體基底60表面形成至少一金氧半導體電 晶體（圖未示），例如p型金氧半導體(PM〇s)電晶體、N型金 氧半導體(NMOS)電晶體或互補型金氧半導體(CM〇S)電晶 〇 體’或其他各式半導體元件。其中金氧半導體電晶體可各具 有間極、側壁子、輕摻雜源極汲極、源極/汲極區域及矽化金 屬層等標準電晶體結構，在此不另加贅述。 接著依序覆蓋一由氧化物所構成的緩衝層（buffer layer)32與一由氮化物所構成的接觸洞蝕刻停止層（contact etching stop layer，Cesl)34在金氧半導體電晶體上。緩衝層 32的厚度約為50埃，而接觸洞蝕刻停止層34的厚度則約為 850埃°緩衝層32及接觸洞蝕刻停止層34皆可選擇性地存 6 201044459 在’且接觸洞蝕刻停止層34可選擇性地對下方的元件提供 應力，例如針對下方為NM〇S的情況可使用具有伸張應力的 接觸洞颠刻停止層SiC、針對下方為pm〇S的情況可使用具 有壓縮應力的接觸洞蝕刻停止層SiN。在下方為STI或非電 晶體元件區域的情況下’接觸洞蝕刻停止層可能為伸張應力 接觸洞餘刻停止層與壓縮應力接觸洞蝕刻停止層所組合的 複合接觸洞蝕刻停止層，且複合接觸洞蝕刻停止層間具有氧 〇化物所構成的緩衝層。 然後形成一層間介電層（interlayer dielectric, ILD)36並覆 蓋接觸洞蝕刻停止層34表面。在本實施例中，層間介電層 36較佳由三種材料層所構成，包括一由次常壓化學氣相沈積 (sub-atmospheric pressure chemical vapor deposition, SACVD) 製程所形成的介電層38，一麟石夕玻璃(phosphosilicate glass, PSG)層 40 以及一四乙基氧石夕烧(tetraethylorthosilicate, TEOS) 〇 層42。其中整個層間介電層36的厚度約為數千埃，較佳約 為3150埃；介電層的38厚度約為數百埃，且較佳為250埃； 磷矽玻璃(phosphosilicateglass，PSG)層40的厚度約介於 1000埃至3000埃，且較佳為1900埃；而四乙基氧石夕烧層 42的厚度約介於1 〇〇埃至2000埃，且較佳為1 〇〇〇埃。層間 介電層36除了是複合材料層外，亦可是單一材料層；層間 介電層36除了包含上述材料外，亦可包含無摻雜之矽玻璃 (USG)、硼磷玻璃(BPSG)、低介電常數介電材料如多孔性介 201044459 電材料、碳化矽（SiC)、氮氧化矽（SiON)、或其任意組合。 然後形成一硬遮罩層44在層間介電層36表面。依據本 發明之較佳實施例，硬遮罩層44是選自由美國應用材料取 知的進階圖案化薄膜(advance(j pattern film, APF)(商品名）， 其厚度約介於1000埃至5〇〇〇埃，且較佳為2〇〇〇埃。然後 再依序形成一介電抗反射層（dieiectric anti-reflective coating， 〇 DARC)46 與一底抗反射層（b〇tt〇m anti-reflective coating, BARC)48在硬遮罩層44表面。在本實施例中，介電抗反射 層46較佳由一釓氧化石夕（snic〇n 〇Xynitride，si〇N)層50與一 氧化層52 —同構成。其中氮氧化矽層5〇的厚度約2〇〇埃， 氧化層52的厚度約50埃，而底抗反射層48的厚度則約1〇2〇 埃。介電抗反射層46、底抗反射層48可選擇性地存在，且 除了無機材料外，上述兩抗反射層更可使用以旋塗方式形成 0 的有機材料。 接著對上述形成的堆疊薄膜進行複數次的圖案轉移製 程，以形成-開口貫穿底抗反射層48、介電抗反射層的、 硬遮罩層44、層間介電層36、觸洞触刻停止層乂以及緩衝 層32等並暴露出底下的金氧半導體電晶體，如電晶體的源 極/汲極區域等。首先，先形成一適用於波長約193奈米的圖 案化光阻層54在上述的堆㈣膜上並暴^部分堆疊薄膜 的上表面，其中圖案化光阻層54的厚度約為腦埃。然後 201044459 選擇性地利用CO及〇2的混合姓刻氣體對圖案化光阻層54 進行-去殘渣(des嶋)步驟，以去除光阻在曝光與顯影過程 中可能因顯影不良而產生的多餘殘渣。 接著如第3圖所示’利用圖案化光阻層54當作遮罩對底 抗反射層48進行一圖案轉移製程，例如湘CFaCH2F2 的混合触刻氣體來去除部分的底抗反射層48與介電抗反射 〇層46’藉此將圖案化光阻層54的開口圖案轉移至底抗反射 層48與介電抗反射層46中並暴露出下方的硬遮罩層44。其 中’ CF4在圖案化的過程中是作為主要的㈣反應氣體，而 CH#2則是用來保護蝕刻對象物側壁的保護氣體。舉例來 說’ CF4在圖案化過程中主要用來去除大部分的底抗反射層 48與介電抗反射層46’並將圖案化光阻層54的開口圖案轉 移至底抗反射層48與介電抗反射層46。CH2F2在蝕刻的過 Q耘中則疋與底抗反射層佔與介電抗反射層46反應，使底抗 反射層48與介電抗反射層46被蚀刻出開口的側壁得以在蝕 刻過程中產生聚合物堆積，藉此保護側壁不至在離子轟擊時 過度受損而產生弧狀的輪廓。 然後再以圖案化光阻層54當作遮罩進行另一次圖案轉移 製程’例如利用包含有CO及〇2的混合蝕刻氣體來去除部分 的硬遮罩層44，藉此將底抗反射層48與介電抗反射層46 中的開口持續轉移至硬遮罩層44中。在本實施例中，利用 201044459 CO及〇2的混合蝕刻氣體來圖案化硬遮罩層44的過程中亦 會同時去除設於硬遮罩層44上方的圖案化光阻層54及底抗 反射層48。 接著利用含有CaXb及CdHXe的混合氣體對圖案化之硬遮 罩層44及層間介電層36進行一預處理並同時去除介電抗反 射層46 ’其中CaXb及CdHXe中的a、b、d及e各代表一整 〇 數而x則代表一鹵素原子(halogen atom)。依據本發明之較 佳實施例’上述混合氣體中的Caxb主要包含CF4而CdHXe 則包含CHF3。如同上述圖案化底抗反射層48與介電抗反射 層46的實施例’此次混合氣體中的CF4在圖案化的過程中 是作為主要的蝕刻反應氣體，而CHF3則是用來保護蝕刻對 象物側壁的保護氣體。舉例來說，CF4在圖案化過程中主要 用來去除介電抗反射層46、開口中剩餘的硬遮罩層44並暴 0 露出層間介電層36表面以及些微的層間介電層36，藉此將 介電抗反射層46的開口圖案轉移至整個硬遮罩層44與層間 介電層36上部。CHF3在圖案化的過程中則是與硬遮罩層44 及層間介電層36反應，使硬遮罩層44與層間介電層36的 侧壁在蝕刻過程中產生聚合物堆積，藉此保護被蝕刻出開口 的側壁不受到離子的過渡轟擊而產生弧狀的輪廓。 隨後以圖案化之硬遮罩層44作為遮罩對層間介電層36 進行一圖案轉移製程’例如利用含有C4F6、〇及Ar的混合 201044459 氣體來去除部分的層間介電層36，進而將硬遮罩層44中的 開口圖案轉移至層間介電層36的四乙基氧矽烷層42、磷矽 玻璃層40以及介電層38。 接著再以圖案化之硬遮罩層44作為遮罩對設於層間介電 層36下方的接觸洞蝕刻停止層34進行第一階段的圖案轉移 製程，例如以CH2F2、Ο及Ar的混合氣體來去除大部分的 q 接觸洞蝕刻停止層34，藉此將硬遮罩層44的開口圖案轉移 至接觸洞蝕刻停止層34中。隨後先利用02作為蝕刻氣體來 去除硬遮罩層44，然後再以CH3F、Ο及Ar的混合氣體來對 接觸洞蝕刻停止層34進行第二階段的圖案轉移製程，以將 層間介電層36的開口圖案完全轉移至接觸洞蝕刻停止層34 並暴露出設於其下的緩衝層32。最後再對緩衝層32進行一 圖案轉移製程，利用CF4、CHF3以及Ar所組成的混合氣體· 來去除部分的緩衝層32，藉此將接觸洞蝕刻停止層34的開 ❹ 口圖案轉移至緩衝層32並暴露出下方的半導體元件，例如 金氧半導體電晶體的源極/汲極區域等。至此即完成本發明較 佳實施例於堆疊介電層中製作出接觸洞的方法。 上述的所有蝕刻步驟可在相同蝕刻機台中以原位方式 (in-situly)完成，或皆於不同I虫刻機台中以非原位方式 (ex-situly)完成，或部分步驟於相同餘刻機台中以原位方式 (in-situly)完成而其餘步驟於不同餘刻台中以非原位方式 11 201044459 0 (ex-situly)完成。又’上述的所有蝕刻步驟可以偵測終點 (end-point)之方式進行或以時間模式（time-mode)進行。 綜上所述’本發明主要在金氧半導體元件上沈積完多層 介電薄膜後利用由CaXb及CdHXe所組成的混合氣體來進行 圖案轉移製程並蝕刻出所需要的開口圖案，其中CaXb主要 包含CF4而CdHXe則包含CHF3或CH2F2。以上述實施例為 〇 例’在圖案化底抗反射層的時候可採用由CF4及CH2F2所構 成的混合蝕刻氣體來去除部分的底抗反射層，而在圖案化硬 遮罩層的時候可採用由CF4及CHF3所組成的混合氣體來去 除部分的硬遮罩層與設於其下的層間介電層以形成開口。其 中，CF4在圖案化的過程中是作為主要的蝕刻反應氣體，而 CHf2則疋用來保護触刻對象物側壁的保護氣體。採用上述 的整合性氣體組合來蝕刻多層介電薄膜，本發明除了可在圖 ❹案轉移的過&巾製作tB所需的開π圖案，又可同時在餘刻的 介電薄膜侧壁產生聚合物堆積並保護側壁不至在離子轟擊 時過渡艾損而產生弧狀的輪廓，以達到一種加乘的效果。 以上所述僅為本發明之較佳實施例，凡依本發明申請專 利範圍所做之均等變化歸飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為習知製作一接觸洞的方法示意圖。 12 201044459 專 第2圖至第3圖為本發明較佳實施例形成一開口之製程示意 圖。 【主要元件符號說明】 12 介電層 14 圖案化光阻層 16 接觸洞 18 輪廓 32 緩衝層 34 接觸洞餘刻停止層 36 層間介電層 38 介電層 40 磷矽玻璃層 42 四乙基氧矽烷層 44 硬遮罩層 46 介電抗反射層 48 底抗反射層 50 氮氧化矽層 52 氧化層 54 圖案化光阻層 60 半導體基底 13201044459 VI. Description of the Invention: [Technical Field] The present invention relates to a method for making an opening, in particular to making a contact hole-like opening in a dielectric layer and avoiding contact holes in the manufacturing process. A method in which the sidewalls create an arcuate profile. 〇[Prior Art] With the advancement of semiconductor manufacturing (4), the miniaturization of microelectronic components has entered the deep sub-micron level, and the higher the density of the semi-conductive (four) pieces on the single wafer, the more the interval between the components Small 'This makes the production of contact holes more and more difficult. At present, it is still the direction of the industry to successfully dig high-aspect ratio contact holes in the dielectric layer to expose a conductive area underneath. Refer to Figure 1 for the month! The figure shows a method for making a contact hole. As shown in the figure, 'first provided' is provided with a plurality of semiconductor elements (four): a bulk substrate (not shown), wherein the semiconductor element may comprise a metal oxide semiconductor (S) transistor or a resistor or the like. The money forms at least a dielectric layer on the semiconductor substrate and covers the completed semiconductor component. Then, a patterned mask is formed, for example, a patterned photoresist layer 14 is exposed on the dielectric layer 12 and a portion of the surface of the layer 12 is exposed, and then the patterned photoresist layer 14 is used as a mask for a process. Part of the dielectric layer 12 is removed by a plasma containing an etching gas to form a contact hole 16 in the dielectric layer 12 and expose a semiconductor 201044459 component on the semiconductor substrate, such as a source/drain of the MOS transistor. . It is known that when a plasma forms an opening such as a contact hole 16 in the dielectric layer 12, the molecules in the etched gas are first bombarded by high-energy electrons in the plasma to generate various ions, thereby bombarding the dielectric layer 12 And produce volatile compounds. It should be noted that since the patterned photoresist layer 14 is disposed around the opening of the contact hole 16 to be formed, the plasma ions are often caused by bombardment of the surface of the dielectric layer 12 which is not covered by the patterned photoresist layer 14. The turning of the angle and the side wall of the dielectric layer 12 of the contact hole 16 are made "the side of the dielectric layer 12 close to the entrance of the contact hole 16" is severely eroded to form a roughly arcuate profile (b〇wing pr〇file) l8. The metal material which is subsequently filled in the contact hole 16 for connecting the semiconductor element is liable to completely fill the entire contact hole 16 due to the expansion of the contact hole 16 to seal the hole first, so that the center portion of the contact hole 16 filled with the metal material is formed. The seam and the poor contact of the components affect the operational efficiency of the entire component. 〇 [Summary of the Invention] Therefore, the main object of the present invention is to provide a method for making an opening such as a contact hole to solve the problem of easily interfering with the side (J) of the dielectric layer in the current process, and to create a circular arc of the contact hole. Contours and other issues. Preferably, the present invention discloses a method for forming a sigma σ, comprising the steps of: depositing a dielectric layer and a hard mask layer on a semiconductor substrate, patterning the hard mask layer for the hard a mask layer _ formation-opening; using a gas containing CaXb and CdHXe in 201044459 to perform a pre-treatment process on the patterned hard mask layer and the dielectric layer, wherein the a, b, d, and e each represent a An integer and X represents a halogen atom; and a process is performed to transfer the opening to the dielectric layer. [Embodiment] Please refer to Figs. 2 to 3, and Figs. 2 to 3 are schematic views showing a process for forming an opening according to a preferred embodiment of the present invention. As shown in Fig. 2, a semiconductor substrate 60 is first provided, such as a substrate made of monocrystalline silicon, gallium arsenide (GaAs) or other semiconductor materials well known in the art. Then, at least one MOS transistor (not shown) is formed on the surface of the semiconductor substrate 60 according to a standard MOS transistor process, such as a p-type MOS transistor or an N-type MOS device. A transistor or a complementary metal oxide semiconductor (CM〇S) transistor, or other various semiconductor components. The MOS transistors may have standard transistor structures such as interpoles, sidewalls, lightly doped source drains, source/drain regions, and deuterated metal layers, and are not described herein. Then, a buffer layer 32 composed of an oxide and a contact etching stop layer (Ces1) 34 made of a nitride are sequentially coated on the MOS transistor. The buffer layer 32 has a thickness of about 50 angstroms, and the contact hole etch stop layer 34 has a thickness of about 850 angstroms. The buffer layer 32 and the contact hole etch stop layer 34 are selectively stored in the vicinity of 2010. The layer 34 can selectively provide stress to the underlying components. For example, for the case of NM〇S below, the contact hole with the tensile stress can be used to inscribe the stop layer SiC, and for the case of the lower pm〇S, the compressive stress can be used. The contact hole etch stop layer SiN. In the case of an STI or non-transistor element region below, the contact hole etch stop layer may be a composite contact hole etch stop layer combined with a tensile stress contact hole residual stop layer and a compressive stress contact hole etch stop layer, and the composite contact The hole etch stop layer has a buffer layer composed of oxysulfide. An interlayer dielectric (ILD) 36 is then formed and covers the surface of the contact hole etch stop layer 34. In the present embodiment, the interlayer dielectric layer 36 is preferably composed of three material layers, including a dielectric layer 38 formed by a sub-atmospheric pressure chemical vapor deposition (SACVD) process. A phosphosilicate glass (PSG) layer 40 and a tetraethylorthosilicate (TEOS) layer 42. The thickness of the entire interlayer dielectric layer 36 is about several thousand angstroms, preferably about 3150 angstroms; the thickness of the dielectric layer 38 is about several hundred angstroms, and preferably 250 angstroms; a phosphosilicate glass (PSG) layer The thickness of 40 is about 1000 angstroms to 3,000 angstroms, and preferably 1900 angstroms; and the thickness of the tetraethyl oxysulfide layer 42 is about 1 angstrom to 2,000 angstroms, and preferably 1 Å. Ai. The interlayer dielectric layer 36 may be a single material layer in addition to the composite material layer; the interlayer dielectric layer 36 may include undoped bismuth glass (USG), borophosphosilicate glass (BPSG), and low in addition to the above materials. Dielectric constant dielectric materials such as porous dielectric 201044459 electrical materials, tantalum carbide (SiC), niobium oxynitride (SiON), or any combination thereof. A hard mask layer 44 is then formed on the surface of the interlayer dielectric layer 36. In accordance with a preferred embodiment of the present invention, the hard mask layer 44 is an advanced patterning film (APF) (trade name) selected from U.S. application materials, having a thickness of about 1000 angstroms to about 5 angstroms, and preferably 2 angstroms. Then, a dielectric anti-reflective coating (〇DARC) 46 and a bottom anti-reflective layer (b〇tt〇m) are sequentially formed. The anti-reflective coating, BARC) 48 is on the surface of the hard mask layer 44. In the present embodiment, the dielectric anti-reflective layer 46 is preferably composed of a layer of snic〇n 〇Xynitride (si〇N) 50 and The oxide layer 52 is formed in the same manner, wherein the ruthenium oxynitride layer 5 〇 has a thickness of about 2 Å, the oxide layer 52 has a thickness of about 50 angstroms, and the bottom anti-reflective layer 48 has a thickness of about 1 〇 2 Å. The anti-reflection layer 46 and the bottom anti-reflection layer 48 may be selectively present, and in addition to the inorganic material, the above two anti-reflection layers may further use an organic material which is formed by spin coating to form 0. Next, the stacked film formed as described above is subjected to plural times. Pattern transfer process to form-open through the bottom anti-reflective layer 48, dielectric anti-reflective layer The hard mask layer 44, the interlayer dielectric layer 36, the contact hole stop layer 乂 and the buffer layer 32, etc., and expose the underlying MOS transistor, such as the source/drain region of the transistor, etc. First, First, a patterned photoresist layer 54 suitable for a wavelength of about 193 nm is formed on the above-mentioned stack (four) film and the upper surface of the partially stacked film is formed, wherein the thickness of the patterned photoresist layer 54 is about cerebral angstrom. Then 201044459 The patterning photoresist layer 54 is selectively subjected to a des-removal step using a mixed gas of CO and 〇2 to remove excess residue which may be caused by poor development during exposure and development. Then, as shown in FIG. 3, a patterned transfer process is performed on the bottom anti-reflective layer 48 by using the patterned photoresist layer 54 as a mask, for example, a mixed-touch gas of the CFaCH2F2 to remove a portion of the bottom anti-reflective layer 48 and the intermediate layer. The electro-reflective ruthenium layer 46' thereby transfers the opening pattern of the patterned photoresist layer 54 to the bottom anti-reflective layer 48 and the dielectric anti-reflective layer 46 and exposes the underlying hard mask layer 44. wherein 'CF4 is in the pattern As the main (four) reaction gas And CH#2 is a shielding gas used to protect the sidewall of the object to be etched. For example, 'CF4 is mainly used to remove most of the bottom anti-reflective layer 48 and the dielectric anti-reflective layer 46' during the patterning process and The opening pattern of the patterned photoresist layer 54 is transferred to the bottom anti-reflective layer 48 and the dielectric anti-reflective layer 46. In the etched Q CH, the 疋 and the bottom anti-reflective layer occupies the dielectric anti-reflective layer 46, so that The bottom anti-reflective layer 48 and the dielectric anti-reflective layer 46 are etched out of the sidewalls of the opening to create a polymer buildup during the etching process, thereby protecting the sidewall from excessive damage during ion bombardment to create an arcuate profile. Then, the patterned photoresist layer 54 is used as a mask to perform another pattern transfer process, for example, by using a mixed etching gas containing CO and germanium 2 to remove a portion of the hard mask layer 44, thereby the bottom anti-reflective layer 48. The openings in the dielectric anti-reflective layer 46 are continuously transferred into the hard mask layer 44. In the present embodiment, the patterned photoresist layer 54 and the bottom anti-reflection provided on the hard mask layer 44 are also removed during the patterning of the hard mask layer 44 by using the mixed etching gas of 201044459 CO and 〇2. Layer 48. Then, the patterned hard mask layer 44 and the interlayer dielectric layer 36 are subjected to a pretreatment by using a mixed gas containing CaXb and CdHXe, and simultaneously remove the dielectric anti-reflective layer 46', wherein a, b, and d in CaXb and CdHXe are Each e represents a whole number of turns and x represents a halogen atom. According to a preferred embodiment of the present invention, Caxb in the above mixed gas mainly contains CF4 and CdHXe contains CHF3. As in the above embodiment of the patterned bottom anti-reflective layer 48 and the dielectric anti-reflective layer 46, CF4 in this mixed gas is used as the main etching reaction gas in the patterning process, and CHF3 is used to protect the etching target. Protective gas on the sidewall of the object. For example, CF4 is mainly used to remove the dielectric anti-reflective layer 46, the remaining hard mask layer 44 in the opening, and expose the surface of the interlayer dielectric layer 36 and the micro-interlayer dielectric layer 36 during the patterning process. This transfers the opening pattern of the dielectric anti-reflective layer 46 to the entire upper of the hard mask layer 44 and the interlayer dielectric layer 36. During the patterning process, CHF3 reacts with the hard mask layer 44 and the interlayer dielectric layer 36, so that the hard mask layer 44 and the sidewalls of the interlayer dielectric layer 36 are polymerized during the etching process, thereby protecting The sidewalls that are etched out of the opening are not subjected to a transitional bombardment of ions to create an arcuate profile. Then, a pattern transfer process is performed on the interlayer dielectric layer 36 by using the patterned hard mask layer 44 as a mask. For example, a portion of the interlayer dielectric layer 36 is removed by using a mixed 201044459 gas containing C4F6, lanthanum and Ar, and then hard. The opening pattern in the mask layer 44 is transferred to the tetraethyloxonane layer 42, the phosphorous glass layer 40, and the dielectric layer 38 of the interlayer dielectric layer 36. Then, the first stage pattern transfer process is performed on the contact hole etch stop layer 34 disposed under the interlayer dielectric layer 36 by using the patterned hard mask layer 44 as a mask, for example, a mixed gas of CH2F2, bismuth, and Ar. Most of the q contact hole etch stop layer 34 is removed, thereby transferring the opening pattern of the hard mask layer 44 into the contact hole etch stop layer 34. Subsequently, the hard mask layer 44 is removed by using 02 as an etching gas, and then the contact hole etching stop layer 34 is subjected to a second-stage pattern transfer process by using a mixed gas of CH3F, germanium, and Ar to laminate the interlayer dielectric layer 36. The opening pattern is completely transferred to the contact hole etch stop layer 34 and exposes the buffer layer 32 disposed thereunder. Finally, a buffer transfer process is performed on the buffer layer 32, and a portion of the buffer layer 32 is removed by using a mixed gas of CF4, CHF3, and Ar, thereby transferring the opening pattern of the contact hole etch stop layer 34 to the buffer layer. 32 and expose the underlying semiconductor component, such as the source/drain region of the MOS transistor. Thus, a method of making a contact hole in a stacked dielectric layer is accomplished by a preferred embodiment of the present invention. All of the etching steps described above can be done in-situly in the same etching machine, or ex-situly in different I-spot machines, or part of the same in the same moment. The machine is completed in-situly and the remaining steps are performed in an ex situ manner 11 201044459 0 (ex-situly) in different residual stages. Further, all of the above etching steps can be performed in an end-point manner or in a time-mode manner. In summary, the present invention mainly performs a pattern transfer process by using a mixed gas composed of CaXb and CdHXe after depositing a multilayer dielectric film on a MOS device, and etching a desired opening pattern, wherein CaXb mainly contains CF4. CdHXe contains CHF3 or CH2F2. Taking the above embodiment as an example, a mixed etching gas composed of CF4 and CH2F2 may be used to remove a portion of the bottom anti-reflection layer when patterning the bottom anti-reflection layer, and may be used when patterning the hard mask layer. A mixed gas composed of CF4 and CHF3 is used to remove a portion of the hard mask layer and the interlayer dielectric layer disposed thereunder to form an opening. Among them, CF4 is used as the main etching reaction gas in the process of patterning, and CHf2 is used to protect the shielding gas of the sidewall of the object. The above-mentioned integrated gas combination is used to etch the multilayer dielectric film, and the present invention can produce the π pattern required for tB in addition to the transfer film and the film can be simultaneously produced on the sidewall of the remaining dielectric film. The polymer builds up and protects the sidewall from the transitional escaping during ion bombardment to create an arcuate profile to achieve a multiplier effect. The above are only the preferred embodiments of the present invention, and all modifications made to the patentable scope of the present invention are intended to be within the scope of the present invention. [Simple description of the drawing] Fig. 1 is a schematic view showing a method of making a contact hole. 12 201044459 Specific Figures 2 through 3 are schematic views of a process for forming an opening in accordance with a preferred embodiment of the present invention. [Main component symbol description] 12 dielectric layer 14 patterned photoresist layer 16 contact hole 18 profile 32 buffer layer 34 contact hole residual stop layer 36 interlayer dielectric layer 38 dielectric layer 40 phosphorous glass layer 42 tetraethyl oxygen Decane layer 44 hard mask layer 46 dielectric anti-reflective layer 48 bottom anti-reflective layer 50 hafnium oxynitride layer 52 oxide layer 54 patterned photoresist layer 60 semiconductor substrate 13