201250856 六、發明說明： 【發明所屬之技術領域】 本發明是關於一種製作開口的方法，尤指一種於硬遮罩中製 作出接觸洞般的開口且可避免在製作過程中使接觸洞側壁 產生弧狀輪廓的方法。 【先前技術】 隨著半導體製程的進步，微電子元件的微小化已進入到深次 微米等級，而單一晶片上的半導體元件的密度越大表示元件 之間的間隔也就越小，這使得接觸洞的製作越來越困難。目 前，要在介電層中順利挖出高深寬比接觸洞，以暴露出下方 足夠面積的導電區域，仍是業界努力的方向。 習知製作一接觸洞的方法通常先提供一設置有複數個半導 體元件的半導體基底，其中半導體元件可包含金氧半導體 (MOS)電晶體或電阻等元件。然後依序形成至少一介電層與 一硬遮罩在半導體基底上並覆蓋所完成的半導體元件，並利 用一圖案化光阻層對硬遮罩及介電層進行一系列的圖案轉 移製程，以於硬遮罩及介電層中形成一接觸洞。 然而，習知通常使用包含氧原子的蝕刻氣體進行上述圖案轉 移製程，而此蝕刻氣體由電漿轟擊至硬遮罩的時候時常會使 硬遮罩的側壁嚴重侵餘而形成一約略弧狀的輪扉（bowing 201250856 profile)。後續填入接觸洞中用來‘連接半導體元件的金屬材料 容易因接觸洞内部的擴張而無法完全填滿整個接觸洞便先 封住洞口，使填入金屬材料的接觸洞中央部位形成縫隙 (seam)並造成元件接觸不良而影響整個元件的運作效能。 【發明内容】 因此本發明之主要目的是提供一種製作如接觸洞等開口的 方法，以解決現行製程中因蚀刻氣體的緣故而使後續接觸洞 產生圓弧輪廓等問題。 本發明較佳實施例是揭露一種形成開口的方法。首先形成一 含碳之硬遮罩於一半導體基底表面，然後利用一不含氧原子 之氣體對該硬遮罩進行一蝕刻製程，以於該硬遮罩中形成一 第一開口。 本發明另一實施例是揭露一種形成開口的方法。首先形成一 硬遮罩以及一介電抗反射層於一半導體基底上，然後形成一 第一底抗反射層於介電抗反射層上、於第一底抗反射層及部 分介電抗反射層中形成一第一開口、形成一第二底抗反射層 於介電抗反射層上並填滿第一開口、於第二抗反射層及部分 "電抗反射層中形成一第二開口以及利用一不含氧原子之 氣體對硬遮罩進行一蝕刻製程，將第一開口及第二開口轉移 至硬遮罩中以形成複數個第三開口。 201250856 本發明又一實施例是揭露一種形成開口的方法。首先形成一 硬遮罩以及一介電抗反射層於一半導體基底上，然後形成— 第一底抗反射層於該介電抗反射層上、蝕刻第一底抗反射 層、介電抗反射層以及硬遮罩以於硬遮罩中形成—第一開 口、形成一第二底抗反射層於介電抗反射層上並填滿開口以 及触刻第二底抗反射層、介電抗反射層及硬遮罩以於硬遮罩 中形成一第二開口 ’其中蝕刻硬遮罩時係利用一不含氧原子 之蝕刻氣體。 【實施方式】 請參照第1圖至第3圖，第1圖至第3圖為本發明較佳實施 例形成一開口之製程示意圖。如第1圖所示，首先提供—半 導體基底60，例如一由單晶石夕（monocrystalline silicon)、石中 化鎵(gallium arsenide，GaAs)或其他習知技藝所熟知之半導 體材質所構成的基底。然後依據標準金氧半導體電晶體製程 於半導體基底60表面形成至少一金氧半導體電晶體（圖未 示），例如P型金氧半導體(PM0S)電晶體、N型金氧半導體 (NMOS)電晶體或互補型金氧半導體(CMOS)電晶體，或其他 各式半導體元件。其中金氧半導體電晶體可各具有閘極結 構、側壁子、輕摻雜源極汲極、源極/没極區域及破化金屬層 等標準電晶體結構，且閘極結構可包含一多晶矽閘極或一由 前高介電常數介電層（high-K first)製程或後高介電常數介電 5 201250856 層（higWClast)製程所完 知本領域者所熟知技藝，在此=加極#由；：這些製程均為熟 =Γ錢化物所構成的接觸洞_停止層(一 觸.门ryer, CESL)34在錢半導㈣㈣上，其中接 觸鑛刻停止層34的厚度約為 34可選擇性地存在，且減、、⑽，賴膽刻停止層 觸洞蝕刻停止層34可選擇性地對 供應力，例如針對下方為nm〇s的情況可使用201250856 VI. Description of the Invention: [Technical Field] The present invention relates to a method for making an opening, in particular to making a contact hole-like opening in a hard mask and avoiding the generation of a contact hole sidewall during the manufacturing process. The method of arc contouring. [Prior Art] With the advancement of semiconductor processes, the miniaturization of microelectronic components has entered the deep sub-micron level, and the greater the density of semiconductor components on a single wafer, the smaller the spacing between components, which makes contact The production of holes is getting harder and harder. At present, it is still the direction of the industry to successfully dig high-aspect ratio contact holes in the dielectric layer to expose a conductive area under a sufficient area. Conventionally, a method of making a contact hole is generally provided by first providing a semiconductor substrate provided with a plurality of semiconductor elements, wherein the semiconductor element may comprise a metal oxide semiconductor (MOS) transistor or a resistor or the like. Forming at least one dielectric layer and a hard mask on the semiconductor substrate and covering the completed semiconductor component, and performing a series of pattern transfer processes on the hard mask and the dielectric layer by using a patterned photoresist layer. A contact hole is formed in the hard mask and the dielectric layer. However, it is conventionally practiced to perform the above-described pattern transfer process using an etching gas containing oxygen atoms, and when the etching gas is bombarded by the plasma to the hard mask, the side walls of the hard mask are often severely invaded to form an approximately arc-like shape. Rim (bowing 201250856 profile). The metal material that is subsequently filled in the contact hole to 'connect the semiconductor element is easily sealed by the expansion of the contact hole and cannot completely fill the entire contact hole, so that the hole is first sealed, and a gap is formed in the center of the contact hole filled with the metal material (seam) ) and cause poor contact of components and affect the operational efficiency of the entire component. SUMMARY OF THE INVENTION It is therefore a primary object of the present invention to provide a method of making openings such as contact holes to solve the problem of arcing contours of subsequent contact holes due to etching gases in current processes. A preferred embodiment of the invention discloses a method of forming an opening. First, a carbon-containing hard mask is formed on the surface of a semiconductor substrate, and then the hard mask is etched by a gas containing no oxygen atoms to form a first opening in the hard mask. Another embodiment of the invention is directed to a method of forming an opening. First forming a hard mask and a dielectric anti-reflective layer on a semiconductor substrate, and then forming a first bottom anti-reflective layer on the dielectric anti-reflective layer, the first bottom anti-reflective layer and a portion of the dielectric anti-reflective layer Forming a first opening, forming a second bottom anti-reflective layer on the dielectric anti-reflective layer and filling the first opening, forming a second opening in the second anti-reflective layer and the portion of the anti-reflective layer, and utilizing A gas containing no oxygen atoms performs an etching process on the hard mask, and the first opening and the second opening are transferred into the hard mask to form a plurality of third openings. 201250856 Another embodiment of the present invention is directed to a method of forming an opening. First, a hard mask and a dielectric anti-reflective layer are formed on a semiconductor substrate, and then a first bottom anti-reflective layer is formed on the dielectric anti-reflective layer, and the first bottom anti-reflective layer and the dielectric anti-reflective layer are etched. And a hard mask is formed in the hard mask to form a first opening, form a second bottom anti-reflective layer on the dielectric anti-reflective layer and fill the opening, and touch the second bottom anti-reflective layer, the dielectric anti-reflective layer And the hard mask forms a second opening in the hard mask. The etching of the hard mask utilizes an etching gas containing no oxygen atoms. [Embodiment] Referring to Figures 1 to 3, Figs. 1 to 3 are schematic views showing a process for forming an opening in accordance with a preferred embodiment of the present invention. As shown in Fig. 1, first, a semiconductor substrate 60 is provided, such as a substrate made of monocrystalline silicon, gallium arsenide (GaAs), or other semiconductor materials well known in the art. . Then, at least one MOS transistor (not shown) is formed on the surface of the semiconductor substrate 60 according to a standard MOS transistor process, such as a P-type metal oxide semiconductor (PMOS) transistor or an N-type gold oxide semiconductor (NMOS) transistor. Or a complementary metal oxide semiconductor (CMOS) transistor, or other various semiconductor components. The MOS transistors may each have a standard transistor structure such as a gate structure, a sidewall spacer, a lightly doped source drain, a source/no-polar region, and a damaged metal layer, and the gate structure may include a polysilicon gate. A pole or a high-k first dielectric process or a high-high dielectric constant dielectric 5 201250856 layer (higWClast) process is well known in the art, in this case = 加极# By:: These processes are all made by the mature = Γ money compound contact hole _ stop layer (one touch ryer, CESL) 34 on the carbon semi-conductive (four) (four), wherein the thickness of the contact ore stop layer 34 is about 34 Selectively present, and subtracting, (10), the etch stop layer etch stop layer 34 can selectively supply the force, for example, for the case of nm 〇 s below
具有伸張應力的接觸洞钱刻停止層Sic、針對下方為PM0S 的情況可使用具有壓縮應力的接觸麗刻停止層siN。在下 方為STI或非電晶體元件區域的情況下，接觸洞蚀刻停止層 y能為伸張應力接觸洞银刻停止層與壓縮應力接觸洞银刻 ^止層所、.a σ的複合接觸洞㈣停止層，且複合接觸洞银刻 停止層間具有氧化物所構成的緩衝層。 然後形成-層間介電層（interlayer dielectric，ILD)36並覆蓋 接觸洞蝕刻停止層34表面。在本實施例中，層間介電層36 可由二種材料層所構成，包括一由次常壓化學氣相沈積 (sub-atmospheric pressure chemical vapor deposition, SACVD) 製程所形成的介電層，一填石夕玻璃(phosphosiHcategiass; PSG)層以及一四乙基氧石夕烧(tetraethyiorthosiHcate，TE0S) 層。其中整個層間介電層30的厚度約為數千埃，較佳約為 3150埃；介電層的厚度約為數百埃，且較佳為25〇埃；磷矽 201250856 玻璃(Ph〇sPh〇silicate glass，PSG)層的厚度約介於ι〇〇〇埃至 3〇00埃’且較佳為19〇0埃；而四乙基氧石夕烧層的厚度約介 於100埃至2_埃，且較佳為1〇〇〇埃。層間介電層36除 了是複合材料層外，亦可是單一材料層；層間介電層36除 了包含上述材料外，亦可包含無摻雜之矽玻璃（USG)、硼磷 玻璃（BPSG)、低介電常數介電材料如多孔性介電材料、碳化 矽（SiC)、氮氧化矽（SiON)、或其任意組合。 然後开〉成一硬遮罩44在層間介電層36表面。依據本發明之 較佳貫施例，硬遮罩44是由非晶碳(amorph〇us carb〇n)等含 碳材料所構成，且較佳選自由美國應用材料取得的進階圖案 化薄膜（advanced pattern film, APF)(商品名），其厚度約介於 1000埃至5000埃，且較佳為2000埃。然後再依序形成一介 電抗反射層（dielectric anti-reflective coating，DARC)46 與一 底抗反射層（bottom anti_reflective coating，BARC)48 在硬遮 罩44表面。在本實施例中，介電抗反射層46可由一氮氧化 矽（silicon oxynitride，SiON)層與一氧化層一同構成之複合結 構’但不揭限於此。其中介電抗反射層46的厚度約250埃， 而底抗反射層48的厚度則約1020埃。介電抗反射層46、底 抗反射層48可選擇性地存在，且除了無機材料外，上述兩 抗反射層更可使用以旋塗方式形成的有機材料。 接著對上述形成的堆疊薄膜進行複數次的圖案轉移製程，以 201250856 形成一開口貫穿底抗反射層48、介電抗反射層46、硬遮罩 44、層間介電層36以及觸洞蝕刻停止層34等並暴露出底下 的金氧半導體電晶體，如電晶體的源極/汲極區域等。例如， 先形成一適用於波長約193奈米的圖案化光阻層54在上述 的堆疊薄膜上並暴露出部分底抗反射層48上表面，其中圖 案化光阻層54的厚度約為_埃。然後選擇性地利用⑺ 及〇2的混合蝕刻氣體對圖案化光阻層54進行一去殘渣 (descum)步驟，以去除光阻在曝光與顯影過程中可能因顯影 不良而產生的多餘殘渣。 接著如第2圖所示，利用圖案化光阻層54當作遮罩對底抗 反射層48進行一圖案轉移製程，例如利用eh及CH2Fy々 混合蝕刻氣體來去除部分的底抗反射層48與介電抗反射層 46,藉此將圖案化光阻層54的開口圖案轉移至底抗反射層 48與介電抗反射層46中並暴露出下方的硬遮罩44。 然後如第3圖所示，再以圖案化光阻層54當作遮罩進行另 一次圖案轉移製程，例如利用不含氧原子的蝕刻氣體來去除 部分的硬遮罩44,藉此將底抗反射層48與介電抗反射層46 中的開口持續轉移至硬遮罩44中以形成一圖案化之硬遮 罩。在本實施例中，該不含氧原子之氣體較佳選自H2、N2、 He、NHS、CH4及。另外需注意的是，利用不含氧原子 的蝕刻氣體來圖案化硬遮罩44的過程中亦會同時去除設於 8 201250856 硬遮罩44上方的圖案化光租層54 遮罩44中形成一開口 ％。 &抗反射層48,以於硬 隨後可以圖案化之硬遮罩44作 觸洞㈣停止層34進行1助/對相介制36及接 遮罩44中的開口 56圖案轉目日：電層％，進而將硬 刻停止層34,以完成本發明較佳丨電層％與接觸洞餘 佳貫轭例製作一開口的方法。 隨著線寬越來越小，由於現今 程從前述硬遮罩中定義出所I.、、、核以-次圖案轉移製 ^ 1¾ ± # ISt 3B? 、碣口圖案，因此目前普遍採 用兩-人曝从配兩次顯影的方 著請參照第4圖至第到所需的開口圖案。接 ^ ^為本發明一實施例將上述形成 開口的方林配至兩切光與料_製程之示意圖。 如第4圖所示，接續前 56，本發明可依序ρ 遮罩44中形成的開口 阻層64於介電抗反射〜射層62以及-圖案化光 θ 46上，其中底抗反射層62較佳填 滿，丨電抗反射層46中的開口 56。 接著如第5圖所干，4 另-崎程以:4=化光阻層64當作遮罩進行 並暴露出下方的硬=反射層62與介電抗反射層46 万的硬遮罩料。然後再利用不含氧原子的關氣 201250856The contact hole stop layer Sic having the tensile stress and the contact stop layer siN having the compressive stress may be used for the case where the lower portion is the PM0S. In the case where the STI or non-transistor element region is below, the contact hole etch stop layer y can be a composite contact hole of the silver-engraved layer of the tensile stress contact hole and the silver-etched stop layer of the compressive stress contact hole, .a σ (4) The layer is stopped, and the composite contact hole has a buffer layer composed of an oxide between the stop layers. An interlayer dielectric (ILD) 36 is then formed and covers the surface of the contact hole etch stop layer 34. In this embodiment, the interlayer dielectric layer 36 may be composed of two material layers, including a dielectric layer formed by a sub-atmospheric pressure chemical vapor deposition (SACVD) process. The layer of phosphosi Hcategiass (PSG) and the layer of tetraethyiorthosi Hcate (TE0S). The thickness of the entire interlayer dielectric layer 30 is about several thousand angstroms, preferably about 3150 angstroms; the thickness of the dielectric layer is about several hundred angstroms, and preferably 25 angstroms; and the phosphor 矽 201250856 glass (Ph〇sPh〇) The thickness of the silicate glass (PSG) layer is about ι 〇〇〇 to 3 〇 Å ′ and preferably 19 〇 0 Å; and the thickness of the tetraethyl oxynitride layer is about 100 Å to 2 _ It is preferably 1 angstrom. The interlayer dielectric layer 36 may be a single material layer in addition to the composite material layer; the interlayer dielectric layer 36 may include undoped bismuth glass (USG), borophosphosilicate glass (BPSG), and low in addition to the above materials. A dielectric constant dielectric material such as a porous dielectric material, tantalum carbide (SiC), bismuth oxynitride (SiON), or any combination thereof. Then, a hard mask 44 is formed on the surface of the interlayer dielectric layer 36. According to a preferred embodiment of the present invention, the hard mask 44 is made of a carbonaceous material such as amorphous carbon (amorph〇us carb〇n), and is preferably selected from advanced patterned films obtained from US applied materials ( The advanced pattern film, APF) (trade name) has a thickness of about 1000 angstroms to 5,000 angstroms, and preferably 2,000 angstroms. Then, a dielectric anti-reflective coating (DARC) 46 and a bottom anti-reflective coating (BARC) 48 are sequentially formed on the surface of the hard mask 44. In the present embodiment, the dielectric anti-reflective layer 46 may be a composite structure of a silicon oxynitride (SiON) layer together with an oxide layer, but is not limited thereto. The thickness of the dielectric anti-reflective layer 46 is about 250 angstroms, and the thickness of the bottom anti-reflective layer 48 is about 1020 angstroms. The dielectric anti-reflective layer 46 and the bottom anti-reflective layer 48 may be selectively present, and in addition to the inorganic material, the above two anti-reflective layers may further use an organic material formed by spin coating. Then, the stacked thin film formed above is subjected to a plurality of pattern transfer processes to form an opening through the bottom anti-reflective layer 48, the dielectric anti-reflective layer 46, the hard mask 44, the interlayer dielectric layer 36, and the contact hole etch stop layer at 201250856. 34 and so on and expose the underlying MOS transistor, such as the source/drain region of the transistor. For example, a patterned photoresist layer 54 suitable for a wavelength of about 193 nm is formed on the above stacked film and exposes a portion of the upper surface of the bottom anti-reflective layer 48, wherein the thickness of the patterned photoresist layer 54 is about _ angstrom . The patterned photoresist layer 54 is then selectively subjected to a descum step using a mixed etching gas of (7) and 〇2 to remove excess residue which may be caused by poor development during exposure and development. Next, as shown in FIG. 2, a patterned transfer process is performed on the bottom anti-reflective layer 48 by using the patterned photoresist layer 54 as a mask, for example, using eh and CH2Fy々 mixed etching gas to remove a portion of the bottom anti-reflective layer 48 and The anti-reflective layer 46 is dielectric, whereby the opening pattern of the patterned photoresist layer 54 is transferred into the bottom anti-reflective layer 48 and the dielectric anti-reflective layer 46 and the underlying hard mask 44 is exposed. Then, as shown in FIG. 3, another pattern transfer process is performed by using the patterned photoresist layer 54 as a mask, for example, using an etching gas containing no oxygen atoms to remove a portion of the hard mask 44, thereby The openings in reflective layer 48 and dielectric anti-reflective layer 46 are continuously transferred into hard mask 44 to form a patterned hard mask. In this embodiment, the gas containing no oxygen atoms is preferably selected from the group consisting of H2, N2, He, NHS, and CH4. In addition, in the process of patterning the hard mask 44 by using an etching gas containing no oxygen atoms, the patterned light-receiving layer 54 disposed above the hard mask 44 of 201250856 is also removed to form a mask 44. % of opening. & anti-reflective layer 48, for hard masking hard mask 44 as a contact hole (4) stop layer 34 for 1 assist / phase interaction 36 and the opening 56 pattern in the mask 44: The layer %, and in turn, the hard stop layer 34, to accomplish the preferred method of the present invention, is to make an opening for the contact hole yoke. As the line width becomes smaller and smaller, since the current process defines the I., , and the core in the above-mentioned hard mask, the pattern is transferred to the pattern, and the mouth pattern is generally adopted. For people exposed to the two developments, please refer to Figure 4 to the desired opening pattern. In the embodiment of the present invention, a schematic diagram of the above-mentioned open-cut square forest to two cut light and material processes is illustrated. As shown in FIG. 4, before the splicing 56, the present invention can sequentially form the opening resist layer 64 formed in the mask 44 on the dielectric anti-reflection layer 62 and the patterned light θ 46, wherein the bottom anti-reflection layer 62 is preferably filled with an opening 56 in the anti-reflective layer 46. Then, as shown in FIG. 5, 4 another-Saki process is carried out as: 4 = the photoresist layer 64 is used as a mask and exposes the underlying hard = reflective layer 62 and the dielectric anti-reflective layer of 460,000 hard masking material. . Then use the gas that does not contain oxygen atoms 201250856
體來蝕刻部分的硬遮罩44，藉此將底抗反射層62及介電^ 反射層40中的開口持續轉移至硬遮罩44中以形成一圖案几 之硬遮罩。卩通後可去除圖案化光阻層64、底抗反射居6之' 介電抗反射層46,然後如上述第一實施例直接利用圖案化與 硬遮罩44作為遮罩蝕刻下方的層間介電層36與接觸洞 停止層34，以完成本實施例製作開口的製程。 X 接著請參照第6圖至第11圖，其為本發明另一實施例將 述形成開口的方法搭配至兩次曝光與兩次顯影製程之示土 圖。如第6圖所示，首先提供一半導體基底80，其上可如第 一實施例中依據製程需求形成至少一金氧半導體電晶體（圖 未示），例如P型金氧半導體(PMOS)電晶體、N型金氧半導 體(NMOS)電晶體或互補型金氧半導體(CMOS)電晶體，或其 他各式半導體元件。 然後依序在·半導體元件上覆蓋一接觸洞蝕刻停止層82、一層 間介電層84、一硬遮罩86、一介電抗反射層88、一第一底 抗反射層90以及一圖案化光阻層92。其中接觸洞蝕刻停止 層82、層間介電層84、硬遮罩86、介電抗反射層88以及第 一底抗反射層9〇等之材料可等同前述實施例，在此不另加 贅述。 接著先以圖案化光阻層92當作遮罩對第一底抗反射層90與 201250856 介電抗反射層.88進行一圖案轉移製程，例如利用cf4及 CHf2的混合餘刻氣體來去除部分的第一底抗反射層9〇與 部分介電抗反射層88。在本實施例中，此蝕刻步驟較佳僅去 除約一半厚度的介電抗反射層88且不暴露出下方的硬遮罩 86，隨後如第7圖所示，去除圖案化光阻層92與剩餘的第 一底抗反射層9〇’以於介電抗反射層88中形成一第一開口 94 ° 然後如第8圖所示，依序形成一第二底抗反射層96以及一 圖案化光阻層98於介電抗反射層88上，其中第二底抗反射 層96較佳填滿介電抗反射層88中的第一開口 94。接著如第 9圖所示，先利用圖案化光阻層98當作遮罩對第二底抗反射 層96與介電抗反射層88進行另一圖案轉移製程，去除部分 第二底抗反射層90及一半厚度的介電抗反射層88且不暴露 出下方的硬遮罩86。然後去除圖案化光阻層98與剩餘的第 一底抗反射層96，以於介電抗反射層88中形成一第二開口 100。 如第10圖所示，先以一道蝕刻製程去除第一開口 94及第二 開口 100底部剩餘的介電抗反射層88並暴露出硬遮罩86， 然後再以剩餘的介電抗反射層88當作遮罩進行另-餘刻製 私以於硬遮罩86中形成複數個第三開口 1的。如同第一實 轭例蝕刻硬遮罩86的方法，本實施例較佳以不含氧原子的 11 201250856 蝕刻氣體對硬遮罩來去除部分的硬遮罩％以形成第三開口 102 ’且不含氧原子的氣體較佳選自H2、N2、He、NH3、CH4 及 c2h4。 隨後如第11圖所示，以剩餘的介電抗反射層88當作遮罩， 或先去除剩餘的介電抗反射層88，以圖案化之硬遮罩86作 為遮罩對層間介電層84及接觸洞蝕刻停止層82進行一蝕刻 製程，進而將硬遮罩86中的第三開口 102圖案轉移至層間 ”電層84與接觸洞餘刻停止層82中，以完成本發明另一實 轭例製作一開口的方法。需注意的是，本發明例於由上述方 法所製作出的開口並不侷限於圓形，又可依據上述各實施例 所揭露的製程沿著閘極之橫軸延伸而形成約略矩形的溝槽 (slot c〇ntact opening) ’然後再填入所需的金屬材料來形成一 矩形接觸插塞，此實施例也屬本發明所涵蓋的範圍。 綜上所述，本發明主要在一堆疊薄膜中蝕刻出開口圖案時利 用不含氧原子的姓刻氣體對堆疊薄膜中的硬遮罩進行蝕 J 乂於硬遮罩中形成所需的開口圖。依據本發明之較佳實 施例，硬遮罩較佳選自美國應用材料取得的ApF薄膜，且不 含氧原子的蝕刻氣體較佳選自Η:、Nr He、NH3、CH4及 QH4。由於習知常採用c〇/〇2/c〇2等為基礎的蝕刻氣體通常 會對硬遮罩產生側向蝕刻（side etch)，除了容易發生局部性 臨界線寬變異之外又會造成開口短小。因此以不含氧原子的 12 201250856 氣體進行蝕刻便可維持良好的硬遮罩輪廓，而得到優良的平 均臨界線寬（critical dimension uniformity)。其次，當臨界線 寬往下縮小時，以不含氧原子的氣體對硬遮罩進行蝕刻不但 可維持良好的開口垂直性，又可避免習知因採用含氧原子钱 刻氣體而造成開口不規則化(hole distortion)的問題。 以上所述僅為本發明之較佳實施例，凡依本發明申請專 利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第3圖為本發明較佳 形成開口之製程示 圖。 〜 第4圖至第5圖為本發明另一實施例形成開口之製程示 圖。 ^ 6圖至第11圖為本發明另-實施例形成開π之製程示意 圖。 。 【主要元件符號說明】 36 層間介電層 46 介電抗反射層 54 圖案化光阻層 60 半導體基底 64 圖案化光阻層 34 接觸洞钱刻停止層 44 硬遮罩 48 底抗反射層 56 開口 62 底抗反射層 201250856 80 半導體基底 82 84 層間介電層 86 88 介電抗反射層 90 92 圖案化光阻層 94 96 第二底抗反射層 98 100 第二開口 102 接觸洞蝕刻停止層 硬遮罩 第一底抗反射層 第一開口 圖案化光阻層 第三開口 14A portion of the hard mask 44 is etched to thereby continuously transfer the openings in the bottom anti-reflective layer 62 and the dielectric reflective layer 40 into the hard mask 44 to form a pattern of hard masks. After the pass-through, the patterned photoresist layer 64 and the bottom anti-reflective layer of the dielectric anti-reflective layer 46 can be removed, and then the patterned and hard mask 44 is directly used as the mask interlayer under the mask etching as in the first embodiment described above. The electrical layer 36 and the contact hole stop layer 34 are used to complete the process of making the opening in this embodiment. X Next, referring to Figs. 6 to 11, a schematic diagram of a method of forming an opening to a double exposure and a two development process according to another embodiment of the present invention. As shown in FIG. 6, a semiconductor substrate 80 is first provided, wherein at least one MOS transistor (not shown), such as a P-type MOS, can be formed according to the process requirements in the first embodiment. A crystal, an N-type metal oxide semiconductor (NMOS) transistor, or a complementary metal oxide semiconductor (CMOS) transistor, or other various semiconductor components. Then, the semiconductor element is sequentially covered with a contact hole etch stop layer 82, an interlayer dielectric layer 84, a hard mask 86, a dielectric anti-reflection layer 88, a first bottom anti-reflection layer 90, and a pattern. Photoresist layer 92. The material of the contact hole etch stop layer 82, the interlayer dielectric layer 84, the hard mask 86, the dielectric anti-reflective layer 88, and the first bottom anti-reflective layer 9A may be equivalent to the foregoing embodiments, and will not be further described herein. Then, the patterned photoresist layer 92 is used as a mask to perform a pattern transfer process on the first bottom anti-reflective layer 90 and the 201250856 dielectric anti-reflective layer 88. For example, the mixed residual gas of cf4 and CHf2 is used to remove part of the film. The first bottom anti-reflective layer 9 is partially and partially dielectric anti-reflective layer 88. In this embodiment, the etching step preferably removes only about half of the thickness of the dielectric anti-reflective layer 88 and does not expose the underlying hard mask 86. Subsequently, as shown in FIG. 7, the patterned photoresist layer 92 is removed. The remaining first bottom anti-reflective layer 9'' forms a first opening 94° in the dielectric anti-reflective layer 88. Then, as shown in FIG. 8, a second anti-reflective layer 96 and a pattern are sequentially formed. The photoresist layer 98 is on the dielectric anti-reflective layer 88, wherein the second bottom anti-reflective layer 96 preferably fills the first opening 94 in the dielectric anti-reflective layer 88. Next, as shown in FIG. 9, the second bottom anti-reflective layer 96 and the dielectric anti-reflective layer 88 are first patterned by using the patterned photoresist layer 98 as a mask to remove a portion of the second bottom anti-reflective layer. The dielectric anti-reflective layer 88 is 90 and half thick and does not expose the underlying hard mask 86. The patterned photoresist layer 98 and the remaining first bottom anti-reflective layer 96 are then removed to form a second opening 100 in the dielectric anti-reflective layer 88. As shown in FIG. 10, the first anti-reflective layer 88 remaining at the bottom of the first opening 94 and the second opening 100 is removed by an etching process and the hard mask 86 is exposed, and then the remaining dielectric anti-reflective layer 88 is removed. A plurality of third openings 1 are formed in the hard mask 86 as a mask. As in the first method of etching the hard mask 86, the present embodiment preferably removes a portion of the hard mask % to form a third opening 102' with an 11 201250856 etching gas-free hard mask that does not contain oxygen atoms. The gas containing oxygen atoms is preferably selected from the group consisting of H2, N2, He, NH3, CH4 and c2h4. Then, as shown in FIG. 11, the remaining dielectric anti-reflective layer 88 is used as a mask, or the remaining dielectric anti-reflective layer 88 is removed first, and the patterned hard mask 86 is used as a mask to the interlayer dielectric layer. 84 and the contact hole etch stop layer 82 perform an etching process, thereby transferring the pattern of the third opening 102 in the hard mask 86 to the interlayer "electric layer 84" and the contact hole stop layer 82 to complete another embodiment of the present invention. The yoke example is a method of making an opening. It should be noted that the opening made by the above method is not limited to a circular shape, and may be along the horizontal axis of the gate according to the process disclosed in the above embodiments. Extending to form a slot c〇ntact opening 'and then filling in the desired metal material to form a rectangular contact plug, this embodiment is also within the scope of the present invention. The present invention mainly etches a hard mask in a stacked film by etching a pattern with a gas containing no oxygen atoms in a stacked film to form a desired opening pattern in the hard mask. According to the present invention, Preferred embodiment, hard mask The etching gas selected from the Applied Materials of the United States and containing no oxygen atoms is preferably selected from the group consisting of ruthenium: Nr He, NH3, CH4, and QH4. Since conventionally, c〇/〇2/c〇2 is used. The basic etching gas usually produces a side etch for the hard mask, which is short in addition to the local critical line width variation, so it can be etched with 12 201250856 gas without oxygen atoms. Maintaining a good hard mask profile results in excellent critical dimension uniformity. Second, when the critical line width is reduced downward, etching the hard mask with a gas containing no oxygen atoms is not only good. The verticality of the opening avoids the problem of hole distortion caused by the use of oxygen-containing atoms to engrave the gas. The above description is only a preferred embodiment of the present invention, and the patent application according to the present invention Equivalent changes and modifications made to the scope are within the scope of the present invention. [Simplified Schematic Description] Figs. 1 to 3 are diagrams showing a preferred process for forming an opening of the present invention. 5 is a process diagram for forming an opening according to another embodiment of the present invention. FIG. 6 to FIG. 11 are schematic diagrams showing a process for forming an open π according to another embodiment of the present invention. [Description of Main Components] 36 Interlayer Dielectric Layer 46 Dielectric anti-reflective layer 54 patterned photoresist layer 60 semiconductor substrate 64 patterned photoresist layer 34 contact hole stop layer 44 hard mask 48 bottom anti-reflective layer 56 opening 62 bottom anti-reflection layer 201250856 80 semiconductor substrate 82 84 interlayer Dielectric layer 86 88 dielectric anti-reflection layer 90 92 patterned photoresist layer 94 96 second bottom anti-reflection layer 98 100 second opening 102 contact hole etching stop layer hard mask first bottom anti-reflection layer first opening patterning Photoresist layer third opening 14