KR20100076457A - Method for forming semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to enable a side wall profile to form a via hole having vertical or positive slopes by remaining a second insulating layer on the side wall of the via hole during the formation of a dual damascene pattern. CONSTITUTION: An etch stopping layer(33A) and a first insulating layer(34) are successively formed on a conductive film(32). The first insulating layer is selectively etched so that a via hole(36) is formed to expose the etch stopping layer. A second insulating layer(37A) is formed to cover the upper side of the first insulating layer. The second insulating layer remains on the side wall of the via hole and the upper surface of the first insulating layer. A trench(41) connected to the via hole is formed by etching the second insulating layer. A second insulating layer remaining in the side wall of the via hole is removed through a cleaning process.

Description

Semiconductor device manufacturing method {METHOD FOR FORMING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor device, and more particularly, to a method for manufacturing metal wiring of a semiconductor device using a dual damascene process.

Recently, in order to solve the RC delay problem of the metal wiring due to the increase in the degree of integration of semiconductor devices, a technology of using copper (Cu) as the metal wiring has been introduced and applied. In forming metal interconnections using copper, since copper has very poor etching characteristics, copper interconnects are typically formed using a damascene process. As a damascene process, a single damascene process or a dual damascene process is used, and a dual damascene process is mainly applied.

1A and 1C are cross-sectional views illustrating a method for manufacturing copper wiring using a dual damascene process according to the related art.

As shown in FIG. 1A, after the conductive film 12, the etch stop film 13, and the insulating film 14 are sequentially formed on the substrate 11 having a predetermined structure, the first hard mask pattern ( 18 is used to etch the insulating layer 14 to form a via hole 15 exposing the etch stop layer 13 on the conductive layer 12.

As shown in FIG. 1B, the insulating layer 14 is etched by a predetermined thickness with a second hard mask pattern 19 having an opening having a line width larger than that of the first hard mask pattern 18 to be connected to the via hole 15. The trench 16 is formed to form a dual damascene pattern 17 including the via hole 15 and the trench 16, and the etch stop layer 13 is etched to expose the upper surface of the conductive layer 12. .

As shown in FIG. 1C, after the barrier metal film 20 is formed along the surface of the structure including the dual damascene pattern 17, the dual damascene pattern 17 is embedded on the barrier metal film 20. Copper is deposited to Next, the planarization process is performed until the upper surface of the insulating film 14 is exposed to complete the copper wiring 21.

However, according to the related art, a nitride film is used as the etch stop film 13, an oxide film is used as the insulating film 14, and the etching stop film 13 is etched while the trench 16 is formed. In the etching process to expose the upper surface of the fluorine (F) containing gas is used as an etching gas. In this case, a transient loss of the etch stop layer 13 may occur due to the insufficient etching selectivity of the etch stop layer 13 and the insulating layer 14 with respect to the etch gas.

Specifically, as shown in 'A' of FIG. 1B, the etch stop layer 13 has a profile that is struck in the direction of the outer wall of the via hole 15. That is, a problem arises that the sidewall profile of the lower region of the via hole 15 including the etch stop layer 13 has a negative slope.

As such, when the via hole 15 sidewall profile has a negative slope due to the excessive loss of the etch stop layer 13, the barrier metal layer 20 may not be normally deposited as shown in FIG. As a result of a buried defect such as void, such as 'C', the contact resistance is increased between the copper wiring 21 and the conductive film 12, and the resistance and RC delay of the copper wiring 21 are increased. Occurs.

As a result, when the sidewall profile of the via hole 15 has a negative slope due to the excessive loss of the etch stop layer 13, a problem occurs that the characteristics and the reliability of the semiconductor device are deteriorated.

The present invention has been proposed to solve the above-mentioned problems of the prior art, and in forming a dual damascene pattern consisting of a via hole and a trench, the via hole lower region sidewall profile has a negative slope due to excessive loss of the etch stop layer. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can be prevented.

According to one aspect of the present invention, a method of manufacturing a semiconductor device includes: sequentially forming an etch stop layer and a first insulating layer on a conductive layer; Selectively etching the first insulating layer to form a via hole exposing the etch stop layer on the conductive layer; Forming a second insulating layer filling the via hole and covering an upper surface of the first insulating layer; Etching the second insulating layer by using a hard mask pattern having a line width of an opening smaller than the line width of the via hole as an etch barrier, and leaving the second insulating layer on an upper surface of the first insulating layer and sidewalls of the via hole; Etching the second insulating layer by using a hard mask pattern having a line width larger than that of the via hole as an etch barrier to form a trench connected to the via hole, and etching the etch stop layer to expose an upper surface of the conductive layer; And performing a cleaning process to remove the second insulating layer remaining on the sidewalls of the via holes. The method may further include forming a barrier metal film on the via hole and the trench surface, and forming a metal wiring on the barrier metal film to fill the via hole and the trench.

According to the present invention based on the above-described problem solving means, in forming a dual damascene pattern consisting of via holes and trenches, the second insulating film is left on the sidewalls of the via holes, even if a transient loss of the etch stop layer occurs during the trench formation process. By removing the second insulating layer remaining on the sidewalls of the via holes through the via, the sidewall profile may have a via hole having a vertical or positive slope. This prevents abnormal deposition of the barrier metal film inside the dual damascene pattern or buried defects such as voids in the metal wiring embedded in the dual damascene pattern, thereby improving contact resistance between the metal wiring and the conductive layer. The increase can be prevented, and the resistance and the RC delay of the metal wiring can be reduced.

As a result, the present invention has the effect of improving the characteristics and reliability of the semiconductor device having a metal wiring formed using a dual damascene process.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

The present invention described below provides a method of manufacturing a semiconductor device capable of preventing the via hole lower sidewall profile from having a negative slope due to excessive loss of the etch stop layer in forming the dual damascene pattern formed of the via hole and the trench. To this end, the present invention is a technical principle to form a sacrificial film on the sidewalls of the via-holes, and to remove the sacrificial film during the cleaning process that is performed after the trench forming process is completed.

2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 2A, the conductive film 32 is formed on the substrate 31 having a predetermined structure. In this case, the conductive layer 32 may include a word line, a bit line, a metal line, and an impurity region (eg, a source or drain region).

Next, the etch stop film 33 and the first insulating film 34 are sequentially formed on the conductive film 32. In this case, the etch stop film 33 serves to protect the conductive film 32 between subsequent dual damascene processes, and may be formed of a nitride film. As the nitride film, a silicon nitride film (Si ₃ N ₄ ) may be used.

The first insulating layer 34 is formed to form a dual damascene pattern, in particular, a via hole, and may be formed of an oxide layer. As the oxide film, a doped oxide film containing impurities in the film or an undoped oxide film containing no impurities in the film can be used. Specifically, as the doped oxide film, boron phosphorus silicate glass (BPSG), phosphorus silicate glass (PSG), boron silicalicate glass (BSG), etc. may be used, and as an undoped oxide film, a silicon oxide film (SiO ₂ ) or a teos (teso Ethyle Ortho Silicate (USG), Un-doped Silicate Glass (USG), High Density Plasma (HDP), Spin On Dielectric (SOD), Spin On Glass (SOG) and the like can be used.

In addition, the first insulating layer 34 may be formed to have a thickness in the range of 3000 kV to 7000 kV.

Next, a first hard mask pattern 35 is formed on the first insulating film 34. The first hard mask pattern 35 may be formed of a photo resist (Photh Resist, PR) or an amorphous carbon layer (ACL).

Next, the via hole 36 exposing the etch stop layer 33 on the conductive layer 32 is formed by etching the first insulating layer 34 using the first hard mask pattern 35 as an etch barrier. do. In this case, an etching process for forming the via hole 36 may be performed using a dry etching method, and a gas containing fluorine (F) may be used as an etching gas. In addition, an etching process may be performed by adding an inert gas (eg, argon gas (Ar)) and oxygen gas (O ₂ ) to the gas containing fluorine. Here, the fluorine-containing gas includes carbon fluoride gas (C _x F _y , where x and y are natural numbers except 0), and methane fluoride gas (C _x H _y F _z , x, y and z are natural numbers except 0). Can be used. For example, an etching process for forming the via hole 36 may be performed using a CF ₄ / Ar / O ₂ mixed gas.

Meanwhile, the etch stop layer 33 exposed in the process of forming the via hole 36 may be partially lost.

As shown in FIG. 2B, after removing the first hard mask pattern 38, the via hole 36 is buried, and a second insulating layer 37 covering the upper surface of the first insulating layer 34 is formed.

The second insulating layer 37 is formed to form a dual damascene pattern, especially a trench, and may be formed of an oxide film. At this time, the second insulating film 37 is preferably formed of a doped oxide film containing impurities in the film. As the doped oxide film, boron phosphorus silicate glass (BPSG), phosphorus silicate glass (PSG), boron silicalicate glass (BSG), or the like may be used.

Here, when both the first insulating film 34 and the second insulating film 37 are formed of a doped oxide film, it is preferable that the concentration of impurities contained in the second insulating film 37 is greater than that of the first insulating film 34. . This is to control the etching rate (or etching selectivity) between the first insulating film 34 and the second insulating film 37 with respect to the cleaning solution in the subsequent cleaning process. For reference, the etching rate for the cleaning solution is faster than the undoped oxide film. In the doped oxide film, the higher the concentration of impurities in the film, the faster the etching rate with respect to the cleaning solution.

In addition, the second insulating layer 37 may be formed to have a thickness in the range of 4000 kV to 8000 kV.

Next, a second hard mask pattern 38 having an opening line width W2 smaller than the first hard mask pattern 35 is formed on the second insulating layer 37. That is, the line width W2 of the opening of the second hard mask pattern 38 is smaller than the line width W1 of the via hole 36.

Next, the second insulating layer 37 is etched using the second hard mask pattern 38 as an etch barrier, and the second insulating layer 37 is left on the top surface of the first insulating layer 34 and the sidewall of the via hole 36. . In this case, the second insulating layer 37 remaining on the sidewall of the via hole 36 serves as a sacrificial layer for adjusting the sidewall profile of the via hole 36 through a subsequent cleaning process. Therefore, the thickness of the second insulating layer 37 remaining on the sidewalls of the via holes 36 may be adjusted in consideration of the thickness of the etch stop layer 33 that is excessively lost in the outer wall direction of the via holes 36 during the subsequent trench formation process. .

The etching process of etching the second insulating layer 37 using the second hard mask pattern 38 as an etch barrier may be performed using the same method as the etching process for forming the via hole 36. That is, the etching process may be performed by using a dry etching method, and the etching gas may be a gas containing fluorine or a mixed gas containing fluorine-containing gas, inert gas, and oxygen gas.

Meanwhile, a portion of the etch stop layer 33 exposed during the etching of the second insulating layer 37 may be lost.

As shown in FIG. 2C, after the second hard mask pattern 38 is removed, the line width W3 of the opening on the second insulating layer 37 is greater than that of the first and second hard mask patterns 35 and 38. 3 hard mask pattern 40 is formed. That is, the third hard mask pattern 40 having the line width W3 of the opening portion larger than the line width W1 of the via hole 36 is formed on the second insulating layer 37.

Next, the second insulating layer 37 is etched using the third hard mask pattern 40 as an etch barrier to form a trench 41 connected to the via hole 36, and the etching stop layer 33 is etched to etch the conductive layer. Expose the top surface of (32). In this case, a part of the second insulating layer 37 is left on the sidewall of the via hole 36 in the form of a spacer. Hereinafter, the reference numeral of the etched second insulating layer 37 is changed to '37A', and the reference numeral of the etched etch stop layer 33 is changed to '33A'.

The etching process for forming the trench 41 may be performed using the same method as the etching process for forming the via hole 36. Accordingly, the etching process for forming the trench 41 may be performed by using a dry etching method, and the etching gas containing fluorine or the etching gas containing fluorine, an inert gas, and an oxygen gas are mixed. Gas can be used.

Here, since the fluorine-containing gas is used in the etching process for forming the trench 41, the via hole (eg, due to the lack of etching selectivity between the etch stop layer 33 and the first and second insulating layers 34 and 37A) is formed. 36) The excessive loss of the etch stop film 33A occurs in the outer wall direction. As a result, the sidewall profile of the via hole 36 including the second insulating layer 37A and the etch stop layer 33A remaining on the sidewall has a negative slope. As such, when the sidewall profile of the via hole 36 has a negative slope, a problem arises in that a barrier metal film is abnormally deposited or a buried defect such as a void in a metal wiring occurs in a subsequent barrier metal film forming process.

In order to solve the problem caused by the sidewall profile of the via hole 36 described above, as shown in FIG. 2D, a second insulating film 37A remaining on the sidewall of the via hole 36 is removed by performing a cleaning process. Since the thickness of the second insulating layer 37A remaining on the sidewalls of the 36 is adjusted in consideration of the thickness of the etch stop layer 33A that is excessively lost during the formation of the trench 41, the thickness of the second insulating layer 37A remaining on the sidewalls of the via hole 36 remains. By removing the second insulating layer 37A, the sidewall profile of the via hole 36 including the etch stop layer 33A may be formed to have a vertical or positive slope.

The cleaning process for removing the second insulating film 37A remaining on the sidewalls of the via hole 36 may be performed by the RON cleaning process. Here, the RON washing step means that the R washing step, the O washing step, and the N washing step are sequentially performed. Specifically, the R cleaning process means a cleaning process using a cleaning solution containing sulfuric acid (H ₂ SO ₄ ), and serves to remove the third hard mask pattern 40 and organic by-products made of an amorphous carbon film. Do this. The O cleaning process means a cleaning process using a cleaning solution containing hydrofluoric acid (HF), and removes the second insulating layer 37A formed on the sidewalls of the via holes 36. At this time, since the first and second insulating layers 34 and 37A are formed of oxide films having different etching rates (or etching selectivity) with respect to the cleaning solution, that is, the cleaning solution containing hydrofluoric acid, loss of the first insulating film 34 is achieved. The second insulating layer 37A remaining on the sidewalls of the via hole 36 can be removed in a state of minimizing. In addition, since the second insulating layer 37A provides the sidewall of the trench 41, the line width of the trench 41 may increase during the O cleaning process. N cleaning process means a cleaning process using a cleaning solution containing ammonium hydroxide (NH ₄ OH), and serves to remove organic by-products and metallic residues.

Through the above-described process, the dual damascene pattern 42 including the via hole 36 and the trench 41 having the vertical or positive inclination of the sidewall profile may be formed.

As shown in FIG. 2E, the barrier metal film 43 is formed along the surface of the structure including the dual damascene pattern 42. In this case, since the sidewall profile of the via hole 36 has a vertical or positive slope, the barrier metal film 43 may be prevented from being deposited abnormally inside the dual damascene pattern 42.

Next, a metal material is deposited to fill the dual damascene pattern 42 on the barrier metal film 43. In this case, the metal material may be copper (Cu).

Next, the planarization process is performed until the upper surface of the second insulating layer 37 is exposed to form the metal wiring 44 embedded in the dual damascene pattern 42. In this case, the planarization process may be performed using chemical mechanical polishing (CMP) or etch back.

As described above, when the dual damascene pattern 42 including the via hole 36 and the trench 41 is formed, the trench 41 is formed by leaving the second insulating layer 37A on the sidewall of the via hole 36. Even if excessive loss of the etch stop layer 33A occurs during the process, the second insulating layer 37A remaining on the sidewalls of the via holes 36 is removed through the cleaning process, so that the sidewall profiles have vertical or positive slopes. There is an effect that can form. As a result, the barrier metal film 43 is abnormally deposited inside the dual damascene pattern 42, or a buried defect such as a void occurs in the metal wiring 44 embedded in the dual damascene pattern 42. It is possible to prevent the increase in contact resistance between the metal wiring 44 and the conductive film 32 and to reduce the resistance and RC delay of the metal wiring 44 by preventing the increase.

As a result, the present invention has the effect of improving the characteristics and reliability of the semiconductor device having the metal wiring 44 formed using the dual damascene process.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

1A and 1C are cross-sectional views illustrating a method for manufacturing copper wiring using a dual damascene process according to the related art.

2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* Description of symbols on the main parts of the drawings *

31 substrate 32 conductive film

33, 33A: etching stop film 34: first insulating film

35: first hard mask pattern 36: via hole

37, 37A: Second insulating film 38: Second hard mask pattern

40: third hard mask pattern 41: trench

42: dual damascene pattern 43: barrier metal film

44: metal wiring

Claims (14)

Sequentially forming an etch stop film and a first insulating film on the conductive film; Selectively etching the first insulating layer to form a via hole exposing the etch stop layer on the conductive layer; Forming a second insulating layer filling the via hole and covering an upper surface of the first insulating layer; Etching the second insulating layer by using a hard mask pattern having a line width of an opening smaller than the line width of the via hole as an etch barrier, and leaving the second insulating layer on an upper surface of the first insulating layer and sidewalls of the via hole; Etching the second insulating layer by using a hard mask pattern having a line width larger than that of the via hole as an etch barrier to form a trench connected to the via hole, and etching the etch stop layer to expose an upper surface of the conductive layer; And Performing a cleaning process to remove the second insulating layer remaining on the sidewalls of the via holes; Semiconductor device manufacturing method comprising a. The method of claim 1, Forming a barrier metal film on the via hole and the trench surface; And Forming a metal wiring on the barrier metal layer to fill the via hole and the trench A semiconductor device manufacturing method further comprising. The method of claim 2, The metal wiring comprises a copper (Cu) manufacturing method. The method of claim 1, The first and second insulating layers may include an oxide layer and the etch stop layer may include a nitride layer. The method of claim 4, wherein Forming the via hole and forming the trench, A method for manufacturing a semiconductor device using a gas containing fluorine (F). The method of claim 1, And the first insulating film is formed of a doped oxide film containing impurities in the film or an undoped oxide film containing no impurities in the film, and the second insulating film is formed of a doped oxide film. The method of claim 6, When the first and second insulating film is formed of a doped oxide film, And a concentration of impurities contained in the second insulating film is greater than that of impurities contained in the second insulating film. The method of claim 6, The undoped oxide film is a silicon oxide film (SiO ₂ ), TEOS (Tetra Ethyle Ortho Silicate), USG (Un-doped Silicate Glass), High Density Plasma (HDP), SOD (Spin On Dielectric), SOG (Spin) On Glass) method of manufacturing a semiconductor device. The method of claim 6, The doped oxide layer may include boron phosphorus silicate glass (BPSG), phosphorus silicate glass (PSG), and boron silicate glass (BSG). The method of claim 6, The said cleaning process is a semiconductor device manufacturing method which performs R cleaning process, O cleaning process, and N cleaning process sequentially. The method of claim 10, The R cleaning step is performed using a cleaning solution containing sulfuric acid (H ₂ SO ₄ ). The method of claim 10, The O cleaning step is performed using a cleaning solution containing hydrofluoric acid (HF). The method of claim 10, The N cleaning process is performed using a cleaning solution containing ammonium hydroxide (NH ₄ OH). The method of claim 1, And the conductive film includes a word line, a bit line, a metal wiring, and an impurity region.

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