KR100399906B1 - Method for forming contact hole of semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a contact hole of a semiconductor device is provided to improve the profile of the contact hole by using an interlayer dielectric with the same etching selectivity to an insulating layer. CONSTITUTION: The first BPSG layer(13), the first USG layer(14) and the second BPSG layer(15) are sequentially formed on a silicon substrate(11) with a junction region(12). The second USG layer(16) and the third BPSG layer(17) are sequentially formed on the second BPSG layer. A contact hole(20) is formed to expose the junction region by sequentially etching the third BPSG layer, the second USG layer, the second BPSG layer, the first USG layer and the first BPSG layer. Then, a native oxide is removed by cleaning the resultant structure.

Description

Contact hole formation method of semiconductor device

The present invention relates to a method of forming a contact hole, and more particularly, to a method of forming a contact hole in a semiconductor device capable of preventing unevenness of sidewalls of a contact hole due to a difference in etching ratios of multiple insulating layers.

In general, a plurality of metal layers are formed in accordance with high integration of semiconductor devices, and various types of insulating films are used to insulate the metal layers and planarize devices.

A method for forming a conventional contact hole will now be described in detail with reference to the accompanying drawings.

1A through 1D are cross-sectional views of a device for explaining a method of forming a contact hole in a conventional semiconductor device.

FIG. 1A shows a state in which the first insulating film 3, the first interlayer oxide film 4 and the second insulating film 5 are sequentially formed on the silicon substrate 1 on which the junction region 2 is formed. Although not shown in the drawings, the first insulating film 3 for the purpose of planarization of the device is formed, and then the first interlayer oxide film 4 for insulation between the conductors is formed, and the second insulating film 5 for the purpose of planarization of the device is continued. ) Is formed.

FIG. 1B shows a state in which the second interlayer oxide film 6 and the third insulating film 7 are sequentially formed on the second insulating film 5. Although not shown here, a second interlayer oxide film 6 is formed for insulation between conductors, and a third insulating film 7 is then formed for the purpose of planarization of the device. The first to second insulating films 3, 5, and 7 are made of BPSG.

The third insulating film 7, the second interlayer oxide film 6, the second insulating film 5, the first interlayer oxide film 4, and the first insulating film 3 are sequentially disposed so that the 1C or junction region 2 is exposed. After etching to form the contact hole 10, the cleaning process is performed by using a BOE in a ratio of 100: 1 for removing an oxide film formed naturally under the contact hole 10. At this time, the first and second interlayer oxide films 4 and 6 exposed to the sidewalls of the contact hole 10 are less etched due to the difference in etching ratios, thereby forming irregularities as shown by arrows A. FIG.

FIG. 1D shows a state in which the barrier metal layer 8 and the metal layer 9 are sequentially formed. At this time, due to the unevenness A of the second interlayer oxide film 4 formed on the sidewall of the contact hole 10, the metal layer 9 is not completely filled, and is shown by an arrow B at the bottom of the contact hole 10. Voids (voids) are formed.

This causes a problem that the reliability of the device is lowered due to a short circuit or an increase in contact resistance between the metal layer 9 and the junction region 2.

Therefore, in the present invention, the interlayer oxide film formed between the insulating films is formed in an in-situ method instead of the USG (Undoped Silicate Glass) film, or after forming the interlayer oxide film, the predetermined part is etched and removed to remove the above problems. It is an object of the present invention to provide a method for forming a contact hole in a semiconductor device capable of solving the problem.

In order to achieve the above object, a method of forming a contact hole includes sequentially forming a first insulating film, a first USG film, and a second insulating film on a silicon substrate on which a junction region is formed, and from the step, a second USG film on a second insulating film. And sequentially forming a third insulating film, and sequentially forming a contact hole by sequentially etching the third insulating film, the second USG film, the second insulating film, the first USG film, and the first insulating film so that the junction region is exposed from the step. And performing a cleaning process on the silicon substrate from the step to remove the naturally grown oxide film.

Another method of forming a contact hole for achieving the above object is to sequentially form a first insulating film and a first interlayer oxide film on a silicon substrate on which a junction region is formed, and etching a predetermined portion of the first interlayer oxide film from the step. Forming a second insulating film after the removal, and sequentially forming a second interlayer oxide film and a third insulating film on the second insulating film from the step; and forming a third insulating film and a third insulating film to expose the junction region. Forming a contact hole by sequentially etching the interlayer oxide film, the second insulating film, the first interlayer oxide film, and the first insulating film, and performing a cleaning process on the silicon substrate to remove the oxide film naturally formed below the contact hole. It is characterized by consisting of steps.

Hereinafter, a method of forming a contact hole according to a first embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2D are cross-sectional views of a device for explaining a method for forming a contact hole in a semiconductor device according to a first embodiment of the present invention.

2A shows a state in which the first insulating film 13, the first USG film 14, and the second insulating film 15 are sequentially formed on the silicon substrate 11 on which the junction region 12 is formed. Although not shown in the drawing, after the first insulating film 13 is formed for the purpose of planarization of the device, the first USG film 14 for the insulation between the conductors is formed to a thickness of 200 to 1000 mW, and the purpose of planarization of the device is in situ. A second insulating film 15 for forming is formed.

2B shows a state in which the second USG film 16 and the third insulating film 17 are sequentially formed on the second insulating film 15. Although not shown in the drawing, the second USG film 16 for insulation between the conductors is formed to a thickness of 200 to 1000 GPa, and the third insulation film 17 is formed for the purpose of planarizing the device in-situ. The first to third insulating films 13, 15, and 17 are made of BPSG.

The third insulating layer 17, the second USG layer 16, the second insulating layer 15, the first USG layer 14, and the first insulating layer 13 are sequentially etched to expose the second region C or the junction region 12. After the contact hole 20 is formed, the cleaning process is performed by using a BOE in a ratio of 100: 1 for removing an oxide film formed naturally under the contact hole 20. In this case, the first to third insulating films 13, 15 and 17, the first USG film, and the second USG film 14 and 16 have the same etching ratio, so that unevenness occurs in the sidewall of the contact hole 20 due to the difference in etching ratio. It doesn't work.

2D shows a state in which the barrier metal layer 18 and the metal layer 19 are sequentially formed. In the first embodiment according to the present invention, by using the USG film having the same etching selectivity as the insulating film, the good metal layer 19 can be formed by suppressing the generation of unevenness on the sidewall of the contact hole 20.

Hereinafter, a method of forming a contact hole according to a second embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3E are cross-sectional views of a device for explaining a method for forming a contact hole in a semiconductor device according to a second embodiment of the present invention.

3A shows a state in which the first insulating film 23 and the first interlayer oxide film 24 are sequentially formed on the silicon substrate 21 on which the junction region 22 is formed. Although not shown in the drawing, the first insulating layer 23 is formed for the purpose of planarization of the device, and then the first interlayer oxide layer 24 is formed to insulate the conductors.

3B shows a state in which a second insulating film 25 is formed after removing a predetermined portion of the first interlayer oxide film 24 by an etching process using a photosensitive film pattern (not shown). The etching process may use a florin-based plasma, or may use BOE and HF. At this time, the ratio of BOE used is NH ₄ F HF is 300: 1 to 9: 1, the ratio of HF is pure water: HF is 100: 1 to 50: 1. The second insulating film 25 is formed for the purpose of planarization of the device.

3C shows a state in which the second interlayer oxide film 26 and the third insulating film 27 are sequentially formed on the second insulating film 25. Although not shown here, a second interlayer oxide film 26 is formed for insulation between conductors, and a third insulating film 27 is formed for the purpose of planarization of the device. The first to third insulating films 23, 25, and 27 are made of BPSG.

The third insulating film 27, the second interlayer oxide film 26, the second insulating film 25, the first interlayer oxide film 24, and the first insulating film 23 are sequentially formed to expose the 3D or junction regions 22. After etching to form the contact hole 30, the etching process is performed by using a BOE of 100: 1 ratio for removing the oxide film formed naturally in the lower portion of the contact hole (30). In this case, since the first interlayer oxide film 24 is not exposed to the sidewall of the contact hole 30, irregularities are not generated in the sidewall of the contact hole 30.

3E shows a state in which the barrier metal layer 28 and the metal layer 29 are sequentially formed. In the second embodiment according to the present invention, by removing the first interlayer thin film formed on the insulating film by a predetermined etching process, the contact hole 30 is prevented from being exposed to the sidewall of the contact hole 30 when the contact hole 30 is formed. A good metal layer 29 can be formed by preventing the formation of unevenness on the sidewalls of the substrate.

As described above, according to the present invention, by using an interlayer oxide film having the same etching selectivity with respect to the insulating film, it is possible to prevent unevenness generated on the sidewalls of the contact hole due to the etching selectivity when removing the natural oxide film after forming the contact hole or when forming the interlayer oxide film as the contact hole. There is an excellent effect of forming a good contact hole by etching and removing a predetermined portion before forming the contact hole so as not to be exposed to the contact hole sidewall.

1A to 1D are cross-sectional views of a device for explaining a method for forming a contact hole in a conventional semiconductor device.

2A through 2D are cross-sectional views of a device for explaining a method for forming a contact hole in a semiconductor device according to a first embodiment of the present invention.

3A through 3E are cross-sectional views of a device for explaining a method for forming a contact hole in a semiconductor device according to a second embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

1, 11 and 21: silicon substrate 2, 12 and 22: junction area

3, 13, and 23: first insulating film 4 and 24: first interlayer oxide film

5, 15, and 25: second insulating film 6 and 26: second interlayer oxide film

7, 17 and 27: third insulating film 8, 18 and 28: barrier metal layer

9,19 and 29: metal layers 10,20 and 30: contact holes

14 and 16: 1st and 2nd USG film A: unevenness

B: void (void)

Claims (9)

Sequentially forming a first BPSG film, a first USG film, and a second BPSG film on a silicon substrate on which a junction region is formed; Sequentially forming a second USG film and a third BPSG film on the second BPSG film from the step; Forming a contact hole by sequentially etching the third BPSG film, the second USG film, the second BPSG film, the first USG film, and the first BPSG film to expose the junction region from the step; And removing the naturally grown oxide film by performing a cleaning process on the silicon substrate from the above step. The method of claim 1, And wherein the first USG film and the second BPSG film, and the second USG film and the third BPSG film are formed in situ, respectively. The method according to claim 1 or 2, Wherein the first and second USG films are formed to a thickness of 200 to 1000 microns. The method of claim 1, The method of forming a contact hole in a semiconductor device, characterized in that the cleaning step is performed using a BOE of 100: 1 ratio. In the method of forming a contact hole of a semiconductor device, Sequentially forming a first BPSG film and a first interlayer oxide film on the silicon substrate where the junction region is formed; Removing a predetermined portion of the first interlayer oxide film by an etching process from the step, and forming a second insulating film; Sequentially forming a second interlayer oxide film and a third BPSG film on the second BPSG film from the step; Forming a contact hole by sequentially etching the third BPSG film, the second interlayer oxide film, the second BPSG film, and the first BPSG film to expose the junction region from the step; And removing the oxide film formed naturally under the contact hole by performing a cleaning process on the silicon substrate from the step. The method of claim 5, The etching process is a contact hole forming method of a semiconductor device, characterized in that carried out using a plasma using a gas of Florin series. The method of claim 5, The etching process is a contact hole forming method of a semiconductor device, characterized in that carried out using BOE and HF. The method of claim 7, wherein The ratio of the BOE is NH ₄ F: HF is 300: 1 to 9: 1, the ratio of HF is pure water: HF is 100: 1 to 50: 1 method for forming a contact hole in a semiconductor device. The method of claim 5, The method of forming a contact hole in a semiconductor device, characterized in that the cleaning step is performed using a BOE of 100: 1 ratio.