CN113130621B - 具有结晶硅和富陷阱多晶硅层的晶片 - Google Patents

具有结晶硅和富陷阱多晶硅层的晶片 Download PDF

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CN113130621B
CN113130621B CN202011472909.9A CN202011472909A CN113130621B CN 113130621 B CN113130621 B CN 113130621B CN 202011472909 A CN202011472909 A CN 202011472909A CN 113130621 B CN113130621 B CN 113130621B
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crystalline semiconductor
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CN113130621A (zh
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A·K·斯塔珀
S·M·尚克
J·J·派卡里克
V·贾因
J·J·埃利斯-莫纳甘
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Abstract

本公开涉及半导体结构，更具体地涉及具有结晶硅和富陷阱多晶硅层的晶片及制造方法。该结构包括：绝缘体上半导体(SOI)晶片，其由下结晶半导体层、位于下结晶半导体层上方的多晶硅层、位于多晶硅层上方的上结晶半导体层、位于上结晶半导体层上方的掩埋绝缘体层，以及位于掩埋绝缘体层上方的顶部结晶半导体层组成。

Description

具有结晶硅和富陷阱多晶硅层的晶片
技术领域
本公开涉及半导体结构，更具体地涉及具有结晶硅和富陷阱多晶硅区的晶片及制造方法。
背景技术
体硅衬底比绝缘体上硅(SOI)衬底便宜。通常，SOI衬底包括薄的硅器件层、处理衬底，以及使器件层与处理衬底物理分隔并电隔离的薄掩埋氧化物(BOX)层。
与内置在体硅衬底中的可比较器件相比，使用SOI技术制造的器件可以表现出某些性能改进。例如，与SOI衬底形成对比，体硅衬底的特征在于与谐波生成的器件隔离差。高电阻率晶片用于大约1至10GHz的射频应用，以减少衬底射频损耗。
发明内容
在本公开的一方面，一种结构包括：绝缘体上半导体(SOI)晶片，所述晶片包括下结晶半导体层、位于所述下结晶半导体层上方的多晶硅层、位于所述多晶硅层上方的上结晶半导体层、位于所述上结晶半导体层上方的掩埋绝缘体层，以及位于所述掩埋绝缘体层上方的顶部结晶半导体层。
在本公开的一方面，一种结构包括：晶片，其由富陷阱多晶硅层和位于所述富陷阱多晶硅层上方的结晶半导体材料组成；掩埋氧化物层，其位于所述结晶半导体材料的表面上；以及结晶半导体层，其位于所述掩埋氧化物层上方。
在本公开的一方面，一种方法包括：在晶片中的单晶部下方形成富陷阱部；在所述单晶部上方形成绝缘体层，所述单晶部在所述富陷阱部和所述绝缘体层之间提供隔离；以及在所述绝缘体层上方形成半导体层。
附图说明
借助本公开的示例性实施例的非限制性示例，参考所提到的多个附图，在下面的详细说明中描述了本公开。
图1示出了根据本公开的方面的晶片。
图2示出了根据本公开的方面的晶片中的非晶区域以及其它特征和相应的制造工艺。
图3示出了根据本公开的方面的晶片的再结晶部以及其它特征和相应的制造工艺。
图4示出了根据本公开的方面的绝缘体上衬底技术的形成以及其它特征和相应的制造工艺。
图5示出了根据本公开的方面的其中单晶衬底与多晶硅层分隔的绝缘体上衬底技术以及其它特征和相应的制造工艺。
图6至8示出了根据本公开的其它方面的晶片和相应的制造工艺。
具体实施方式
本公开涉及半导体结构，更具体地涉及具有结晶硅和富陷阱多晶硅层的晶片及制造方法。更具体地，本公开提供了一种具有使富陷阱多晶硅层与掩埋氧化物层分隔的结晶硅的绝缘体上硅(SOI)晶片及制造方法。有利地，除了其它优点之外，本公开为场效应晶体管提供了改善的线性。
在实施例中，晶片是绝缘体上衬底(SOI)技术。该晶片包括薄硅层、掩埋氧化物层和具有富陷阱多晶硅层的单晶硅处理晶片(handle wafer)。薄硅层可以是单晶材料，例如单晶硅。硅层和单晶硅也可以由其它单晶衬底材料组成。富陷阱多晶硅层位于掩埋氧化物层下方并与之分隔。在进一步的实施例中，位于掩埋氧化物层下面的结晶硅可用于FET或NPN体接触，并且富陷阱多晶硅层将提供改善的线性。
在更具体的实施例中，该结构包括衬底和富陷阱层。在富陷阱层上方提供第一结晶层，并在第一结晶层上方提供电介质层(例如，掩埋氧化物层)。第一结晶层将在富陷阱层和电介质层之间提供分隔。在掩埋电介质层上方提供第二结晶层，从而形成其中富陷阱层与掩埋氧化物层分隔的SOI晶片。在实施例中，第一结晶层和第二结晶层可以是单晶硅，并且掩埋电介质层可以是氧化物材料。并且，在实施例中，富陷阱层包含多晶硅晶体材料。
可以使用许多不同的工具以多种方式制造本公开的结构。但是，一般而言，这些方法和工具用于形成尺寸为微米和纳米级的结构。用于制造本公开的结构的方法(即，技术)已经从集成电路(IC)技术中采用。例如，该结构被构建在晶片上，并且通过在晶片顶部执行光刻工艺而图案化的材料膜实现。特别地，结构的制造使用三个基本构建块：(i)在衬底上沉积材料薄膜，(ii)通过光刻成像在膜顶部上施加图案化的掩模，以及(iii)对掩模选择性地蚀刻膜。
图1示出了根据本公开的方面的晶片。更具体地，图1的结构10包括用作前端模块的处理晶片12，在示例性实施例中，该处理晶片具有用于RF器件应用的高电阻率。例如，晶片12的电阻率可以是高电阻率，例如但不限于1000ohm-cm或更大。晶片12可以由单晶材料12a组成。例如，单晶材料12a可以是单晶Si材料。在另外的实施例中，单晶材料12a可以是其它单晶半导体材料，例如SiGe、SiC、Ge等，并且可以可选地接合至玻璃或蓝宝石(也由参考标号12a表示)。可以在晶片12上形成可选的氧化物材料层14。在实施例中，作为示例，可选的氧化物材料14可具有大约50nm的厚度，可以通过热氧化形成，例如在炉中使用1000℃氧化而形成。
图2示出了延伸到晶片12内的非晶区16。在实施例中，非晶区16在晶片12的表面上由例如非晶Si组成，并且延伸到晶片的一定深度内。非晶区16通过使用注入工艺对衬底12进行非晶化来制造，该注入工艺低于防止晶片12(例如单晶材料12a)再结晶的临界剂量。在实施例中，非晶区16可以通过涂层(例如氧化物材料14)或在晶片12的裸表面上被注入。在实施例中，注入工艺可以是采用1E14至1.5E15剂量水平的氩注入工艺，并且在更优选的实施例中，采用1.25E15的剂量水平。注入可以使用氩或其它注入元素，例如，诸如其它稀有气体之类的其它惰性气体，如氙、锗、氮或氧等。在实施例中，非晶区16的表面上具有数十纳米厚的结晶硅层，其在随后的退火步骤期间形成用于非晶硅再结晶的籽晶。
在图3中，对晶片12进行快速热退火处理以使晶片12的表面再结晶，从而在晶片12的表面形成单晶区12b。快速热退火处理会在再结晶区(层)12b下方留下一个或多个多晶硅或富陷阱多晶硅层18。本领域技术人员应该理解，富陷阱多晶硅层18将有利地提供改善的线性，并且能够钉扎回栅偏置。快速热退火处理可以在0到10秒内达到900℃至1150℃之间的温度。在实施例中，热退火处理是1000℃下的尖峰退火(例如0秒)。在实施例中，多晶硅或富陷阱多晶硅层的厚度为10nm至500nm，并且在一个实施例中为50nm。
如图4所示，示出了具有图3的晶片的硅晶片120。硅晶片120包括硅层180，硅层180具有例如通过1000℃的热氧化形成为0.1至5微米厚，并且在一个实施例中，形成为0.4微米厚(尽管本文可以构想其它尺寸)的氧化的下表面层20。晶片120包括氢注入层100，如本领域中已知的，其比下表面低数十或数百纳米。如箭头所示，晶片120被接合至晶片12。然后，使用例如本领域公知的SmartcutTM处理沿着氢注入区100分离晶片120，接着执行本领域公知的平面化处理，从而产生图5中代表性地示出的结构。用于形成晶片的工艺在例如美国专利No.5,374,564中进一步示出，该专利的全部内容通过引用并入本文中。
参考图5，应当理解，绝缘体层14和20将形成如图5所示的完成的晶片中的掩埋氧化物层(BOX)。尽管在图中分别进行了绘制，但是氧化物14和20将在层20的氧化步骤期间合并成单个氧化物层。替代地，可以省略氧化物层14，仅使用氧化物层20来形成BOX层。如果是这种情况，则可以在晶片(例如，供体晶片)120或晶片(例如，受体晶片)12上形成氧化物层20。
此外，如图5所示，在沿着氢注入区100分离晶片120之后，该晶片120将形成现在被接合至绝缘体层14、20的衬底22，例如，这形成SOI技术的上部。衬底22可以是单晶Si或本文中作为示例描述的其它合适的单晶半导体材料。以这种方式，晶片现在是绝缘体上硅(SOI)衬底，其中富陷阱多晶硅层18位于再结晶区12b下方，并且通过再结晶区12b与氧化物层14/20分隔。即，再结晶区12b是中间层，其防止富陷阱多晶硅层18与绝缘体层20(例如BOX)之间直接接触。在富陷阱多晶硅层18下方还有结晶底层，例如单晶Si层12a。
图6至8示出了根据本公开的其它方面的晶片和相应的制造工艺，其中富陷阱多晶硅区18、18a在区域18a中延伸到处理晶片12表面。更具体地，图6所示的结构10a包括位于晶片12上方的图案化材料24。在实施例中，图案化材料24是在注入处理之前沉积和图案化的氧化物材料(如箭头所示)。图案化是常规的光刻和蚀刻工艺。例如，在沉积氧化物材料24之后，在氧化物材料24上方形成的抗蚀剂被暴露于能量(光)以形成图案(开口)。将使用具有选择性化学的蚀刻工艺(例如反应离子蚀刻(RIE))来通过开口去除氧化物材料，从而留下图6所示的氧化物材料24的图案。然后可以通过常规的氧灰化处理或其它公知的剥除剂去除抗蚀剂。在图案化处理之后，制造方法继续执行本文已经描述的注入处理，不同之处在于氧化物材料24将阻挡部分注入物进入晶片12中。
在图7中，通过使用选择性化学的常规蚀刻工艺去除氧化物材料。对晶片12进行快速热退火处理以使晶片12的表面再结晶，从而在晶片12的表面形成单晶区12b，并在单晶区12b的下方和邻近该单晶区12b形成富陷阱多晶硅层18a。
在该实施例中，快速热退火处理将留下延伸到再结晶区12b的表面的富陷阱多晶硅延伸区18a，其图案对应于图案化的氧化物材料的图案。富陷阱多晶硅延伸区18a也被单晶区12b围绕，其中一部分与掩埋氧化物层20接触(见图8)，其余部分通过单晶区12b与掩埋氧化物层20隔开。快速热退火处理可以在0到10秒内达到900℃至1150℃之间的温度。在实施例中，热退火处理是1000℃下的尖峰退火(例如0秒)。
如图8所示，绝缘体或电介质层(例如，氧化物)20被沉积在晶片12上方，更具体地，沉积在再结晶区12b和延伸到再结晶区12b的表面的富陷阱多晶硅层18a上方。层20可以通过任何合适的常规工艺形成，例如注氧隔离(SIMOX)、沉积、热氧化和/或其它合适的工艺。
仍然参考图8，衬底22沉积在层20上方。衬底22可以是单晶Si或本文描述的其它合适的单晶衬底。在实施例中，衬底22可以被直接接合至氧化物层20(例如BOX)，或者可以先被接合至单独的氧化物材料，该氧化物材料又使用晶片接合和/或本文描述的其它合适的方法而被接合至层20。以此方式，晶片现在是绝缘体上硅(SOI)衬底，其中富陷阱多晶硅层18、18a位于再结晶区12b下方以及被再结晶区12b围绕并且通过再结晶区12b与氧化物层18部分地隔开。
本文描述的晶片可用于片上系统(SoC)技术中。本领域技术人员应该理解，SoC是将电子系统的所有部件集成在单个芯片或衬底上的集成电路(也称为“芯片”)。由于部件被集成在单个衬底上，因此与具有等效功能的多芯片设计相比，SoC消耗的功率少得多，占用的面积也小得多。因此，SoC正成为移动计算(例如，智能电话)和边缘计算市场中的主导力。SoC也常用于嵌入式系统和物联网中。
上述方法用于集成电路芯片的制造。所得到的集成电路芯片可以由制造商以原始晶片形式(即，作为具有多个未封装芯片的单个晶片)，作为裸芯或以封装形式分发。在后一种情况下，芯片以单芯片封装(例如塑料载体，其引线固定到主板或其它更高级别的载体)或多芯片封装(例如陶瓷载体，其具有表面互连和/或掩埋互连)的形式被安装。在任何情况下，芯片然后与其它芯片、分立电路元件和/或其它信号处理器件集成，作为(a)中间产品(例如主板)或(b)最终产品的一部分。最终产品可以是包括集成电路芯片的任何产品，从玩具和其它低端应用到具有显示器、键盘或其它输入设备以及中央处理器的高级计算机产品。
本公开的各种实施例的描述已经出于说明的目的给出，但并非旨在是穷举的或限于所公开的实施例。在不脱离所描述的实施例的范围和精神的情况下，许多修改和变化对于本领域普通技术人员将是显而易见的。本文中所用术语的选择旨在最好地解释各实施例的原理、实际应用或对市场中发现的技术的技术改进，或者使本技术领域的其他普通技术人员能够理解本文公开的实施例。

Claims (20)

1.一种半导体结构，包括绝缘体上半导体(SOI)晶片，所述晶片包括下结晶半导体层、位于所述下结晶半导体层上方的多晶硅层、位于所述多晶硅层上方的上结晶半导体层、位于所述上结晶半导体层上方的掩埋绝缘体层，以及位于所述掩埋绝缘体层上方的顶部结晶半导体层，其中，所述上结晶半导体层是单晶半导体层。
2.根据权利要求1所述的结构，其中所述掩埋绝缘体层是掩埋氧化物层，所述下结晶半导体层是单晶硅，所述上结晶半导体层是单晶硅。
3.根据权利要求2所述的结构，其中所述单晶硅是高电阻率硅。
4.根据权利要求3所述的结构，其中所述高电阻率硅是＞1000ohm-cm的。
5.根据权利要求1所述的结构，其中所述多晶硅层是富陷阱的。
6.根据权利要求1所述的结构，其中所述上结晶半导体层使所述多晶硅层与所述掩埋绝缘体层分隔。
7.根据权利要求1所述的结构，其中所述下结晶半导体层和所述上结晶半导体层是处理晶片，并且所述多晶硅层被嵌入在所述处理晶片内且位于所述下结晶半导体层和所述上结晶半导体层之间。
8.根据权利要求1所述的结构，其中所述多晶硅层包括延伸到所述上结晶半导体层的表面并与所述掩埋绝缘体层的一部分接触的延伸区域。
9.一种半导体结构，包括：
晶片，其由富陷阱多晶硅层和位于所述富陷阱多晶硅层上方的结晶半导体材料组成；
掩埋氧化物层，其位于所述结晶半导体材料的表面上；以及
结晶半导体层，其位于所述掩埋氧化物层上方，
其中，所述结晶半导体材料是单晶半导体材料。
10.根据权利要求9所述的结构，其中位于所述富陷阱多晶硅层上方的所述结晶半导体材料使所述富陷阱多晶硅层与所述掩埋氧化物层隔离。
11.根据权利要求9所述的结构，其中所述结晶半导体层是单晶材料。
12.根据权利要求11所述的结构，其中所述单晶材料是单晶硅基材料。
13.根据权利要求12所述的结构，其中所述晶片、所述掩埋氧化物层和所述结晶半导体层是绝缘体上半导体(SOI)技术。
14.根据权利要求12所述的结构，其中所述晶片是处理晶片，并且所述富陷阱多晶硅层被嵌入在所述处理晶片内。
15.根据权利要求14所述的结构，其中所述单晶半导体材料位于所述富陷阱多晶硅层的上方和下方。
16.根据权利要求15所述的结构，其中所述富陷阱多晶硅层包括延伸到其上方的所述单晶半导体材料的表面的延伸部并与所述掩埋氧化物层的一部分接触。
17.根据权利要求16所述的结构，其中所述富陷阱多晶硅层的所述延伸部在其侧面被所述晶片的所述单晶半导体材料围绕。
18.一种制造半导体结构的方法，包括：
在晶片中的单晶部下方形成富陷阱部；
在所述单晶部上方形成绝缘体层，所述单晶部在所述富陷阱部和所述绝缘体层之间提供分隔；以及
在所述绝缘体层上方形成半导体层。
19.根据权利要求18所述的方法，其中形成所述富陷阱部和所述单晶部包括使所述单晶部非晶化，然后进行快速热退火处理。
20.根据权利要求19所述的方法，其中所述非晶化是使用低于防止晶片再结晶的临界剂量的惰性气体的注入处理，并且所述快速热退火处理使所述晶片再结晶以在所述富陷阱部上方形成所述单晶部。
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