CN116133433A - 三阱区内的电熔丝和三阱区上的栅极结构 - Google Patents
三阱区内的电熔丝和三阱区上的栅极结构 Download PDFInfo
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Abstract
本公开涉及半导体结构,更具体地涉及位于三阱上的电熔丝和栅极结构及制造方法。该结构包括:衬底,其包括有界区域;栅极结构,其形成在有界区域内;以及电熔丝,其形成在有界区域内并电连接到栅极结构。
Description
技术领域
本公开涉及半导体结构,更具体地涉及三阱区上的电熔丝(eFuse)和栅极结构及制造方法。
背景技术
电熔丝(电子熔丝)是一种用于计算机芯片的微观熔丝。电熔丝允许对芯片进行动态实时重新编程。例如,通过使用一组电熔丝,芯片制造商可以允许芯片上的电路在其运行时变化。
电熔丝可以由硅或金属迹线制成。这些迹线比芯片上的其他迹线弱,从而在这些其他迹线失效之前失效。以这种方式,例如,通过电迁移,电熔丝可以熔断,并且可以在操作期间对芯片进行编程。然而,电熔丝需要大的芯片面积,特别是在仅在三阱区中提供FET的技术中。例如,在这种布局中,电熔丝最多可以使用12%的芯片面积。
发明内容
在本公开的一方面,一种结构包括:衬底,其包括有界区域;栅极结构,其形成在所述有界区域内;以及电熔丝,其形成在所述有界区域内并电连接到所述栅极结构。
在本公开的一方面,一种结构包括:衬底,其包括由阱界定的区域;至少一个浅沟槽隔离结构,其位于由所述阱界定的所述区域内;栅极结构,其位于由所述阱界定的所述区域上方;以及电熔丝,其电连接到所述栅极结构并位于由所述阱界定的所述区域内的所述至少一个浅沟槽隔离结构上方。
在本公开的一方面,一种方法包括:在衬底中形成由阱包围的有界区域;在所述有界区域内形成至少一个浅沟槽隔离结构;在所述有界区域上方形成栅极结构;以及形成电连接到所述栅极结构的电熔丝,所述电熔丝形成在所述有界区域内的所述至少一个浅沟槽隔离结构上方。
附图说明
在下面的详细描述中,借助本公开的示例性实施例的非限制性示例,参考所提到的多个附图来描述本公开。
图1示出了根据本公开的一些方面的除其他特征之外的三阱区以及相应的制造工艺。
图2示出了根据本公开的一些方面的除其他特征之外的三阱区上方的电熔丝以及相应的制造工艺。
图3示出了根据本公开的一些方面的除其他特征之外的三阱区上方的电熔丝上的硅化物以及相应的制造工艺。
图4示出了根据本公开的一些方面的除其他特征之外的到三阱区上方的电熔丝的接触以及相应的制造工艺。
图5示出了除其他特征之外的三阱区上方的栅极结构和电熔丝的俯视图。
图6示出了根据本公开的附加方面的除其他特征之外的掩埋非晶半导体层上方的电熔丝以及相应的制造工艺。
具体实施方式
本公开涉及半导体结构,更具体地涉及三阱区上方的栅极结构和电熔丝及制造方法。更具体地,电熔丝结构包括与编程场效应晶体管(FET)相结合的三阱区(例如,环)内的硅化物多晶硅电熔丝。有利地,三阱区内的硅化物多晶硅电熔丝可以在电熔丝阵列基元(array cell)中提供显著的面积节省。例如,与已知的电熔丝布局相比,在三阱区内使用硅化物多晶硅电熔丝可以在8位电熔丝阵列基元中节省58%的面积。
在更具体的实施例中,可以在具有编程FET的三阱区顶部上设置硅化多晶硅电熔丝;也就是,硅化多晶硅电熔丝可以与编程FET共用相同的三阱区。在另外的实施例中,电熔丝、编程FET和束缚二极管(tie down diode)可以共用相同的三阱区。束缚二极管可以防止在制造过程中发生并且可能导致阱和/或栅极损坏的等离子体充电。还可以设想,在相同的三阱区中为电熔丝阵列提供所有平行的位基元(bit cell)。在另外的实施例中,可以用掩埋多晶硅层替代三阱区。通过将电熔丝和FET分组在相同的三阱内(或掩埋多晶硅材料上方),现在可以实现紧凑的设计布局。
本公开的电熔丝可以使用多种不同的工具,以多种方式来制造。然而,通常,使用方法和工具来形成具有微米和纳米级尺度(dimension)的结构。已经根据集成电路(IC)技术采用了用于制造本公开的电熔丝的方法(即,技术)。例如,这些结构建立在晶片上,并在晶片顶部上借助光刻工艺图案化的材料膜中实现。特别地,电熔丝的制造使用三个基本构造块:(i)在衬底上沉积材料薄膜;(ii)通过光刻成像在膜顶部上施加图案化掩模;以及(iii)对掩模有选择性地蚀刻膜。
图1示出了根据本公开的一些方面的除其他特征之外的三阱区以及相应的制造工艺。更具体地,图1的结构10包括衬底12。在实施例中,衬底12包括体衬底,其包括任何合适的晶体取向(例如,(100)、(110)、(111)或(001)晶体取向)。衬底12可以由任何合适的材料组成,包括但不限于Si、SiGe、SiGeC、SiC、GaAs、InAs、InP和其他III/V或II/VI族化合物半导体。
图1进一步示出了衬底12中的三阱区15。三阱区15包括阱14、16、18。在实施例中,阱14是深N阱,阱16是P阱,阱18是围绕P阱16(提供隔离阱)的N阱。在实施例中,N阱14、18掺杂有n型掺杂剂,例如砷(As)、磷(P)和Sb,以及其他合适的示例;而P阱掺杂有p型掺杂剂,例如硼(B)。
阱14、16、18可以通过在衬底12中引入掺杂剂来形成,例如使用离子注入工艺。在实施例中,图案化的注入掩模可用于限定为注入工艺而暴露的选定区域。注入掩模可以包括光敏材料层,例如有机光致抗蚀剂层,其通过旋涂工艺施加,被预烘烤,暴露于通过光掩模投射的光下,曝光后烘烤,并用化学显影剂进行显影。注入掩模具有足以阻止掩蔽区域接收一定剂量的注入离子的厚度和阻止能力。
仍参考图1,浅沟槽隔离结构20、20a形成在衬底12中,并且优选地形成在阱16、18中以及它们的结处。在实施例中,浅沟槽隔离结构20a可以完全位于阱16内。浅沟槽隔离结构20、20a可以使用常规光刻、蚀刻和沉积工艺形成。例如,将形成在衬底12上方的抗蚀剂暴露于能量(光)下以形成图案(开口)。使用具有选择性化学作用的蚀刻工艺,例如反应离子蚀刻(RIE),将图案从抗蚀剂转移到衬底12,以通过抗蚀剂的开口在衬底12中形成一个或多个沟槽。在通过常规氧灰化工艺或其他已知剥离剂去除抗蚀剂之后,可以通过任何常规沉积工艺,例如化学气相沉积(CVD)工艺,沉积绝缘体材料。衬底12的表面上的任何残留材料可以通过常规化学机械抛光(CMP)工艺去除。
图2示出了除其他特征之外的三阱区15上方的电熔丝24和栅极结构22以及相应的制造工艺。例如,电熔丝和栅极结构22完全界定在阱18内、阱14上方和阱16内和/或上方。在实施例中,栅极结构22和电熔丝24二者都可以包括使用已知的沉积和图案化工艺,例如光刻和蚀刻工艺,沉积和图案化的多晶硅材料。
在实施例中,栅极结构22可以通过先栅极工艺形成。在先栅极工艺中,例如,栅极材料22a,例如栅极电介质材料和多晶硅材料,被沉积在阱16上方的衬底12上,随后被执行图案化工艺,例如光刻和蚀刻工艺。用于栅极结构22的多晶硅材料的沉积也可用于电熔丝24。例如,可以使用CVD工艺来沉积多晶硅材料。在实施例中,栅极电介质材料可以是低k栅极电介质材料,例如氧化物。在其中在浅沟槽隔离结构20a上形成电熔丝24并且在阱16上方形成栅极结构22的图案化工艺之后,可以在图案化的栅极结构22以及可选地在电熔丝24的侧壁上形成侧壁间隔物(spacer)22b。侧壁间隔物22b可以是通过任何已知的沉积工艺形成的氮化物或氧化物材料(或其组合),然后被执行各向异性蚀刻工艺。
图3示出了除其他特征之外的三阱区15上方的扩散区26、26a和电熔丝24上的硅化物接触28。在形成硅化物接触28之前,可以使用本领域技术人员已知的常规离子注入工艺在阱16中形成扩散区26、26a,从而无需进一步解释即可完全理解本公开。在实施例中,扩散区26a可以是在后续处理步骤期间防止等离子体充电的束缚二极管。此外,扩散区26可以是通过常规注入工艺形成的源极/漏极区,包括在沉积侧壁间隔物材料之后顺序地形成的晕圈和延伸注入物。
硅化物接触28可以通过常规硅化物工艺形成。例如,硅化物工艺开始于在完全形成和图案化的半导体器件(例如,扩散区26、26a、电熔丝24和栅极结构22(在此截面图中未示出))上方沉积薄过渡金属层,例如镍、钴或钛。在沉积材料之后,加热结构,允许过渡金属与器件的有源区中暴露的半导体材料(Si或本文所述的其他半导体材料)发生反应,形成低电阻过渡金属硅化物。在反应之后,通过化学蚀刻去除任何剩余的过渡金属,在器件22的有源区中和电熔丝24上留下硅化物接触28。
图4示出了除其他特征之外的到三阱区15上方的电熔丝24和其他部件的接触。更具体地,接触30a-30e(例如,金属化特征)形成在扩散区26、26a和电熔丝24(以及栅极结构22的栅极材料22a(在此截面图中未示出))上。在实施例中,接触30a-30e可以通过常规工艺形成。例如,可通过常规沉积工艺(例如,CVD)沉积层级间(interlevel)电介质材料34的堆叠,随后执行光刻和蚀刻工艺以形成暴露硅化物接触28(或硅化物接触28上的金属特征)的沟槽。在层级间电介质材料34中形成沟槽之后,可以通过任何常规沉积工艺,例如CVD工艺,来沉积导电材料,以形成接触30a-30e。层级间电介质材料34的表面上的任何残留材料可以通过常规化学机械抛光(CMP)工艺去除。
图4还示出了另一金属化特征,例如将电熔丝24连接到栅极结构22的布线结构32。在实施例中,布线结构32可以通过类似于接触30a-30c的常规CMOS工艺形成,因此,此处不需要进一步解释即可完全理解本公开。在实施例中,布线结构32与栅极结构22的扩散区26的接触30a和电熔丝24的接触30b接触。以此方式,电熔丝24电连接到栅极结构22,例如编程FET。
图5示出了除其他特征之外的三阱区15(由N阱18限定)的隔离阱(例如P阱16)上方的电熔丝24的俯视图。更具体地,图5示出了电熔丝24、栅极结构22和扩散区26a(例如,束缚二极管),其位于由N阱18(例如,N阱环)限定的单个三阱区15上方并共用该单个三阱区15。如图5进一步所示,栅极结构22可以是三阱区15上方的多指FET(或平行(parallel)位基元),通过互连32连接到电熔丝24。此外,电熔丝24可以设置在三阱区15内的浅沟槽隔离结构24上方。
图6示出了衬底12中由P阱区38、38a界定的掩埋非晶半导体层36上方的电熔丝24。在该实施例中,可以消除阱14、16。在实施例中,例如,掩埋非晶半导体层36可以通过使用注入工艺使衬底12非晶化来制造,此工艺使用注入掩模来保护用于形成P阱区38、38a的衬底区域。可以在防止衬底12(例如,单晶材料)再结晶的临界剂量以下提供注入工艺。在实施例中,注入工艺可以是约1E14至1.5E15的剂量水平的氩注入工艺,随后执行退火工艺(例如,950℃至1100℃)以形成多晶硅材料层。注入工艺也可以使用其他注入元素,例如在形成电熔丝24和栅极结构22之前提供的其他惰性气体,例如其他稀有气体,如氙、锗、氮或氧等。掩埋非晶半导体层36连接到界定电熔丝24和栅极结构22的N阱18的底部。
此外,可以使用例如离子注入工艺在衬底12中形成P阱区38、38a和P阱38b。如已经公开的,掩埋非晶半导体层36的离子注入工艺中使用的注入掩模将防止在P阱区38、38a的位置处形成非晶半导体层36。P阱38a可用于扩散区26a(例如二极管),P阱38b可用于栅极结构22。在实施例中,P阱38、38a连接(接触)到掩埋非晶半导体层36下方的衬底12。以这种方式,P阱区38、38a可以形成在非晶半导体层36下方延伸并连接到衬底12的环,同时还界定电熔丝24和栅极结构22。本领域技术人员还应该理解,P阱38b的离子注入工艺可以使衬底(例如在阱38b和掩埋非晶半导体层36之间)再结晶为如图所示的单晶材料12a。此外,在该实施例中,栅极结构22可以是浮体(floating body)FET。
可以在片上系统(SoC)技术中利用电熔丝。SoC是将电子系统的所有部件集成在单个芯片或衬底上的集成电路(也称为“芯片”)。由于部件被集成在单个衬底上,因此与具有等效功能的多芯片设计相比,SoC消耗的功率少得多,占用的面积也少得多。因此,SoC正成为移动计算(例如在智能手机中)和边缘计算市场中的主导力量。SoC也用于嵌入式系统和物联网。
上述方法用于集成电路芯片的制造。所得到的集成电路芯片可以由制造商以原始晶片形式(即,作为具有多个未封装芯片的单个晶片),作为裸芯或以封装形式分发。在后一种情况下,芯片以单芯片封装(例如塑料载体,其引线固定到主板或其它更高级别的载体)或多芯片封装(例如陶瓷载体,其具有表面互连和/或掩埋互连)的形式被安装。在任何情况下,芯片然后与其它芯片、分立电路元件和/或其它信号处理器件集成,作为(a)中间产品(例如主板)或(b)最终产品的一部分。最终产品可以是包括集成电路芯片的任何产品,从玩具和其它低端应用到具有显示器、键盘或其它输入设备以及中央处理器的高级计算机产品。
本公开的各种实施例的描述已经出于说明的目的给出,但并非旨在是穷举的或限于所公开的实施例。在不脱离所描述的实施例的范围和精神的情况下,许多修改和变化对于本领域普通技术人员将是显而易见的。本文中所用术语的选择旨在最好地解释各实施例的原理、实际应用或对市场中发现的技术的技术改进,或者使本技术领域的其他普通技术人员能够理解本文公开的实施例。
Claims (20)
1.一种结构,包括:
衬底,其包括有界区域;
栅极结构,其形成在所述有界区域内;以及
电熔丝,其形成在所述有界区域内并电连接到所述栅极结构。
2.根据权利要求1所述的结构,其中,所述有界区域包括三阱区,所述三阱区包括掩埋N阱、位于所述掩埋N阱上方的P阱以及围绕所述栅极结构和所述电熔丝的N阱环。
3.根据权利要求2所述的结构,其中,所述N阱环接触所述掩埋N阱。
4.根据权利要求2所述的结构,其中,所述电熔丝位于所述P阱内的浅沟槽隔离结构上方并且通过至少一个金属化特征电连接到所述栅极结构。
5.根据权利要求4所述的结构,其中,所述电熔丝包括硅化多晶硅材料。
6.根据权利要求5所述的结构,其中,所述栅极结构包括场效应晶体管并且包括多晶硅栅极结构。
7.根据权利要求5所述的结构,还包括位于所述三阱区内的束缚二极管。
8.根据权利要求1所述的结构,其中,所述有界区域包括掩埋在所述衬底中的非晶半导体层和延伸穿过所述非晶半导体层的P阱。
9.根据权利要求8所述的结构,其中,所述栅极结构和所述电熔丝位于所述非晶半导体层上方。
10.根据权利要求9所述的结构,其中,所述非晶半导体层包括多晶硅材料。
11.根据权利要求10所述的结构,其中,所述栅极结构包括浮体场效应晶体管。
12.一种结构,包括:
衬底,其包括由阱界定的区域;
至少一个浅沟槽隔离结构,其位于由所述阱界定的所述区域内;
栅极结构,其位于由所述阱界定的所述区域上方;以及
电熔丝,其电连接到所述栅极结构并位于由所述阱界定的所述区域内的所述至少一个浅沟槽隔离结构上方。
13.根据权利要求12所述的结构,还包括位于由所述阱界定的所述区域中的扩散区。
14.根据权利要求13所述的结构,其中,所述扩散区包括束缚二极管。
15.根据权利要求12所述的结构,其中,所述阱包括N阱环,并且所述区域包括三阱区,所述三阱区包括掩埋N阱、位于所述掩埋N阱上方并由所述N阱环界定的P阱。
16.根据权利要求15所述的结构,其中,所述栅极结构包括位于所述三阱区中的平行位基元。
17.根据权利要求15所述的结构,还包括位于所述三阱区的结处的浅沟槽隔离结构。
18.根据权利要求12所述的结构,其中,所述阱包括延伸穿过掩埋多晶硅材料的P阱环。
19.根据权利要求18所述的结构,其中,所述栅极结构是浮体栅极结构。
20.一种方法,包括:
在衬底中形成由阱包围的有界区域;
在所述有界区域内形成至少一个浅沟槽隔离结构;
在所述有界区域上方形成栅极结构;以及
形成电连接到所述栅极结构的电熔丝,所述电熔丝形成在所述有界区域内的所述至少一个浅沟槽隔离结构上方。
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