CN118039640A - 具有富陷阱区和低电阻率区的集成结构 - Google Patents

具有富陷阱区和低电阻率区的集成结构 Download PDF

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CN118039640A
CN118039640A CN202311418476.2A CN202311418476A CN118039640A CN 118039640 A CN118039640 A CN 118039640A CN 202311418476 A CN202311418476 A CN 202311418476A CN 118039640 A CN118039640 A CN 118039640A
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semiconductor
low resistivity
high resistivity
resistivity
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V·杰恩
C·R·肯尼
J·J·派卡里克
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GlobalFoundries US Inc
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Abstract

本公开涉及具有富陷阱区和低电阻率区的集成结构。本公开涉及半导体结构，更具体地涉及具有富陷阱区和低电阻率区的衬底和制造方法。该结构包括：高电阻率半导体衬底；有源器件，其位于高电阻率半导体衬底之上；以及低电阻率区，其浮置在高电阻率半导体衬底中，并位于有源器件下方。

Description

具有富陷阱区和低电阻率区的集成结构
技术领域
本公开涉及半导体结构，更具体地，涉及具有富陷阱区(高电阻率区)和低电阻率区的集成结构和制造方法。
背景技术
在高电阻率半导体衬底上的BiCMOS集成对于不同的器件需要不同的参数。这些不同的参数在驻留于同一衬底上的所有集成器件(例如电路)之间可能不兼容。在制造过程中，这些不同的参数还可能导致其他器件的低良品率。
发明内容
在本公开的一方面，一种结构包括：高电阻率半导体衬底；有源器件，其位于所述高电阻率半导体衬底之上；以及低电阻率区，其浮置在所述高电阻率半导体衬底中，并位于所述有源器件下方。
在本公开的一方面，一种结构包括：处理衬底，其包括高电阻率半导体材料；掩埋绝缘体层，其位于所述处理衬底上方；半导体层，其位于所述掩埋绝缘体层上；有源器件，其位于所述半导体层之上；非单晶半导体区，其位于所述有源器件下方的所述处理衬底中，并且接触所述掩埋绝缘体层的下侧；以及低电阻率区，其浮置在所述处理衬底中，并位于所述有源器件下方。
在本公开的一方面，一种方法包括：在高电阻率半导体衬底之上形成有源器件；以及形成低电阻率区，所述低电阻率区浮置在所述高电阻率半导体衬底中并位于所述有源器件下方。
附图说明
在随后的详细描述中借助本公开的示例性实施例的非限制性示例，参考所指出的多个附图描述了本公开。
图1示出了根据本公开的除其他特征之外的具有位于有源器件下方的高电阻率区和低电阻率区二者的结构和相应的制造工艺。
图2示出了根据本公开的集成设计布局和相应的制造工艺。
具体实施方式
本公开涉及半导体结构，更具体地，涉及具有富陷阱区(高电阻率区)和低电阻率区的结构和制造方法。更具体地，本公开涉及具有富陷阱注入区和低电阻率注入区的在高电阻率晶片上的BiCMOS集成结构。有利地，该集成方案除了保持后段制程(BEOL)无源器件和RF FET性能(例如，切换(switch))之外，还保持了高NPN良品率，并且降低了BiCMOS集成的器件到器件泄漏。本公开还提供了FET器件的辐射硬化的益处。
在实施例中，结构可以包括用于辐射硬化的电子器件的集成电路。该结构包括包含绝缘体上半导体(SOI)技术的高电阻率半导体材料。该结构包括接触掩埋绝缘体材料的具有高电阻率注入物的区域，从而在RF FET或BEOL无源器件下方形成富陷阱层。混合区可以被深沟槽隔离结构围绕，并包括位于双极器件、FET或二极管等下方的低电阻率区。另一区域包括位于逻辑FET或其他有源器件下方的富陷阱区和低电阻率区二者。具有FET或无源器件的另一区域完全没有富陷阱区和低电阻率区二者。
本公开的结构可以使用多种不同的工具，以多种方式来制造。然而，一般地，使用方法和工具来形成具有微米和纳米级尺寸的结构。已经根据集成电路(IC)技术采用了用于制造本公开的结构的方法(即，技术)。例如，这些结构建立在晶圆上，并在晶圆顶部上借助光刻工艺而图案化的材料膜中实现。具体地，结构的制造使用三个基本构造块：(i)在衬底上沉积材料薄膜；(ii)通过光刻成像在膜顶部上施加图案化的掩模；以及(iii)对掩模选择性地蚀刻所述膜。此外，如本领域公知的，可以使用预清洁工艺来清洁蚀刻表面的任何污染物。此外，如本领域公知的，在必要时，可以使用快速热退火工艺来驱入掺杂物或材料层。
图1示出了根据本公开的除其他特征之外的具有位于有源器件下方的高电阻率区和低电阻率区二者的结构和相应的制造工艺。更具体地，结构10包括器件区100，器件区100包括位于浅沟槽隔离结构16之间的有源器件14。在一些更具体的实施例中，有源器件14可以是用于辐射硬化应用的逻辑器件(例如，FET)。如本文中更详细地描述的，有源器件14可以设置在半导体衬底12上。
在实施例中，有源器件14包括被侧壁隔离物(spacer)14b围绕的栅电极14a。栅电极14a可以是任何已知的功函数金属，例如Ti、TiN、TiAl等，或者多晶硅材料。侧壁隔离物14b可以是使用常规沉积方法(例如化学气相沉积(CVD))以及随后的本领域已知的常规各向异性蚀刻工艺制造的氧化物和/或氮化物材料。有源器件14还包括源极和漏极区14c，其设置在半导体衬底12中(更具体地，在绝缘体上半导体衬底上)。栅电极14a可以设置在栅极电介质材料上，栅极电介质材料例如是高k栅极电介质材料，例如HfO2、Al2O3、Ta2O3、TiO2、La2O3、SrTiO3、LaAlO3、ZrO2、Y2O3、Gd2O3以及包括其多层的组合。
器件14可以使用常规CMOS工艺制造。例如，在标准CMOS处理中，在半导体衬底12上形成(例如沉积)栅极电介质材料和栅电极材料，然后进行常规图案化工艺。可以在图案化的材料上沉积诸如氮化物和/或氧化物的绝缘体材料，随后进行各向异性蚀刻工艺以形成侧壁隔离物14b。源极和漏极区14c可以通过本领域已知的常规离子注入工艺或具有原位掺杂的外延生长工艺形成。本领域技术人员很清楚，源极和漏极区14c也可以通过使用外延生长和注入工艺来形成，使得源极和漏极区14c的顶部位于半导体衬底12的顶部(即，顶部半导体层12c)上方。
尽管对理解本公开并不重要，但可以在源极和漏极区14c以及栅电极(例如，多晶硅材料)上形成硅化物接触。本领域技术人员应当理解，硅化物工艺开始于在完全形成且图案化的半导体器件(例如，掺杂或离子注入的源极和漏极区14c以及相应器件(如果是多晶硅材料))之上沉积薄过渡金属层，例如，镍、钴或钛。在沉积材料之后，加热该结构，这允许过渡金属与半导体器件的有源区(例如，源极、漏极、栅极接触区)中暴露的硅(或本文所述的其他半导体材料)反应，形成低电阻过渡金属硅化物。在反应之后，通过化学蚀刻去除任何剩余的过渡金属，在器件的有源区中留下硅化物接触。本领域技术人员应当理解，当栅极结构由金属材料构成时，在器件上将不需要硅化物接触。
仍然参考图1，半导体衬底12可以包括绝缘体上半导体(SOI)技术。半导体衬底12从底部到顶部包括处理衬底12a、掩埋绝缘体层12b和顶部半导体层12c。处理衬底12a可以是高电阻率衬底，以提供提高的射频(RF)性能。在实施例中，作为示例性示例，处理衬底12a可以是电阻率在约1Kohm-cm到大于10Kohm-cm的范围内的P型半导体衬底。处理衬底12a为掩埋绝缘体层12b和顶部半导体层12c提供机械支撑。
掩埋绝缘体层12b可包括电介质材料，例如二氧化硅、氮化硅、氧氮化硅、氮化硼或其组合。在一个优选实施例中，掩埋绝缘体层12b可以是掩埋氧化物(BOX)。可以通过沉积工艺(例如化学气相沉积(CVD)、等离子体增强化学气相沉积CVD(PECVD)或物理气相沉积(PVD))来形成掩埋绝缘体层12b。在另一实施例中，可以使用热生长工艺(例如，热氧化)或将氧原子注入并退火到处理衬底12a中的注入工艺来形成掩埋绝缘体层12b。
处理衬底12a和顶部半导体层12c可以包括任何合适的半导体材料，例如Si、Ge、SiGe、SiC、SiGeC、III-V族化合物半导体、II-VI族化合物半导体或其任何组合。通常，处理衬底12a和顶部半导体层12c包括单晶半导体材料，例如，具有任何合适的晶体取向(例如，(100)、(110)、(111)或(001)晶体取向)的单晶硅。
仍然参考图1，可以在处理衬底12a中形成可选的非单晶半导体区18。在更具体的实施例中，非单晶半导体区18可以是富陷阱区，更具体地是非晶区或多晶硅区。在实施例中，非单晶半导体区18可以直接在器件14下方的掩埋绝缘体层12b的下侧下方形成并与其接触。
在实施例中，非单晶半导体区18可降低总电离剂量(TID)的效应。例如，非单晶半导体区18可产生陷阱，使得作为电离辐射的结果形成的载流子能够复合，从而器件14的Vt(或性能)不变。本领域普通技术人员应理解，电子器件中总电离剂量的效应可以包括导致器件劣化和功能失效的参数劣化。这包括阈值电压偏移，阈值电压偏移会改变电子器件起作用的方式，例如他们如何被激活或去激活。还可能发生增益降低、泄漏增加、定时变化以及功能降低。
非单晶半导体区18可以使用图案化的注入掩模通过注入工艺来形成。例如，非单晶半导体区18可以通过毯式(blanket)氩注入工艺形成；然而，针对注入工艺，本文中可以预期使用任何非掺杂剂或惰性气体。
作为说明性的非限制示例，可以在300KeV和1x1015cm-2剂量下对处理衬底12a进行氩注入。作为进一步的说明性示例，根据注入区域的期望厚度和深度，本文预期其他注入参数，包括例如离子剂量可以小于或大于1x1015cm-2或在1x1013cm-2至5x1016cm-2的范围内。类似地，注入的能量可以根据距富陷阱区表面的期望深度而被调整。非单晶半导体区18的厚度可以根据注入工艺的参数而被调整。这样，非单晶半导体区18可以是高电阻率区，例如，高于处理衬底12a的电阻率，这将降低TID。
图1还示出了位于处理衬底12a中的低电阻率区20。在实施例中，低电阻率区20可以用于降低单事件翻转(single event upset)。本领域普通技术人员应理解，单事件翻转(SEU)是由单个电离粒子(离子、电子、光子等)撞击微电子器件(例如，器件14)中的敏感节点引起的状态变化。该状态变化是由逻辑元件的重要节点中或附近的电离产生的自由电荷(电子-空穴对(EHP))的结果。作为该撞击的结果而引起的器件输出或操作的错误被称为SEU或软错误。
低电阻率区20可以是包括硼的注入区，其具有比处理衬底12a低的电阻率。例如，根据注入条件，低电阻率区20可以小于100Ohm-cm至0.001Ohm-cm。在实施例中，低电阻率区20是浮置区(例如，没有电连接)，其与非单晶半导体区18或器件14分隔开且不与其接触。在实施例中，低电阻率区20可以通过处理衬底12a的高电阻率区与非单晶半导体区18分隔开一距离“X”，其中“X”为约0.5微米；然而，根据期望的器件性能以及处理衬底12a的厚度，本文还预期其他距离。
低电阻率区20可以使用图案化的注入掩模通过注入工艺来形成。例如，低电阻率区20可以通过毯式硼注入工艺形成。作为说明性的非限制示例，可以在400KeV和5E11 cm-2剂量下对处理衬底12a进行硼注入。作为进一步的说明性示例，根据注入区域的期望厚度和深度，本文预期其他注入参数，包括例如离子剂量可以小于或大于5E11 cm-2或在5E10 cm-2至1E17 cm-2的范围内。注入的能量可以根据低电阻率区20的期望深度而被调整。低电阻率区20的厚度可以根据注入工艺的参数而被调整。
针对低电阻率区20和非单晶半导体区18二者，可以使用相应的图案化的注入掩模来限定被暴露用于注入的选定区域。注入掩模可以包括光敏材料层，例如有机光致抗蚀剂层，其通过旋涂工艺施加，被预烘烤，暴露于通过光掩模投射的光，曝光后烘烤，并用化学显影剂显影。每个注入掩模具有足以阻止掩蔽区域接收一定剂量的注入离子的厚度和停止能力。
图2示出了根据本公开的方面的集成设计布局。特别地，集成设计布局10a包括四个器件区：器件区100、器件区200、器件区300和器件区400。如图2所示，每个器件区100、200、300、400设置在关于图1描述的包括处理衬底12a、掩埋绝缘体层12b和顶部半导体层12c的半导体衬底12上。还应认识到，器件区100是关于图1描述的器件区100。
器件区200可以包括标准逻辑器件22。替代地，器件区200可以包括无源器件。在标准逻辑器件22的实施方式中，逻辑器件22包括被侧壁隔离物22b围绕的栅电极22a。栅电极20a可以是任何已知的功函数金属(例如Ti、TiN、TiAl等)或者多晶硅材料。侧壁隔离物22c可以是使用常规沉积方法(例如CVD)以及随后的本领域已知的常规各向异性蚀刻工艺制造的氧化物和/或氮化物材料。有源器件22还包括设置在半导体层12c中的源极和漏极区22c。这也可以是通过如本文中已经描述的外延生长和注入工艺形成的突起的源极和漏极区22c。栅电极22a可以设置在栅极电介质材料上，栅极电介质材料例如是高k栅极电介质材料，例如HfO2、Al2O3、Ta2O3、TiO2、La2O3、SrTiO3、LaAlO3、ZrO2、Y2O3、Gd2O3以及包括其多层的组合。器件区200没有任何高电阻率区和低电阻率区。
器件区300可以包括标准RF器件或BEOL无源器件24。在该实施方式中，除了源极和漏极区24c之外，标准RF器件24包括被侧壁隔离物24b围绕的栅电极24a。器件区300还包括非单晶半导体区18，非单晶半导体区18直接在器件24下方的掩埋绝缘体层12b的下侧下方形成并与其接触。器件区100和300中的非单晶半导体区18可以使用同一图案化的掩模在同一注入工艺中形成。如前面所公开的，低电阻率区20可以是包括氩的注入区。然而，器件区300没有任何低电阻率区。
器件区400包括异质结双极晶体管26，例如，NPN。在实施例中，器件区400可以包括其他器件，例如二极管或无源器件。如本领域中已知的，异质结双极晶体管26包括发射极26a、外部/内部基极区26b、集电极区26c和子集电极区26d。在实施例中，集电极区26c形成在子集电极区26d之上。集电极区26c例如可以是Si材料。子集电极区26d可以使用本领域已知的图案化的掩模通过离子注入工艺在处理衬底12a中形成。注入物可以是n型掺杂剂，例如砷(as)、磷(P)和Sb，以及其他合适的示例。外部/内部基极区26b可以是外延生长在顶部半导体层12c上的半导体材料，例如SiGe。发射极26a可以是在内部基极区26b上外延生长的N型半导体材料。
集电极区26c和子集电极区26d在深沟槽隔离结构28内被隔离。在实施例中，深沟槽隔离结构28可通过本领域技术人员已知的常规光刻、蚀刻和沉积方法形成。例如，将形成在顶部半导体层12c上的抗蚀剂暴露于能量(光)下，并利用常规抗蚀剂显影剂进行显影，以形成图案(开口)。具有选择性化学的蚀刻工艺，例如反应离子蚀刻(RIE)，将用于将图案从图案化的光致抗蚀剂层转移到顶部半导体层12c和处理衬底12a，以形成一个或多个沟槽。在通过常规氧灰化工艺或其他已知的剥离剂去除抗蚀剂之后，可以通过任何常规沉积工艺(例如CVD工艺)沉积绝缘体材料。顶部半导体层12c表面上的任何残留材料都可以通过常规化学机械抛光(CMP)工艺去除。
仍参考器件区400，在子集电极区26d下方的处理衬底12a中形成低电阻率区20。在另外的实施例中，低电阻率区20不接触子集电极区26d。低电阻率区20可以接触深沟槽隔离区28以便隔离器件26。器件区100和400中的低电阻率区20可以使用同一掩模在同一注入工艺中形成。如前面所公开的，低电阻率区20可以是包括硼的注入区，其具有比处理衬底12a低的电阻率。
可以在片上系统(SoC)技术中利用该结构。SoC是将电子系统的所有部件集成在单个芯片或衬底上的集成电路(也称为“芯片”)。由于部件被集成在单个衬底上，因此与具有等效功能的多芯片设计相比，SoC消耗的功率少得多，占用的面积也少得多。因此，SoC正成为移动计算(例如在智能手机中)和边缘计算市场中的主导力量。SoC也常用于嵌入式系统和物联网。
上述方法用于集成电路芯片的制造。所得到的集成电路芯片可以由制造商以原始晶圆形式(即，作为具有多个未封装芯片的单个晶圆)，作为裸芯或以封装形式分发。在后一种情况下，芯片以单芯片封装(例如塑料载体，其引线固定到主板或其它更高级别的载体)或多芯片封装(例如陶瓷载体，其具有表面互连或掩埋互连、或者表面互连和掩埋互连两者)的形式被安装。在任何情况下，芯片然后与其它芯片、分立电路元件和/或其它信号处理器件集成，作为(a)中间产品(例如主板)或(b)最终产品的一部分。最终产品可以是包括集成电路芯片的任何产品，从玩具和其它低端应用到具有显示器、键盘或其它输入设备以及中央处理器的高级计算机产品。
本公开的各种实施例的描述已经出于说明的目的给出，但并非旨在是穷举的或限于所公开的实施例。在不脱离所描述的实施例的范围和精神的情况下，许多修改和变化对于本领域普通技术人员将是显而易见的。本文中所用术语的选择旨在最好地解释各实施例的原理、实际应用或对市场中发现的技术的技术改进，或者使本技术领域的其他普通技术人员能够理解本文公开的实施例。

Claims (20)

1.一种结构，包括：
高电阻率半导体衬底；
有源器件，其位于所述高电阻率半导体衬底之上；以及
低电阻率区，其浮置在所述高电阻率半导体衬底中，并位于所述有源器件下方。
2.根据权利要求1所述的结构，其中，所述高电阻率半导体衬底包括位于掩埋绝缘体层和顶部半导体层下方的高电阻率处理衬底。
3.根据权利要求2所述的结构，其中，所述低电阻率区在所述掩埋绝缘体层和所述高电阻率处理衬底中的所述有源器件下方浮置且不接触所述掩埋绝缘体层和所述有源器件，其中在所述有源器件与所述低电阻率区之间具有高电阻率区。
4.根据权利要求3所述的结构，其中，所述低电阻率区包括硼。
5.根据权利要求3所述的结构，还包括位于高电阻率处理衬底中的非单晶半导体区。
6.根据权利要求5所述的结构，其中，所述非单晶半导体区包括与所述掩埋绝缘体层的下侧接触且与所述低电阻率区分隔开的非晶半导体材料和多晶半导体材料中的一种。
7.根据权利要求5所述的结构，其中，所述非单晶半导体区包括与所述掩埋绝缘体层的下侧接触且与所述低电阻率区分隔开的富陷阱半导体区。
8.根据权利要求5所述的结构，其中，所述有源器件包括逻辑晶体管。
9.根据权利要求5所述的结构，还包括位于所述高电阻率处理衬底之上且没有所述低电阻率区和所述非单晶半导体区的器件。
10.根据权利要求5所述的结构，还包括位于所述高电阻率处理衬底之上且没有所述低电阻率区的器件，所述器件包括位于所述器件下方的所述非单晶半导体区。
11.根据权利要求5所述的结构，还包括位于所述高电阻率处理衬底之上且没有所述非单晶半导体区的器件，所述器件包括位于所述器件下方的所述低电阻率区。
12.一种结构，包括：
处理衬底，其包括高电阻率半导体材料；
掩埋绝缘体层，其位于所述处理衬底上方；
半导体层，其位于所述掩埋绝缘体层上；
有源器件，其位于所述半导体层之上；
非单晶半导体区，其位于所述有源器件下方的所述处理衬底中，并且接触所述掩埋绝缘体层的下侧；以及
低电阻率区，其浮置在所述处理衬底中，并位于所述有源器件下方。
13.根据权利要求12所述的结构，其中，所述低电阻率区包括硼，并且所述非单晶半导体区包括非晶半导体材料和多晶半导体材料中的一种。
14.根据权利要求12所述的结构，其中，所述非单晶半导体区包括与所述掩埋绝缘体层的下侧接触且与所述低电阻率区分隔开的富陷阱半导体材料。
15.根据权利要求12所述的结构，还包括位于所述半导体层之上的第二器件，其中，位于所述第二器件下方的所述高电阻率半导体材料没有所述低电阻率区和所述非单晶半导体区。
16.根据权利要求15所述的结构，还包括位于所述半导体层之上的第三器件，其中，位于所述第三器件下方的所述高电阻率半导体材料没有所述低电阻率区且包括所述非单晶半导体区。
17.根据权利要求16所述的结构，还包括位于所述处理衬底之上的第四器件，其中，位于所述第四器件下方的所述高电阻率半导体材料没有所述非单晶半导体区且包括所述低电阻率区。
18.根据权利要求12所述的结构，其中，所述有源器件包括辐射硬化的逻辑器件。
19.根据权利要求12所述的结构，其中，所述低电阻率区包括硼。
20.一种方法，包括：
在高电阻率半导体衬底之上形成有源器件；以及
形成低电阻率区，所述低电阻率区浮置在所述高电阻率半导体衬底中并位于所述有源器件下方。
CN202311418476.2A 2022-11-13 2023-10-30 具有富陷阱区和低电阻率区的集成结构 Pending CN118039640A (zh)

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US6884702B2 (en) * 2002-06-04 2005-04-26 Advanced Micro Devices, Inc. Method of making an SOI semiconductor device having enhanced, self-aligned dielectric regions in the bulk silicon substrate
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