TWI755973B - 具有背閘極觸點及埋藏高電阻層的場效電晶體 - Google Patents

具有背閘極觸點及埋藏高電阻層的場效電晶體 Download PDF

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TWI755973B
TWI755973B TW109144313A TW109144313A TWI755973B TW I755973 B TWI755973 B TW I755973B TW 109144313 A TW109144313 A TW 109144313A TW 109144313 A TW109144313 A TW 109144313A TW I755973 B TWI755973 B TW I755973B
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威霍 詹恩
安東尼Ｋ 史坦普
史蒂芬Ｍ 尚克
莫納漢 約翰Ｊ 艾立斯
約翰Ｊ 貝肯瑞
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美商格芯（美國）集成電路科技有限公司
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Abstract

本揭露係有關於半導體結構，且更具體地，係有關於具有背閘極觸點及埋藏高電阻層的場效電晶體及製造方法。該結構包括：操作晶圓，其包括單晶半導體區；單晶半導體區上方的絕緣體層；絕緣體層上方的半導體層；操作晶圓中的高電阻層，係藉由單晶半導體區而與絕緣體層隔開；以及半導體層上的裝置。

Description

具有背閘極觸點及埋藏高電阻層的場效電晶體
本揭露係有關於半導體結構，且更具體地，係有關於具有背閘極觸點及埋藏高電阻層的場效電晶體及製造方法。
塊狀矽基板比絕緣體上矽（SOI）基板更便宜。通常，SOI基板包括矽的薄裝置層、操作基板、以及將裝置層與操作基板物理分離並電隔離的薄埋藏氧化物（BOX）層。與內置在塊狀矽基板中的同類裝置相比，使用SOI技術製造的裝置可能會表現出某些性能改進。例如，與SOI基板相反，塊狀矽基板的特徵是與諧波產生（harmonic generation）有比較差的裝置隔離。具有接觸BOX的富阱層的高電阻率晶圓可用作為操作基板，但富阱層的存在不允許本體觸點（body contacts）的形成。
在本揭露的一態樣，一種結構包括：操作晶圓，其包括單晶半導體區；單晶半導體區上方的絕緣體層；絕緣體層上方的半導體層；操作晶圓中的高電阻層，係藉由單晶半導體區而與絕緣體層隔開；以及半導體層上的裝置。
在本揭露的一態樣，一種結構包括：晶圓，包括埋藏氧化物層下方的單晶區及埋藏氧化物層上方的半導體層；至少一阱，形成於埋藏氧化物層下方的單晶區中；多晶矽層，嵌入在晶圓內，並藉由單晶區而與至少一阱及埋藏氧化物層隔開；裝置，位於半導體層上；以及背閘極觸點，係延伸經過半導體層並接觸至少一阱。
在本揭露的一態樣，一種結構包括：在絕緣體晶圓上半導體上的至少一場效電晶體，絕緣體晶圓上半導體包括高電阻多晶矽層，係藉由在絕緣體晶圓上半導體的單晶區而與埋藏氧化物層及至少一場效電晶體的阱所隔開。
本揭露係有關於半導體結構，且更具體地，係有關於具有背閘極觸點及埋藏高電阻層的場效電晶體及製造方法。更具體地，本揭露係有關於在絕緣體上半導體（SOI）技術上所形成的場效電晶體，其具有（多個）背閘極觸點及埋藏高電阻層。在具體實施例中，埋藏高電阻層是埋藏在單晶晶圓內的富含阱多晶矽材料。有利地，本文揭露的結構保留了背偏置觸點，並能夠以改善的隔離度來改善線性度及RF性能。
在更特定的具體實施例中，場效電晶體包括在具有高電阻層的單晶操作晶圓（晶圓處理器）中的本體觸點。在具體實施例中，高電阻層是富含阱多晶矽層，其被埋藏在操作晶圓中並且不與SOI技術的埋藏絕緣體層（例如，BOX）接觸。亦即，單晶矽區將高電阻多晶矽層及埋藏絕緣體層（例如，BOX）分開。這使得能夠在操作晶圓中形成本體偏置區/阱。而且，藉由利用本文所述的結構，除其他優點外，還可以實現以下優點：（i）利用用於開關裝置的富含阱（高電阻率）埋藏層而改善的線性；（ii）因高電阻層的電感、電容及電阻（LCR）之被動裝置性能的優勢；（iii）對基板的改善電容，包括例如改善增益（噪音因數（NF））；以及（iv）改善的裝置間隔離度，亦即共享阱裝置也顯示出更好的隔離度。
本揭露的電晶體可使用多種不同的工具以多種方式製造。但是，通常，這些方法和工具用於形成尺寸在微米及奈米等級的結構。已從積體電路（IC）技術採用了用於製造本揭露的電晶體的方法，亦即技術。例如，該結構建立在晶圓上，並在晶圓頂部上藉由微影成像製程所圖案化的材料膜中實現。特別是，電晶體的製造係使用三個基本建構組件：（i）沉積材料的薄膜於基板上，（ii）藉由微影成像而在膜的頂部上施加圖案化的遮罩，以及（iii）選擇性地將膜蝕刻至遮罩。
圖1為顯示根據本揭露態樣的具有除其他特徵之外的高電阻層的晶圓。更具體地，晶圓10包括使用作為前端模組的操作晶圓12，且其可具有用於RF裝置應用的高電阻率。操作晶圓12可代表絕緣體上半導體（SOI）技術。SOI技術可為例如完全耗盡的SOI （FDSOI）或部分耗盡的SOI （PDSOI）。本領域技術人員應當理解，操作晶圓12可為SOI技術中的支撐基板。例如，操作晶圓12可為塊狀Si或具有拋光或蝕刻背面的其他半導體基板。
在具體實施例中，操作晶圓12包括單晶材料12a，其包含例如單晶Si材料。在替代具體實施例中，單晶材料12a可為其他單晶半導體材料，例如SiGe、SiC等。使用常規的熱氧化製程或本領域技術人員已知的其他製程，將絕緣體或介電層12b（例如，埋藏氧化物層（BOX））黏結或沉積到單晶材料12a上，亦即，藉由注入氧的分離法（SIMOX）及/或其他合適的製程，使得對於本揭露的完整理解不需要進一步的解釋。基板12c沉積在絕緣體層12b上方或直接結合至絕緣體層12b。基板12c可為單晶矽或本文所述的其他合適的單晶基板。
仍參考圖1，高電阻層14被嵌入在操作晶圓12內。更具體地，高電阻層14被嵌入在絕緣體層12b的下方，並被單晶材料例如單晶材料區12d而與絕緣體層12b完全分開。這樣，高電阻層14不接觸或觸碰絕緣體層12b。在具體實施例中，高電阻層14可為富含阱多晶矽材料，其在形成基板12c及絕緣體層12b之前，藉由注入製程，接著熱退火製程來製造。
在具體實施例中，高電阻層14可以在低於防止操作晶圓12（例如單晶材料12a）的再結晶的臨界劑量的情況下，藉由注入製程（其形成非晶材料）而形成。更具體地，植入製程可處於1E14至5E15的劑量，並且在更優選的具體實施例中為1E15。植入者可為氬氣或其他惰性氣體例如氮氣，或氧氣等。在注入製程之後，對操作晶圓12進行快速熱退火製程，以使操作晶圓12的表面再結晶，形成單晶材料區12d。快速熱退火製程還將在再結晶區（層）12d下方留下富含阱多晶矽層14。快速熱退火製程的溫度可為0到10秒內介於900°C至1150°C之間。本領域技術人員應該理解，富含阱多晶矽層14將有利地提供改善的線性度並將能夠釘紮閘極偏壓。
圖2為顯示根據本揭露態樣的除其他特徵之外的淺溝槽隔離區及擴散或阱區。在具體實施例中，淺溝槽隔離區16可具有被調整為延伸至高電阻層14的深度，以高度隔離任何隨後形成的裝置。在具體實施例中，淺溝槽隔離區16可藉由本領域技術人員已知的常規微影、蝕刻及沉積方法而形成。例如，將形成在基板12c上的阻劑暴露於能量（光）以形成圖案（開口）。具有選擇性化學作用的蝕刻製程，例如反應性離子蝕刻（RIE），將用於通過阻劑的開口在基板12c、絕緣體層12b及單晶區12d中形成一或多個溝槽。阻劑接著可藉由常規的氧灰化製程或其他已知的剝離劑而去除。在去除阻劑之後，絕緣體材料（例如，氧化物）可藉由任何常規的沉積製程，例如化學氣相沉積（CVD）製程來沉積。基板12c表面上的任何殘留材料可藉由常規化學機械拋光（CMP）製程而去除。
仍參考圖2，可選的淺溝槽隔離區18形成在基板12c內，延伸到絕緣體層12b。在具體實施例中，可選的淺溝槽隔離區18也可以部分地延伸到BOX層12b中。可選的淺溝槽隔離區18可以本文已描述的方式，與淺溝槽隔離區16同時形成。可選的淺溝槽隔離區18可用於例如邏輯場效電晶體（FET）。
另外，在絕緣體層12b下方並且在淺溝槽隔離區16及高電阻層14之間的單晶材料區12d內，形成用於NFET及PFET的阱20a、20b。在具體實施例中，單晶材料區12d的厚度及阱20a、20b的注入能量可被優化，以確保阱20a、20b與高電阻層14完全分離，亦即，阱20a、20b不要接觸或觸碰高電阻層14。
更具體地，且仍參考圖2，阱20a、20b可藉由在基板例如單晶材料區12d中引入一定濃度的相反導電類型的不同摻雜劑來形成。例如，除了其他合適的例子以外，P阱摻雜有p型摻雜劑，例如硼（B），而N阱摻雜有n型摻雜劑，例如砷（As）、磷（P）及Sb。在具體實施例中，各個圖案化的注入遮罩可用於限定暴露出的所選區，以用於為阱20a、20b注入不同摻雜劑。注入遮罩可包括一層光敏材料，例如有機光阻劑，其藉由旋塗製程施加、預烘烤、暴露於經過光遮罩所投射的光，曝光後烘烤，並以化學顯影劑顯影。如本領域技術人員應當理解的，每個注入遮罩具有足以阻擋遮罩區以防止接收一定劑量的注入離子的厚度及停止能力。
在圖3中，根據本揭露的各態樣，除其他特徵之外及相應的製造程序，電晶體22係形成在基板12c上。在具體實施例中，電晶體22亦可代表電阻器及/或其他線路後端（BEOL）被動裝置，例如，線路後端（BEOL）材料中的MIMcap、感應器、傳輸線等。
在圖3中，電晶體22（或其他裝置）係使用常規沉積、微影及蝕刻製程，而形成在基板12c上。例如，對於電晶體22，使用常規沉積製程，例如原子層沉積（ALD）及CVD製程，然後藉由使用微影及具有選擇化學作用的蝕刻（RIE）的圖案化製程，閘極介電材料22a與功函數金屬（或多晶矽材料）22b係沉積在基板12c上。在具體實施例中，閘極介電材料22a可為高k閘極介電材料，例如，HfO2 、Al2 O3 、Ta2 O3 、TiO2 、La2 O3 、SrTiO3 、LaAlO3 、ZrO2 、Y2 O3 、Gd2 O3 ，及包括其多層的組合。用於p通道FET的功函數材料的實例包括Ti、TiAlC、Al、TiAl、TaN、TaAlC、TiN、TiC及Co。用於n通道FET的功函數材料的實例包括TiN、TaN、TaAlC、TiC、TiAl、TaC、Co、Al、TiAl、HfTi、TiSi、TaSi或TiAlC。功函數材料可藉由CVD、包括濺射的物理氣相沉積（PVD）、ALD或其他合適方法來沉積。
在圖案化步驟之後，側壁間隔物22c係形成於圖案化的材料上方。在具體實施例中，側壁間隔物22c係藉由常規的沉積製程接著異向性蝕刻製程而形成。側壁間隔物22c可由任何合適的側壁材料組成。例如，側壁材料可為氮化物材料。在側壁間隔物22c的側面上形成凸起的擴散區22d，例如源極和汲極區。如本領域技術人員已知的，例如，藉由在基板12c上的摻雜外延生長製程，凸起的源極和汲極區22d被形成，從而不需要進一步解釋就完全理解本揭露。儘管在圖中電晶體結構被顯示為相同，是本領域技術人員應當理解，根據需要，這些電晶體結構可為具有不同閾值電壓的NFET及/或PFET。另外，不需要同時製造電晶體。
本領域普通技術人員還應該理解，電晶體可在層12d上形成，亦即，在單晶材料區12d上形成，如代表性的參考數字23所示。在此具體實施例中，高電阻層14保留在電晶體23下方。電晶體23可以與電晶體22類似的方式形成，但採用較早的製造流程。另外，其他裝置，例如主動或被動裝置，可在單晶材料區12d上形成，這將需要在形成此類裝置之前對層12b、12c蝕刻或去除。另外，本領域技術人員應該理解，可將高電阻層14限制在電晶體22下方（例如，並非晶圓上到處都有），以減少諧波。對於邏輯FET，不需要在下面具有高電阻層14。
圖4為顯示根據本揭露態樣的除其他特徵之外的背閘極觸點24。在具體實施例中，背閘極觸點24形成在介電材料26中，並延伸以直接接觸相應的阱20a、20b。背閘極觸點24可形成在隔離區16、18之間。在沒有可選的隔離區18的情況下，背閘極觸點24可形成在隔離區16與電晶體22的升高擴散區22d之間。
為了形成背閘極觸點24（以及到源極與汲極區的觸點），阱20a、20b的暴露表面經歷矽化物製程，其開始於沉積薄的過渡金屬層，例如鎳、鈷或鈦，然後進行退火製程，以形成低電阻過渡金屬矽化物。在退火製程之後，金屬材料例如鎢或鋁或其合金係沉積在矽化物區上以及介電材料26中的溝槽內，以形成背面觸點24。在介電材料26、基板12c及絕緣體層12b內形成溝槽，以暴露下面的阱20a、20b。如本文先前所述，溝槽可藉由具有選擇化學性的常規微影及蝕刻製程（RIE）而形成。
本文所述的電晶體及附加結構可用於晶片上系統（SoC）技術中。本領域技術人員應該理解，SoC是積體電路（也稱為「晶片」），係將電子系統的所有組件集成在單個晶片或基板上。由於組件集成在單個基板上，因此與具有等效功能的多晶片設計相比，SoC消耗的功率少很多，佔用的面積也少很多。因此，SoC成為行動計算（例如智慧型手機）及邊緣計算市場中的主導力量。SoC也常用於嵌入式系統及網際網路中。
如上所述的方法被用於積體電路晶片的製造中。製造商可以原始晶圓形式（亦即，具有多個未封裝晶片的單個晶片）、裸晶片或封裝形式，來分佈所得的積體電路晶片。在後一種情況下，晶片安裝在單晶片封裝中（例如塑膠載體，其引線固定在主板或其他更高級別的載體上）或在多晶片封裝中（例如具有一個或兩個表面互連或埋藏互連的陶瓷載體）。在任何情況下，晶片接著與其他晶片、分立電路元件及/或其他訊號處理設備集成在一起，作為（a）中間產品（例如母板）或（b）最終產品的一部分。最終產品可為任何包含積體電路晶片的產品，範圍從玩具及其他低端應用到具有顯示器、鍵盤或其他輸入設備以及中央處理器的高級計算機產品。
已出於說明的目的呈現了對本揭露的各種具體實施例的描述，但這些描述並不旨為窮舉的或限於所揭露的具體實施例。在不脫離所描述的具體實施例的範疇及精神的情況下，許多修改及變化對於本領域普通技術人員來說將是顯而易見的。選擇本文使用的術語是為了最好地解釋具體實施例的原理，對市場上發現的技術的實際應用或技術上的改進，或者使本領域的其他普通技術人員能夠理解本文揭露的具體實施例。
10:晶圓 12:操作晶圓 12a:單晶材料 12b:絕緣體層 12c:基板 12d:單晶材料區 14:高電阻層（富含阱多晶矽層） 16:淺溝槽隔離區 18:淺溝槽隔離區 20a:阱 20b:阱 22:電晶體 22a:閘極介電材料 22b:功函數金屬 22c:側壁間隔物 22d:擴散區 23:電晶體 24:背閘極觸點 26:介電材料
藉由本揭露的例示性具體實施例的非限制性實例的方式，參考所提到的多個附圖，闡述本揭露於下面的詳細描述中。
圖1為顯示根據本揭露態樣的具有除其他特徵之外的高電阻層的晶圓。
圖2為顯示根據本揭露態樣的除其他特徵之外的淺溝槽隔離區及阱。
圖3為顯示根據本揭露態樣的除其他特徵之外的電晶體。
圖4為顯示根據本揭露態樣的除其他特徵之外的背閘極觸點。
12:操作晶圓
12a:單晶材料
12b:絕緣體層
12c:基板
12d:單晶材料區
14:高電阻層(富含阱多晶矽層)
16:淺溝槽隔離區
18:淺溝槽隔離區
20a:阱
20b:阱
22:電晶體
22a:閘極介電材料
22b:功函數金屬
22c:側壁間隔物
22d:擴散區
24:背閘極觸點
26:介電材料

Claims (19)

  1. 一種結構，其包含：一操作晶圓，包含一單晶半導體區；一絕緣體層，位於該單晶半導體區上方；一半導體層，位於該絕緣體層上方；一高電阻層，位在介於該操作晶圓的半導體材料之間，係藉由該單晶半導體區而與該絕緣體層隔開；以及一裝置，位於該半導體層上；其中該單晶半導體區是一單晶矽材料，係將該高電阻層與該絕緣體層完全分離。
  2. 如請求項1所述之結構，其中該裝置是一場效電晶體(FET)。
  3. 如請求項2所述之結構，進一步包含在該場效電晶體下方的一阱區，該阱區係藉由該單晶半導體區而與該高電阻層隔開。
  4. 如請求項3所述之結構，其中該高電阻層不接觸亦不觸碰該絕緣體層及該阱區。
  5. 如請求項4所述之結構，其中該高電阻層是嵌入在該操作晶圓內的一富含阱多晶矽層。
  6. 如請求項2所述之結構，進一步包含複數個背閘極觸點，係延伸至該場效電晶體下方的該阱區並與之接觸。
  7. 如請求項6所述之結構，進一步包含隔離該場效電晶體的複數個淺溝槽隔離區，其中該複數個淺溝槽隔離區延伸經過該單晶半導體區、該絕緣體層及該半導體層到達該高電阻層。
  8. 如請求項7所述之結構，進一步包含複數個次級淺溝槽隔離區，係至少延伸至該絕緣體層。
  9. 如請求項1所述之結構，其中該裝置是一被動裝置，位在該半導體層上或在線材料的後端裡。
  10. 如請求項1所述之結構，其中，該高電阻層僅在該半導體層上的該裝置下方的選定區中。
  11. 如請求項1所述之結構，進一步包含另一裝置，位在該單晶半導體區上。
  12. 一種結構，其包含：一晶圓，包含一埋藏氧化物層下方的一單晶區及該埋藏氧化物層上方的一半導體層；至少一阱，形成於該埋藏氧化物層下方的該單晶區中；一多晶矽層，嵌入在該晶圓內，並藉由該單晶區而與該至少一阱及該埋藏氧化物層隔開；一裝置，位於該半導體層上；以及複數個背閘極觸點，係延伸經過該半導體層並接觸該至少一阱。
  13. 如請求項12所述之結構，其中該裝置是一場效電晶體(FET)。
  14. 如請求項12所述之結構，其中，該單晶區是該晶圓的一單晶半導體材料。
  15. 如請求項14所述之結構，其中嵌入在該晶圓內的該多晶矽層是一高電阻層，不接觸亦不觸碰該埋藏氧化物層及該至少一阱。
  16. 如請求項12所述之結構，進一步包含隔離該裝置的複數個淺溝槽隔離區，該複數個淺溝槽隔離區延伸至該多晶矽層並與之接觸。
  17. 如請求項16所述之結構，進一步包含複數個次級淺溝槽隔離區，係至少延伸至該絕緣體層。
  18. 如請求項12所述之結構，其中該單晶區是一單晶半導體材料，係將該多晶矽層與該絕緣體層及該至少一阱完全分離。
  19. 一種結構，其包含在一絕緣體晶圓上半導體上的至少一場效電晶體，該絕緣體晶圓上半導體包含一高電阻多晶矽層，係藉由在該絕緣體晶圓上半導體的一單晶區而與一埋藏氧化物層及該至少一場效電晶體的一阱所隔開，其中該高電阻多晶矽層係位在該埋藏氧化物層及該阱下方，且該高電阻多晶矽層不接觸該埋藏氧化物層亦不接觸該阱。
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