TW201537637A - 絕緣層覆矽基底及其形成方法 - Google Patents
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- 239000000758 substrate Substances 0.000 claims abstract description 67
- 238000000034 method Methods 0.000 claims abstract description 52
- 230000007547 defect Effects 0.000 claims abstract description 30
- 239000013078 crystal Substances 0.000 claims abstract description 20
- 239000000463 material Substances 0.000 claims abstract description 20
- 230000003647 oxidation Effects 0.000 claims description 36
- 238000007254 oxidation reaction Methods 0.000 claims description 36
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 34
- 229910052732 germanium Inorganic materials 0.000 claims description 27
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 8
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000002019 doping agent Substances 0.000 claims description 3
- 239000004744 fabric Substances 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 2
- 229910052797 bismuth Inorganic materials 0.000 claims description 2
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims description 2
- 239000000460 chlorine Substances 0.000 claims description 2
- 229910052801 chlorine Inorganic materials 0.000 claims description 2
- 230000005669 field effect Effects 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 239000000969 carrier Substances 0.000 abstract description 4
- 238000000151 deposition Methods 0.000 abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 229920005591 polysilicon Polymers 0.000 abstract description 3
- 239000012212 insulator Substances 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 115
- 229910052715 tantalum Inorganic materials 0.000 description 13
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 13
- 230000001590 oxidative effect Effects 0.000 description 7
- 125000004429 atom Chemical group 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 5
- 239000007943 implant Substances 0.000 description 5
- 239000002245 particle Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 230000006798 recombination Effects 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 239000000370 acceptor Substances 0.000 description 3
- 238000001953 recrystallisation Methods 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 239000000356 contaminant Substances 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- YNJBWRMUSHSURL-UHFFFAOYSA-N trichloroacetic acid Chemical compound OC(=O)C(Cl)(Cl)Cl YNJBWRMUSHSURL-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000005270 abrasive blasting Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000008187 granular material Substances 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- -1 hydrogen ions Chemical class 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- XEEYBQQBJWHFJM-UHFFFAOYSA-N iron Substances [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 238000006748 scratching Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
本揭露係關於具有富阱層之絕緣層覆矽基底及其相關形成方法,其中富阱層包括結晶缺陷且設置於操作晶圓中。在一些實施例中,此絕緣層覆矽基底具有操作晶圓。富阱層係設置於操作晶圓中,其位於毗接操作晶圓之一頂表面處,並具有多個用以捕捉載子之結晶缺陷。絕緣層,具有毗接操作晶圓頂表面之第一側及毗接主動矽薄層之相反的第二側。藉由將富阱層形成於操作晶圓中,可降低沉積富阱層材料(例如:多晶矽)於操作晶圓上之相關製造成本,並避免熱不穩定性問題。
Description
本揭露係有關於絕緣層覆矽基底及其相關之形成方法。
積體晶片係形成於包括半導體材料的基底上。傳統上,積體晶片係形成於包括固體層半導體材料之塊體基底上。近年來,出現絕緣層覆矽基底(silicon-on-insulator,SOI)作為替代物。絕緣層覆矽基底係具有一層絕緣材料隔離主動矽薄層及下層操作晶圓之基底。此層絕緣材料使主動矽薄層及操作晶圓電性分離,以減少形成於主動矽薄層中之裝置漏電流(current leakage)。此主動矽薄層亦提供其他優點,如:快速之轉換時間及較低之操作電壓,使得絕緣層覆矽基底廣泛應用於射頻(radio frequency,RF)大批量製造(high volume fabrication),如:射頻轉換器。
在一些實施例中,本揭露係有關於基底。此基底包括操作晶圓。此基底更進一步包括設置於操作晶圓中之富阱層,而富阱層之位置係自操作晶圓頂表面延伸至操作晶圓中下層之結晶層,其中富阱層包括多個配置以捕捉載子之結晶缺陷。此基底更進一步包括絕緣層以及主動矽薄層,此絕緣層在
與富阱層之交界面處具有第一側毗接操作晶圓之頂表面,而主動矽薄層毗接相反於第一側之絕緣層第二側。
在其他實施例中,本揭露係有關於絕緣層覆矽基底基底。此絕緣層覆矽基底基底包括高電阻矽操作晶圓。此絕緣層覆矽基底基底更進一步包括設置於操作晶圓中之富阱層,富阱層之位置係毗接操作晶圓頂表面,其中富阱層包括多個配置以捕捉載子之結晶缺陷。此絕緣層覆矽基底基底更進一步包括熱氧化物層以及主動矽薄層,此熱氧化物層在與富阱層之交界面處具有第一側毗接操作晶圓之頂表面,而主動矽薄層毗接相反於第一側之熱氧化物層第二側。
在另一些實施例中,本揭露係有關於絕緣層覆矽基底基底之形成方法。此方法包括損壞高電阻操作晶圓之頂表面以沿頂表面形成非晶相區域。此方法更進一步包括執行高溫熱氧化製程以同步於非晶相區域上形成熱氧化物層,並於非晶相區域中形成多個配置以捕捉載子之結晶缺陷。此方法更包括固定主動矽晶圓至熱氧化物層,並降低主動矽晶圓之厚度以形成毗接熱氧化物層之主動矽薄層。
100‧‧‧絕緣層覆矽基底
102‧‧‧操作晶圓
104‧‧‧結晶層
106‧‧‧富阱層
106a‧‧‧頂表面
108‧‧‧絕緣層
108a‧‧‧第一側
108b‧‧‧第二側
110‧‧‧主動矽薄層
200‧‧‧SOI基底
202‧‧‧矽操作晶圓
204‧‧‧富阱層
206‧‧‧氧化引致疊差
300‧‧‧方法
302、304、306、308、310、312、314、316‧‧‧步驟
400‧‧‧剖面圖
402‧‧‧操作晶圓
500‧‧‧剖面圖
502‧‧‧操作晶圓
503‧‧‧頂表面
504‧‧‧佈值物質
506‧‧‧非晶相區域
508‧‧‧剖面圖
510‧‧‧研磨顆粒
600‧‧‧剖面圖
602‧‧‧氧化粒子
604‧‧‧高溫
606‧‧‧熱氧化物層
700‧‧‧剖面圖
702‧‧‧主動矽基底
800‧‧‧剖面圖
d‧‧‧深度
t1、t2‧‧‧厚度
搭配附圖閱讀以下詳細的描述說明可以對本揭露各個面向有更完善的了解。必須強調的是,根據常規作法,附圖中各項特徵並未按照真實比例繪示。事實上,各項特徵尺寸比例可能任意放大或縮小,以使討論內容更清楚明瞭。
第1圖繪示一些實施例之剖面圖,其中絕緣層覆矽基底具有包括富阱層的矽操作晶圓,而富阱層包括多個結晶缺陷。
第2圖繪示一些實施例之剖面圖,其中絕緣層覆矽基底具有包括富阱層的矽操作晶圓,而富阱層中包括氧化引致疊差或錯位的結晶缺陷。
第3圖繪示製造絕緣層覆矽基底之方法實施例流程圖,其中絕緣層覆矽基底具有包括富阱層的操作晶圓,而富阱層包括多個結晶缺陷。
第4、5A-5B、6-8圖繪示一些實施例之剖面圖,其顯示製造絕緣層覆矽基底之方法,其中絕緣層覆矽基底具有包括富阱層的矽操作晶圓,而富阱層包括多個結晶缺陷。
以下提供許多不同實施例或示例,以施行所請標的之各種特徵。以下描述元件及設置之特定示例以簡化本揭露。當然,此等僅為示例,並非意圖作為限定。舉例而言,在以下”形成第一特徵於第二特徵上或上方”的描述中,可能包含第一特徵及第二特徵形成直接接觸的實施方式,亦可能包含形成額外的特徵於第一特徵及第二特徵之間,而第一特徵與第二特徵並未直接接觸的實施方式。此外,本揭露在不同例子可能使用重複的標號數字及/或字母。此重複係為了簡化及清楚之目的,並非代表所討論之不同實施例及/或結構間具有特定的關係。
再者,本文使用之空間性相對詞語,例如:”下面”、”之下”、”較低”、”之上”、”較高”及其相似者,係為了簡單描述如圖中繪示之元件或特徵相對另一元件或特徵之關係。這些空間性相對詞語意圖涵蓋除了圖中所繪示方位以外,裝置於使用
或操作中之不同方位。此設備或組件亦可轉向(旋轉90度或於其他方向),而所使用之空間性詞語亦可依此理解。
絕緣層覆矽基底一般使用具有高電阻之操作晶圓。使用高電阻操作晶圓使絕緣層覆矽基底符合應用要件,如:裝置與裝置之隔離、被動元件品質因子(passive component Q-factors)。然而,這些高電阻操作晶圓為低摻雜,因此來自操作晶圓表面或次表面區域之載子可能沿著高電阻操作晶圓表面堆積,依上層氧化埋層中存在之電荷種類形成累積(accumulation)或反向層(inversion layer)。施加至上層主動矽薄層中之裝置的電壓可與累積層交互作用產生寄生表面傳導(parasitic surface conduction),其引發裝置對裝置的串音(cross-talk)及/或射頻訊號之非線性失真(non-linear distortions)。
為了避免此種非線性失真,絕緣層覆矽基底可包括配置以(configured to)捕捉載子之富阱層(trap-rich layer),其設置於操作晶圓及絕緣層之間。一般在將操作晶圓接合至主動矽晶圓前,經由沉積富阱材料於操作晶圓上形成富阱層。舉例而言,可在將操作晶圓接合至主動矽晶圓前,經由沉積一層多晶矽層於操作晶圓上形成富阱層。然而,以這樣的方式形成富阱層不甚理想,因其在製程中引入額外的成本,且使絕緣層覆矽基底具有熱不穩定性(thermal instability)[例如:高溫前段(front end of line,FEOL)製程可能影響多晶矽之結晶結構及其與操作晶圓之交界面(interface),降低多晶矽層之捕捉性質]。
因此,本揭露係關於絕緣層覆矽基底及其相關之
形成方法,此絕緣層覆矽基底具有包括結晶缺陷之富阱層,且此富阱層設置於操作晶圓中。於一些實施例中,絕緣層覆矽基底包括操作晶圓。富阱層係設置於操作晶圓中,其位置係自操作晶圓頂表面延伸至操作晶圓中下層之結晶層,且富阱層包括多個配置以捕捉載子之結晶缺陷。絕緣層係設置於操作晶圓之上。此絕緣層在與富阱層之交界面處具有毗接(abut)操作晶圓頂表面之第一側,及毗接主動矽薄層之相反的第二側。藉由將富阱層形成於操作晶圓中,可降低沉積富阱層材料(例如:多晶矽)於操作晶圓上之相關製造成本,並避免熱不穩定性問題。
第1圖繪示一些實施例剖面圖,其中絕緣層覆矽基底(SOI基底)100具有包括多個結晶缺陷的富阱層106,且富阱層106設置於操作晶圓102中。
SOI基底100包括操作晶圓102。在一些實施例中,操作晶圓102可包括高電阻矽操作晶圓(亦即,具有高於1kΩ-cm之電阻的矽晶圓)。設置絕緣層108(例如:熱氧化物層)於操作晶圓102上。絕緣層108具有毗接操作晶圓102頂表面106a之第一側108a及毗接主動矽薄層110之相反的第二側108b。在一些實施例中,操作晶圓102之頂表面106a可能受損而使操作晶圓102之原子被取代。經取代的原子使得操作晶圓102之頂表面106a成為粗糙表面而具有突出部延伸至上層絕緣層108中。
絕緣層108係配置以使主動矽薄層110與操作晶圓102電性隔離。於一些實施例中,絕緣層108可包括熱氧化物層[例如:二氧化矽(SiO2)]。在一些實施例中,主動矽薄層110可
包括一或多個半導體裝置。舉例而言,主動矽薄層110可包括被動元件及/或具有一或多個場效電晶體之射頻轉換器(RF switch)。
富阱層106係設置於操作晶圓102中,其位於毗接絕緣層108之處。在一些實施例中,富阱層106自操作晶圓102之頂表面106a延伸至操作晶圓102中之下層結晶層104。富阱層106包括多個結晶缺陷。在一些實施例中,富阱層106可包括結晶缺陷,其包括錯位(亦即:原子脫離位置或在結晶晶格中未對齊之區域)及/或氧化引致疊差(oxidation induced stacking fauts,OISF)。此結晶缺陷係配置以捕捉載子(例如:來自絕緣層中)之再結合中心(recombination centers)。一旦載子被再結合中心捕捉,其生命期(lifetime)下降。因此,經由捕捉載子於富阱層106之結晶缺陷中,得以避免載子沿操作晶圓102頂表面累積,緩和引發射頻訊號之非線性失真的寄生表面傳導。
第2圖繪示一些實施例之剖面圖,其中SOI基底200具有設置於矽操作晶圓202中的富阱層204,而富阱層204中包括氧化引致疊差206或錯位的結晶缺陷。
SOI基底200具有富阱層204,其包括刻意以不適當之預氧化回火(pre-oxidation anneal)(例如:於非晶矽區域上進行預氧化回火)及後續氧化製程所引起的結晶缺陷。富阱層204係設置於結晶層104及絕緣層108之間。在一些實施例中,富阱層204可包括植入矽操作晶圓202中以形成非晶矽材料之摻質殘餘物(a remnant of a dopant species)。在不同實施例中,摻質殘餘物可包括氬(Ar)、碳(C)及/或(Ge)。
富阱層204包括氧化引致疊差206及錯位。氧化引致疊差206及錯位可能自絕緣層108之底表面(例如:第一側108a)延伸至富阱層204中。在一些實施例中,氧化引致疊差206及錯位可沿(111)平面延伸。由於非晶矽材料再結晶之晶格變形(distortion),氧化引致疊差206及錯位可經由露出矽表面之劃線蝕刻(delineation etch)[例如:賴特蝕刻(Wright’s etch)、射哥蝕刻(Secco’s etch)、射托蝕刻(Sirtle’s etch)]或穿透式電子顯微鏡(例如:TEM)測得。
第3圖繪示製造絕緣層覆矽基底之方法300部份實施例的流程圖,此SOI基底具有包括富阱層的操作晶圓,而富阱層包括多個結晶缺陷。方法300形成富阱層於操作晶圓中,因為沒有額外沉積富阱層於操作晶圓上,可藉此在SOI基底形成上提供低成本。
以下將以一系列之動作或事件繪示或描述方法300,應了解的是,此些動作或是件之繪示順序並非意圖限制本揭露。舉例而言,部份動作可以不同順序發生及/或與本文所描述之步驟及/或本文所描述之外的其他步驟同步(cocurrently)發生。此外,並非需要所有繪示之步驟以執行本揭露之一或多個面向或實施例。再者,文中所述之一或多個動作可於一或多個獨立的動作及/或樣態中執行。
於步驟302中,提供操作晶圓。在一些實施例中,操作晶圓可包括矽操作晶圓。在一些實施例中,操作晶圓可包括其他半導體材料[例如:III-V族半導體材料、碳化矽(silicon carbide)、矽鍺(silicon germanium)、鍺(germanium)等]。
於步驟304中,操作晶圓被損壞以於操作晶圓之頂表面中形成非晶相(受損)區域。操作晶圓之損壞係透過從操作晶圓置換原子來執行。於步驟306,在一些實施例中,損壞操作晶圓可能係經由在操作晶圓之頂表面中植入形成非晶矽區域之佈值物種,而不引入供體(donors)或受體(acceptors)至操作晶圓。於步驟308,在其他實施例中,損壞操作晶圓可能係經由機械性損壞操作晶圓之頂表面[例如:微滑痕(micro-scratching)、噴砂法(abrasive blasting)等]。
於步驟310,可執行預清潔步驟以自操作晶圓表面移除汙染物。在一些實施例中,預清潔步驟可包括標準濕式清潔步驟(RCA清潔法)。在一些實施例中,預清潔步驟可引入金屬污染物(例如:鐵原子)至操作晶圓表面。此金屬原子可作為間隙原子(interstitials)沿氧化引致疊差擴散,而使得氧化引致疊差作為載子之再結合中心。
於步驟312,於具有流動之氧化環境的高溫爐(furnace)中執行高溫熱氧化製程。高溫熱氧化製程係配置以於操作晶圓之頂表面上形成絕緣層。在一些實施例中,絕緣層可包括熱氧化物(例如:二氧化矽)。高溫熱氧化製程係更進一步配置以於操作晶圓之非晶相區域中同步形成結晶缺陷(例如:錯位及/或氧化引致疊差)。舉例而言,可經由將非晶相區域插入包括氧[例如:不含抑制結晶缺陷之含氯(chlorine)氣流]之流動氧化環境中以執行高溫熱氧化製程,而不經適宜之預回火以使非晶相層於再結晶之非晶相中形成氧化引致疊差及/或錯位。
於步驟310,將主動基底固定至絕緣層。
於步驟312,降低主動基底之厚度以形成毗接絕緣層之主動薄層。
第4-8圖繪示一些實施例之剖面圖,其顯示製造絕緣層覆矽基底之方法,其中絕緣層覆矽基底具有包括富阱層的矽操作晶圓,而富阱層包括多個結晶缺陷。雖然第4-8圖之描述係關連至方法300,應了解的是,第5-12圖所揭露之結構並不侷限於此方法,而可代表獨立於此方法之結構。
第4圖繪示對應於步驟302的一些實施例之剖面圖400。
如剖面圖400所示,提供操作晶圓402。在一些實施例中,操作晶圓402可包括高電阻矽晶圓。在此實施例中,高電阻矽晶圓包括高於或等同於1kΩ-cm之電阻值。在一些實施例中,操作晶圓402可包括具有(100)晶相之高電阻矽晶圓。在其他實施例中,操作晶圓402可包括具有不同晶相[例如:(111)晶相]之高電阻矽晶圓。
第5A-5B圖繪示一些對應步驟304之實施例的剖面圖500及508。
第5A圖繪示經佈植製程損傷之操作晶圓502的剖面圖500。經由引入佈植物質504至操作晶圓502之頂表面503執行佈植製程。佈值物質504置換操作晶圓502中之原子以形成非晶相區域506,而非晶相區域506包括沿著操作晶圓502之頂表面503設置且位於結晶層104上之非晶相層(例如:晶格中具有結晶缺陷而不具有長週期性結晶結構之膜層)。非晶相區域506
自操作晶圓502之頂表面503垂直延伸深度d至操作晶圓502中。應了解的是,非晶相區域506之深度d可經由調整一或多個佈值製程參數(例如:改變佈值製程之能量)而改變。
佈值物質504可包括電中性物質,而不引入供體或受體至操作晶圓502中。舉例而言,在一些實施例中,佈值物質504可包括氬(Ar)、矽(Si)、碳(C)及/或鍺(Ge)。在一些實施例中,使用大於或相當於約1e15/cm2之劑量及介於約1kV及約1MV範圍間之能量執行佈植製程。
第5B圖繪示經佈植製程損傷之操作晶圓502的剖面圖508。如剖面圖508所示,經由強行推入多個研磨顆粒510(例如:沙、粗拋光漿料)於操作晶圓502的頂表面上,而在操作晶圓502之頂表面503引入機械損壞。當與操作晶圓502碰撞時,研磨顆粒510置換操作晶圓502內的原子以形成設置於結晶層104上方之非晶相區域506。
應了解的是,雖然第5B圖繪示以噴砂製程形成機械損壞,但機械損壞並不限於這些製程。舉例而言,在一些實施例中,可經由對操作晶圓502進行微滑痕以於操作晶圓502之頂表面503中形成微刮痕,而在操作晶圓502中引入機械損壞。舉例而言,在一些實施例中,操作晶圓502之頂表面503可以尺寸介於1-10μm之研磨粒子(例如:鑽石)進行滑刮(scratch)。
第6圖繪示對應於步驟312的一些實施例之剖面圖600。
如剖面圖600所示,於具有包括氧化粒子602之流動氧化環境的高溫爐中執行高溫熱氧化製程。流動氧化環境沒
有抑制形成氧化引致疊差之試劑[例如:含氯(chlorine)氣流像是氫氯酸(hydrochloric acid,HCl)、三氯乙酸(trichloroacetic acid,TCA)等]。執行高溫熱氧化製程包括於氧化環境存在下將操作晶圓102暴露於高溫604,導致沿操作晶圓102之頂表面形成熱氧化物層606。因為高溫熱氧化製程之執行係提供氧原子至熱氧化物層606及操作晶圓102之交界面,熱氧化物層606消耗部分包括非晶相區域506之操作晶圓102。
高溫熱氧化製程同步形成結晶缺陷於操作晶圓102之非晶相區域506中。舉例而言,在一些實施例中,高溫熱氧化製程造成非晶相區域506再結晶,其中此再結晶矽包括氧化引致疊差及/或錯位。在這些實施例中,氧化引致疊差及/或錯位自熱氧化物層606向外延伸。於非晶相區域506中形成結晶缺陷導致非晶相區域506形成位於熱氧化物層及下方結晶矽層中間之富阱層106。富阱層106包括可作為捕捉載子之再結合中心的結晶缺陷。
在一些實施例中,高溫熱氧化製程可於具有乾氧氣或濕水氣環境之高溫爐中執行。在一些實施例中,將受損操作晶圓置於維持溫度高於550℃且包括流動氧化環境(例如:流動氧氣或水蒸氣)之高溫爐執行高溫熱氧化製程。高溫流動氧化環境可使熱氧化物層606成長,而不允許非晶相材料磊晶(epitaxial)再成長。
第7圖繪示對應於步驟314的一些實施例之剖面圖700。
如剖面圖700所示,接合主動矽基底702至操作晶
圓102。在被接合至操作晶圓102時,主動矽基底702具有厚度t1。在一些實施例中,可使用直接接合製程(direct bonding process)將主動矽基底702經由熱氧化物層606接合至操作晶圓102。
第8圖繪示對應於步驟316的一些實施例之剖面圖800。
如剖面圖800所示,降低主動矽基底702之厚度。降低主動矽基底之厚度形成毗接熱氧化物層606之主動矽薄層110(其厚度為t2,且t2<t1)。在一些實施例中,可經由執行佈植製程,沿著平行於主動矽基底702頂表面之橫向裂解面(cleaving plane)將氫植入主動矽基底702,來降低主動矽基底702之厚度。植入氫導致沿著裂解面形成氫分子(H2)及氫離子(H+),其使矽原子間之鍵結變弱。接著,施加力量以沿著裂解面切割主動矽基底702,形成主動矽薄層110。在一些實施例中,舉例而言,主動矽基底702可經由蝕刻製程降低厚度。
因此,本揭露係關於具有富阱層之SOI基底及其相關形成方法,其中富阱層包括結晶缺陷且設置於操作晶圓中。
上述列舉概述了一些實施例的特徵,以使此技藝人士對本揭露之各個面向更為明瞭。此技藝人士應了解的是,可輕易地以本揭露為基礎去設計或改良其他製程及結構,以執行與本文實施例相同之目的及/或達成相同之優點。此技藝人士亦應可理解,此類等同結構並未偏離本揭露之精神與範圍,且其可在不偏離本揭露之精神與範圍中做各種改變、取代及變化。
100‧‧‧絕緣層覆矽基底
102‧‧‧操作晶圓
104‧‧‧結晶層
106‧‧‧富阱層
106a‧‧‧頂表面
108‧‧‧絕緣層
108a‧‧‧第一側
108b‧‧‧第二側
110‧‧‧主動矽薄層
Claims (10)
- 一種絕緣層覆矽基底,包括:一操作晶圓;一富阱層,其設置於該操作晶圓中,該富阱層之位置係毗接(abut)該操作晶圓之一頂表面處,其中該富阱層包括配置以捕捉載子之多個結晶缺陷;一絕緣層,在與該富阱層之交接處具有毗接該操作晶圓之該頂表面之一第一側;以及一主動矽薄層,毗接相反於該絕緣層之該第一側之一第二側。
- 如申請專利範圍第1項所述之絕緣層覆矽基底,其中該多個結晶缺陷包括錯位或氧化引致疊差。
- 如申請專利範圍第1項所述之絕緣層覆矽基底,其中該絕緣層包括一熱氧化物層。
- 如申請專利範圍第1項所述之絕緣層覆矽基底,其中該富阱層包括一非晶矽材料,其中該非晶矽材料包括植入該操作晶圓以形成該非晶矽材料之一摻質殘餘物,其中該摻質殘餘物包括氬(Ar)、矽(Si)、碳(C)、或鍺(Ge)。
- 如申請專利範圍第1項所述之絕緣層覆矽基底,其中該操作晶圓之該頂表面係受損,其受損的方式使該操作晶圓之原子被取代,而形成具有突出部延伸至該絕緣層中之一粗頂表面。
- 如申請專利範圍第1項所述之絕緣層覆矽基底,其中該主動矽薄層包括具有一或多個場效電晶體之一射頻轉換器。
- 一種形成絕緣層覆矽基底之方法,包括:損壞一高電阻操作晶圓之一頂表面以沿該頂表面形成一非晶矽區域;執行一高溫氧化製程以同時於該非晶矽區域上形成一熱氧化物層及於該非晶矽區域中形成配置以捕捉載子之多個結晶缺陷;將一主動矽晶圓固定至該熱氧化物層;以及降低該主動矽晶圓之厚度以形成毗接該熱氧化物層之一主動矽薄層。
- 如申請專利範圍第7項所述之形成絕緣層覆矽基底之方法,其中執行該高溫氧化製程包括:將該高電阻操作晶圓插入具有一流動氧化環境之一高溫爐,而該流動氧化環境包括乾氧氣或溼水氣,其中該高溫氧化製程係於溫度維持高於550℃之一高溫爐中執行,且其不含有可抑制氧化引致疊差生成的含氯氣體。
- 如申請專利範圍第7項所述之形成絕緣層覆矽基底之方法,其中執行該高溫氧化製程包括:植入一佈植物質至該操作晶圓之該頂表面以形成包括一非晶矽層之該非晶矽區域,而不引入供體或受體至該高電阻操作晶圓中,其中該佈植物質包括氬(Ar)、矽(Si)、碳(C)、或鍺(Ge)。
- 如申請專利範圍第7項所述之形成絕緣層覆矽基底之方法,其中損壞該高電阻操作晶圓包括:於該頂表面中形成微刮痕以機械性損壞該頂表面。
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TWI755973B (zh) * | 2020-01-15 | 2022-02-21 | 美商格芯(美國)集成電路科技有限公司 | 具有背閘極觸點及埋藏高電阻層的場效電晶體 |
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CN106571389B (zh) | 2015-10-10 | 2020-08-07 | 中芯国际集成电路制造(上海)有限公司 | 晶体管及其形成方法 |
CN107275197A (zh) * | 2016-04-08 | 2017-10-20 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
US10438838B2 (en) | 2016-09-01 | 2019-10-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure and related method |
FR3062517B1 (fr) * | 2017-02-02 | 2019-03-15 | Soitec | Structure pour application radiofrequence |
US10553474B1 (en) * | 2018-08-29 | 2020-02-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming a semiconductor-on-insulator (SOI) substrate |
US11271079B2 (en) | 2020-01-15 | 2022-03-08 | Globalfoundries U.S. Inc. | Wafer with crystalline silicon and trap rich polysilicon layer |
US11289474B2 (en) | 2020-04-20 | 2022-03-29 | Globalfoundries U.S. Inc. | Passive devices over polycrystalline semiconductor fins |
CN112420915B (zh) * | 2020-11-23 | 2022-12-23 | 济南晶正电子科技有限公司 | 复合衬底的制备方法、复合薄膜及电子元器件 |
CN115548117A (zh) | 2021-06-29 | 2022-12-30 | 联华电子股份有限公司 | 半导体结构及其制造方法 |
CN113948446A (zh) * | 2021-09-28 | 2022-01-18 | 苏州华太电子技术有限公司 | 半导体工艺以及半导体结构 |
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US20020187619A1 (en) * | 2001-05-04 | 2002-12-12 | International Business Machines Corporation | Gettering process for bonded SOI wafers |
US20090004458A1 (en) * | 2007-06-29 | 2009-01-01 | Memc Electronic Materials, Inc. | Diffusion Control in Heavily Doped Substrates |
US7868419B1 (en) * | 2007-10-18 | 2011-01-11 | Rf Micro Devices, Inc. | Linearity improvements of semiconductor substrate based radio frequency devices |
US20130089968A1 (en) * | 2010-06-30 | 2013-04-11 | Alex Usenko | Method for finishing silicon on insulator substrates |
EP2656388B1 (en) * | 2010-12-24 | 2020-04-15 | QUALCOMM Incorporated | Trap rich layer for semiconductor devices |
US8951896B2 (en) * | 2013-06-28 | 2015-02-10 | International Business Machines Corporation | High linearity SOI wafer for low-distortion circuit applications |
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TWI755973B (zh) * | 2020-01-15 | 2022-02-21 | 美商格芯(美國)集成電路科技有限公司 | 具有背閘極觸點及埋藏高電阻層的場效電晶體 |
US11296190B2 (en) | 2020-01-15 | 2022-04-05 | Globalfoundries U.S. Inc. | Field effect transistors with back gate contact and buried high resistivity layer |
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