CN113078717A

CN113078717A - Voltage dump circuit applied to voltage sampling of multiple batteries

Info

Publication number: CN113078717A
Application number: CN202110492006.5A
Authority: CN
Inventors: 莫艳图; 田岭; 王宗民; 孔瀛; 柏晓鹤; 胡文瑞; 李阳
Original assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Current assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Priority date: 2021-05-06
Filing date: 2021-05-06
Publication date: 2021-07-06
Anticipated expiration: 2041-05-06
Also published as: CN113078717B

Abstract

The invention relates to a voltage dump circuit applied to sampling of voltages of multiple batteries, which adopts a voltage clamping principle when an MOS (metal oxide semiconductor) tube works in a stable state to sample the voltages of a positive end and a negative end of a battery, then utilizes a charge pump to control a dump switch, and simultaneously converts the sampled high voltage into low voltage according to a charge balance principle at two ends of a capacitor and transmits the low voltage to a post-stage circuit so as to realize voltage signal processing. The circuit can realize the sampling of the voltage of the single batteries in the series battery pack one by one from top to bottom, can also realize the sampling of the voltage of any single battery in the series battery pack, and is not restricted by the series quantity of the batteries in the power supply range which can be borne by the circuit. The circuit of the invention has simple structure and good compatibility with BCD technology, and is suitable for the voltage acquisition circuit of a plurality of series-connected batteries.

Description

Voltage dump circuit applied to voltage sampling of multiple batteries

Technical Field

The invention relates to a voltage dump circuit, which is characterized by realizing the collection of the voltage of a plurality of series batteries, wherein the differential mode input voltage does not exceed 5V, the common mode input voltage does not exceed the maximum working voltage of the circuit, and the voltage dump circuit is not limited by the number of the series batteries.

Background

The voltage dump circuit is an important component of a high-voltage sampling circuit and is often applied to a battery management chip for sampling the serial voltage of a plurality of batteries. In the voltage dump circuit, the voltage dump sampling control circuit is mainly used for clamping common-mode input voltages corresponding to different series battery pack positions to realize the sampling of battery voltages, a dump control signal is generated through the boosting principle of a charge pump, and the dump control signal controls the two battery voltages to be converted into low-voltage signals which can be identified by an internal comparator after the battery sampling is finished.

The traditional voltage dump circuit is realized by adopting a high-voltage process, differential mode input voltage is easily limited by threshold voltage of a PMOS (P-channel metal oxide semiconductor) tube, the range of the input voltage is narrow, and the circuit structure is relatively complex and is not beneficial to further integration of the circuit.

Disclosure of Invention

The technical problem solved by the invention is as follows: the defects in the prior art are overcome, the minimum 1V differential mode input voltage is realized by adopting a thin gate oxide PMOS tube of an advanced BCD (binary-coded decimal) process as a clamping sampling tube, and the input voltage range of the circuit is improved. The voltage dump sampling control circuit adopts a clamping mechanism of an MOS (metal oxide semiconductor) tube and a Zener diode, the control voltage is improved through the charge pump principle, the control of a dump switch is realized, and the circuit complexity is reduced. The voltage dump switch circuit adopts a principle of charge balance at two ends of a capacitor, the charge of a capacitor plate of an input stage is balanced after a dump switch is closed, the charge of an output plate is changed along with the change of the voltage of an input plate, the voltage is dumped from high voltage to low voltage, and the complexity of the circuit is further reduced due to the structure that two MOS (metal oxide semiconductor) tubes are added with two capacitors.

The technical solution of the invention is as follows: a voltage dump circuit applied to voltage sampling of a plurality of batteries comprises a voltage dump sampling control circuit and a voltage dump switch circuit;

the voltage dump sampling control circuit is used for generating a switching-on/off signal for controlling the voltage dump switch and ensuring that the control signal is adjusted along with the change of the input sampling voltage;

the voltage dump switch circuit is used for converting the sampled voltage into a low-voltage signal by a charge balance principle and transmitting the low-voltage signal to the internal signal processing circuit.

The voltage dump sampling control circuit comprises a PMOS tube P1, a PMOS tube P2, a PMOS tube P3, a PMOS tube P4, a PMOS tube P5, an NMOS tube N1, an NMOS tube N2, an NMOS tube N3, an NMOS tube N4, an NMOS tube N5, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a Zener diode D1, a capacitor C1, a constant current source I1 and a constant current source I2;

a gate terminal of an NMOS tube N1 is connected with a control signal S1, a source terminal of an NMOS tube N1 is connected with a positive terminal of a constant current source I1, a drain terminal of an NMOS tube N1 is connected with a drain terminal and a gate terminal of a PMOS tube P1, a gate terminal of the PMOS tube P2 and a positive terminal of the constant current source I2, a negative terminal of the constant current source I2 and a negative terminal of the constant current source I2 are connected with GND, a source terminal of the PMOS tube P2 and a source terminal of the PMOS tube P2 are connected with VCC, a drain terminal of the PMOS tube P2 is connected with a drain terminal and a gate terminal of the NMOS tube N2, a top terminal of a resistor R2 is connected with VCC, a bottom terminal of the resistor R2 is connected with a drain terminal of the NMOS tube N2, a drain terminal of the NMOS tube N2 and a drain terminal of the PMOS tube P2, a drain terminal of the NMOS tube N2 is connected with a drain terminal of the NMOS tube N2, a drain terminal of the PMOS tube P2, a drain terminal of the PMOS, the negative end of a Zener diode D1 is connected with the left end of a resistor R3 and the drain end of an NMOS tube N5, the gate end of the NMSO tube N5 is connected with a control signal S2, the source end of the NMOS tube N5 is connected with the top end of a resistor R4, the bottom end of the resistor R4 is connected with GND, the right end of the resistor R3 and the top end of a capacitor C1 are connected with a dump switch control signal S4, the bottom end of the capacitor C1 is connected with the control signal S3, the drain ends of a PMOS tube P4 and a PMOS tube P5 are connected with GND, the gate end of the PMOS tube P4 is connected with a battery input signal VI + end, and the gate end of the PMOS tube P5 is connected with the battery input signal VI-end.

The voltage dump switch circuit comprises an NMOS transistor N6, an NMOS transistor N7, a capacitor C2 and a capacitor C3;

the source end of an NMOS tube N6 is connected with the source end of an NMOS tube N7, the gate end of an NMOS tube N6 and the gate end of the NMOS tube are connected with a control signal S4, the drain end of the NMOS tube N6 and the left end of a high-voltage capacitor C2 are connected with a battery input signal VI +, the drain end of an NMOS tube N7 and the left end of the high-voltage capacitor C3 are connected with a battery input signal VI-, the right end of the high-voltage capacitor C2 is connected with an internal signal VO +, and the right end of a high-voltage capacitor C3 is connected with the internal signal VO-.

Compared with the prior art, the invention has the beneficial effects that:

(1) compared with the traditional voltage dump circuit, the input stage structure of the main body of the invention adopts the symmetrical design of the PMOS tubes with high voltage resistance, and the two input ends of the circuit are completely equivalent according to the low voltage clamping principle, namely the voltage of the VI + end can be larger than the voltage of the VI-end and can also be smaller than the voltage of the VI-end. In addition, the thin gate oxide PMOS tube is adopted, the gate source voltage for clamping is also reduced, and the range of differential mode input voltage is improved.

(2) The dump switch comprises two high-voltage-resistant NMOS tubes which are connected in a source end butt joint mode, drain ends of the two NMOS tubes are respectively connected to VI + and VI-, an NMOS tube structure with two high-voltage-resistant ends is realized, and the common-mode voltage range of dump signals is enlarged.

(3) The Zener diode structure is introduced into the dump switch control circuit, and the forward conduction voltage drop of the Zener diode structure is used for quickly establishing a working point in the acquisition process of the control circuit so as to ensure that the dump switch is in a closed state. The reverse conducting characteristic of the Zener diode enables the dump switch signal to be clamped at a relatively low voltage, the gate voltage of the dump switch is ensured not to be over-voltage, and the reliability of the circuit is improved.

(4) The circuit structure is mainly realized based on a process containing Bipolar, CMOS and DMOS, the compatibility of high voltage and low voltage of the circuit is improved, the single-chip integration level of the high-voltage analog switch and the low-voltage analog-to-digital converter is greatly improved, and the packaging complexity of the circuit is reduced.

Drawings

FIG. 1 is a schematic diagram of a voltage dump circuit.

Fig. 2 is a waveform diagram of a control signal of the present invention.

Detailed Description

FIG. 1 is a schematic diagram of a voltage dump circuit, including a voltage dump sampling control circuit and a voltage dump switch circuit. When the input voltages VI + and VI-are applied to the circuit and stabilized, if VI + is greater than VI-, the voltage V at point A is_ADue to the clamping of the PMOS pipe P4, the voltage is higher than VI-by one grid source voltage, if VI + is less than VI-, V_AIt is one gate-source voltage higher than VI +. Assuming VI is the minimum of VI + and VI-, the gate-source voltage of the PMOS transistor P4 is V_GSP4Then, there are:

V_A＝VI+V_GSP4

in the steady state, V_AReducing a gate-source voltage through an NMOS transistor N4 to obtain V_BAccording to the clamping mechanism of the diode, V_BReducing a diode conduction voltage drop V by a Zener diode D1_DThereby obtaining a dump control voltage V_CSuppose the gate-source voltage of the NMOS transistor N4 is V_GSN4Then, there are:

V_C＝V_A-V_GSN4-V_D＝VI+V_GSP4-V_GSN4-V_D

according to the circuit design requirement, the PMOS tube P4 and the NMOS tube N4 are designed in a matching way, so that V is enabled to be V_GSP4And V_GSN4Equal, then there are:

V_C＝VI-V_D

thus, the steady state operating point of the voltage dump circuit is: dump switch control terminal voltage V_CThe voltage of the input end VI is lower than that of the input end VI by a diode conduction voltage drop, and at the moment, both the NMOS tube N6 and the NMOS tube N7 are not connectedOn and off.

After the dump voltage sampling is completed, the circuit can dump, at this time, signals are no longer connected to the input ends VI + and VI-of the circuit, and the charge pump starts to work, namely the control end S3 of the capacitor C1 is changed from low level 0V to high level 5V, and according to the charge pump principle, V is changed into V according to the charge pump principle_CThe voltage of the capacitor C2 and the capacitor C3 is driven to be 5V, so that the NMOS transistor N6 and the NMOS transistor N7 are conducted, the voltage of VI + and VI-is pulled to the same potential, the charges on the left pole plates of the capacitor C2 and the capacitor C3 are transmitted to the right pole plate, and the charges enter an internal low-voltage circuit to dump the voltage.

In order to ensure the working continuity of the circuit dump circuit, after each dump is completed, a narrow pulse signal needs to be provided to the input signal S2 to make the NMOS transistor N5 conductive and turn V on_CIs discharged so that V_CThe voltage of the transistor N is decreased to turn off the NMOS transistor N6 and the NMOS transistor N7. To ensure that NMOS transistor N6 and NMOS transistor N7 are completely in the OFF state, V_CWill be properly over-bled, so the power supply VCC is required to be coupled to V through the resistor R1, the NMOS transistor N4 and the zener diode D1 before the next dump begins_CUntil V is properly charged_CThe voltage reaches the steady-state working point (V) of the next working_C＝VI-V_D)。

After the first voltage dump is completed, VI + and VI-are pulled to the same level, and the VI voltage is pulled up, according to the clamping principle of the PMOS transistor P5, V_AThe voltage will also be increased, like V_BThe voltage also becomes large. If V_BToo high a voltage will result in V_CThe voltage cannot be discharged excessively, so that the NMOS transistor N6 and the NMOS transistor N7 cannot be completely turned off in a short time. Therefore, after the input signals VI + and VI-are disconnected from the signal source, a high-level narrow pulse input signal S1 needs to be introduced to turn on the NMOS transistor N1, so that the current flowing through the PMOS transistor P1 becomes I1+ I2, after current mirroring, the currents flowing through the PMOS transistor P2, the PMOS transistor P3, the NMOS transistor N2 and the NMOS transistor N3 all become I1+ I2, and due to the increase of the current of the NMOS transistor N3, V is changed to be 1+ I2_BThe voltage is pulled down properly, counteracting V introduced by the next voltage dump_BThe voltage is increased to ensure that the control circuit is in a steady-state working point (V) after each dump_C＝VI-V_D). The timing relationship of the signal S1, the signal S2, and the signal S3 is shown in fig. 2, in which the switching waveforms of the input signals VI + and VI-connected and disconnected are added to fig. 2 (high level indicates that the switch is closed, and low level indicates that the switch is open).

Resistor R1 in FIG. 1 is used to regulate VCC to V_CThe charging speed is controlled by a resistor R2 for regulating the speed of VCC charging the gate terminal of NMOS transistor N4 via PMOS transistor P3, and a resistor R3 for controlling V_CThe resistance R4 is mainly used for regulating V_CThe discharge rate of (2). The PMOS tube P1, the PMOS tube P2 and the PMOS tube P3 form a cascode PMOS tube current mirror, and the NMOS tube N2 and the NMOS tube N3 form a cascode NMOS tube current mirror.

The invention is not described in detail and is within the knowledge of a person skilled in the art.

Claims

1. A voltage dump circuit applied to voltage sampling of a plurality of batteries is characterized in that: the device comprises a voltage dump sampling control circuit and a voltage dump switch circuit;

2. The voltage dump circuit applied to sampling of voltages of a plurality of batteries according to claim 1, wherein: the voltage dump sampling control circuit comprises a PMOS tube P1, a PMOS tube P2, a PMOS tube P3, a PMOS tube P4, a PMOS tube P5, an NMOS tube N1, an NMOS tube N2, an NMOS tube N3, an NMOS tube N4, an NMOS tube N5, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a Zener diode D1, a capacitor C1, a constant current source I1 and a constant current source I2;

3. The voltage dump circuit applied to sampling of voltages of a plurality of batteries according to claim 1, wherein: the voltage dump switch circuit comprises an NMOS transistor N6, an NMOS transistor N7, a capacitor C2 and a capacitor C3;