CN113053888A - 集成电路 - Google Patents

集成电路 Download PDF

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Publication number
CN113053888A
CN113053888A CN202011276805.0A CN202011276805A CN113053888A CN 113053888 A CN113053888 A CN 113053888A CN 202011276805 A CN202011276805 A CN 202011276805A CN 113053888 A CN113053888 A CN 113053888A
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layer
gate
thickness
region
channel member
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CN202011276805.0A
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Inventor
吴沛勳
韩铭鸿
陈柏年
林志勇
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

在此提供一种集成电路和半导体装置。此半导体装置包括基板；位于基板上的输入/输出装置；位于基板上的核心装置。此输入/输出装置包括第一栅极结构，其具有界面层；第一高介电常数介电质堆叠，其位于界面层上；以及导电层，其位于第一高介电常数介电质堆叠上并与之物理接触。核心装置包括包括第二栅极结构，其具有界面层；第二高介电常数介电质堆叠，其位于界面层上；以及导电层，其位于第二高介电常数介电质堆叠上并与之物理接触。第一高介电常数介电质堆叠包括第二高介电常数介电质堆叠及第三介电层。

Description

集成电路
技术领域
本发明实施例涉及一种集成电路装置，且特别涉及一种具有不同厚度的栅极介电层的集成电路装置及其制造方法。
背景技术
半导体集成电路工业已经历快速成长。集成电路的材料和设计方面的技术进步已经产生了数代的集成电路，其中每一代都比上一代具有更小且更复杂的电路。在集成电路的发展过程中，随着几何尺寸(亦即，利用工艺所制造的最小装置尺寸或线宽)的降低，功能密度(functional density，亦即，每一芯片面积中内连接的装置数量)已普遍增加。尺寸缩减的工艺具有提升生产效率及降低相关成本的优点。然而，随着如此的尺寸缩减，加工与制造集成电路的复杂性也随之增加。
举例而言，随着集成电路技术朝着更小的技术节点发展，已经导入多栅极(multi-gate)装置，以通过增加栅极-通道耦合(gate-channel coupling)、降低截止状态电流(off-state current)及降低短通道效应(short-channel effects,SCEs)，而改善栅极控制。多栅极装置通常是指以下的装置：具有栅极结构或其一部分设置在通道区域的多于一侧上。全绕式栅极(gate-all-around,GAA)晶体管是多栅极装置的示范例，在高性能和低漏电流的应用中，这些多栅极装置已成为普遍且有潜力的候选方案。与平面式晶体管相比，如此的配置方式提供了优选的通道控制，并且大幅降低了短通道效应(特别是，通过降低次临界漏电流(sub-threshold leakage))。全绕式栅极晶体管具有部分地或完全地围绕通道区域而延伸的栅极结构，而可从每一侧提供对通道区域的存取。全绕式栅极晶体管的通道区域可以由纳米线(nanowire)、纳米片(nanosheet)、其他纳米结构及/或其他合适的结构所形成。在一些实施例中，如此的通道区域包含垂直堆叠的多个纳米线(其水平延伸，而提供水平配向的沟道)。
集成电路装置包括具有不同功能的晶体管，例如，输入/输出功能及核心功能。这些不同的功能要求晶体管具有不同的结构。同时，具有相似的工艺与相似的工艺视窗以制造这些不同的晶体管而降低成本及改善良率是有利的。虽然现有的全绕式栅极晶体管及工艺已普遍能够符合其预期目的，然而其仍无法完全满足所有方面的需求。举例而言，不同的核心功能(例如，高速应用与低功率(及/或低漏电流)应用)可能会需要全绕式栅极晶体管的不同栅极介电层厚度。因此，如何持续缩小用于具有不同栅极介电层厚度以适合不同应用的输入/输出装置与核心装置的栅极堆层是半导体行业面临的挑战。本公开的目标在于解决以上问题及其他相关问题。
发明内容
本公开的一实施例是公开一种集成电路，包括：基板，具有第一区域及第二区域；第一全绕式栅极装置，位于第一区域中，其中第一全绕式栅极装置包括：第一通道构件，在第一方向上纵向延伸；以及第一栅极结构，包裹第一通道构件的通道区域，其中第一栅极结构包括第一界面层，第一界面层具有在大致垂直于第一方向的第二方向上所测量到的第一厚度；第二全绕式栅极装置，位于第一区域中，其中第二全绕式栅极装置包括：第二通道构件，在第一方向上纵向延伸；以及第二栅极结构，包裹第二通道构件的通道区域，其中第二栅极结构包括第二界面层，第二界面层具有在第二方向上所测量到的第二厚度，且第二厚度大于第一厚度；以及第三全绕式栅极装置，位于第二区域中，其中第三全绕式栅极装置包括：第三通道构件，在第一方向上纵向延伸；以及第三栅极结构，包裹第三通道构件的通道区域，其中第三栅极结构包括第三界面层，第三界面层具有在第二方向上所测量到的第三厚度，且第三厚度大于第二厚度。
本公开的一实施例是公开一种集成电路装置，包括：核心装置，包括：第一通道构件；第一栅极结构，与第一通道构件啮合，其中第一栅极结构包括第一界面层，其中第一界面层包裹第一通道构件的通道区域；第二通道构件；以及第二栅极结构，与第二通道构件啮合，其中第二栅极结构包括第二界面层，其中第二界面层包裹第二通道构件的通道区域，其中第二界面层在大致垂直于第二通道构件的纵轴的方向上的厚度大于第一界面层在大致垂直于第一通道构件的纵轴的方向上的厚度；以及输入/输出装置，包括：第三通道构件；以及第三栅极结构，与第三通道构件啮合，其中第三栅极结构包括第三界面层，其中第三界面层包裹第三通道构件的通道区域，其中第三界面层在大致垂直于第三通道构件的纵轴的方向上的厚度的厚度大于第二界面层的厚度。
本公开的一实施例是公开一种集成电路装置的制造方法，包括：提供基板，其中基板具有第一通道构件、第二通道构件及第三通道构件，其中第一通道构件及第二通道构件位于集成电路的核心区域中，且第三通道构件位于集成电路的输入/输出区域中；通过第一工艺以形成第一氧化物层及第二氧化物层，其中第一氧化物层包裹第一通道构件的通道区域，且第二氧化物层包裹第二通道构件的通道区域；通过不同于第一工艺的第二工艺，以形成第三氧化物层包裹第三通道构件的通道区域；分别形成第一介电层、第二介电层及第三介电层于第一氧化物层、第二氧化物层及第三氧化物层上，分别形成第一盖层、第二盖层及第三盖层于第一介电层、第二介电层及第三介电层上，移除第二盖层以暴露出第二介电层，其中在移除第二盖层之后，第一盖层及第三盖层分别保留于第一介电层及第三介电层上；以及在移除第二盖层之后，进行退火工艺以增加第二氧化物层的厚度。
附图说明
依据以下的详细说明并配合说明书附图做完整公开。应注意的是，依据本产业的一般作业，附图并未必按照比率绘制。事实上，可能任意的放大或缩小元件的尺寸，以做清楚的说明。
图1A及图1B是依据一些实施例的半导体装置的示意性方框图及用于输入/输出及核心装置的三个栅极堆叠的相应的局部剖面示意图。
图2A及图2B是依据一些实施例的用于形成如图1A及图1B所示出的半导体装置的方法的流程图。
图3是依据一些实施例的半导体装置的透视示意图。
图4、图5、图6、图7、图8、图9、图10、图11、图12、图13、图14、图15、图16、图17及图18是依据一些实施例的半导体装置在图2A及图2B所述的方法的工艺期间的剖面示意图。
其中，附图标记说明如下：
10：半导体结构(集成电路)
12：核心区域
14：输入/输出区域
16：装置区域
18：全绕式栅极装置
20：全绕式栅极装置
22：装置区域
24：第三全绕式栅极装置
26：通道构件
27：基板
28a：栅极介电层
28b：栅极介电层
28c：栅极介电层
30a：界面层
30b：界面层
30c：界面层
32a：高介电常数介电层
32b：高介电常数介电层
32c：高介电常数介电层
36：隔离结构
100：方法
102：操作步骤
104：操作步骤
106：操作步骤
108：操作步骤
110：操作步骤
112：操作步骤
114：操作步骤
116：操作步骤
118：操作步骤
120：操作步骤
122：操作步骤
124：操作步骤
126：操作步骤
200：半导体结构(半导体装置)
202：第一区域(核心区域)
204：第二区域(输入/输出区域)
206a：装置结构(全绕式栅极核心装置结构)
206b：装置结构(全绕式栅极核心装置结构)
206c：装置结构(全绕式栅极输入/输出装置结构)
208：基板
210：隔离结构
212a：鳍片(经堆叠鳍片)
212b：鳍片(经堆叠鳍片)
212c：鳍片(经堆叠鳍片)
216：虚置栅极结构
220：半导体层(纳米线)
222：半导体层
230：虚置界面层
232：虚置栅极电极
234：第一栅极硬掩模层
236：第二栅极硬掩模层
238：栅极间隔物
240：源极/漏极部件
242：接触蚀刻停止层
244：层间介电层
246：栅极沟槽
248：界面层
249：掩模层
250a：栅极介电层
250b：栅极介电层
250c：栅极介电层
252a：界面层
252b：界面层
252c：界面层
254a：高介电常数介电层
254b：高介电常数介电层
254c：高介电常数介电层
260：盖层(厚度调整层)
261：掩模层
270：退火工艺
271：退火工艺
272：部分
274：氧原子的运动
276：非晶硅层
282：栅极电极层
P1：通道节距
S1：间隔
TIL1：厚度
TIL2：厚度
TIL3：厚度
具体实施方式
以下的公开内容提供许多不同的实施例或范例以实施本公开的不同部件(feature)。以下的公开内容叙述各个构件及其排列方式的特定范例，以简化说明。当然，这些特定的范例并非用以限定。例如，若是本说明书叙述了一第一部件形成于一第二部件之上或上方，即表示其可能包括上述第一部件与上述第二部件是直接接触的实施例，亦可能包括了有额外的部件形成于上述第一部件与上述第二部件之间，而使上述第一部件与第二部件可能未直接接触的实施例。另外，以下公开的不同范例可能重复使用相同的参照符号及/或标记。这些重复为了简化与清晰的目的，并非用以限定所讨论的不同实施例及/或结构之间有特定的关系。
再者，其中可能用到与空间相对用词，例如“在……之下”、“下方”、“较低的”、“上方”、“较高的”等类似用词，是为了便于描述附图中一个(些)部件或特征与另一个(些)部件或特征之间的关系。空间相对用词用以包括使用中或操作中的装置的不同方位，以及附图中所描述的方位。当装置被转向不同方位时(旋转90度或其他方位)，其中所使用的空间相对形容词也将依转向后的方位来解释。此外，除非另有定义，否则当使用“大约”、“近似于”或其他类似的用语等描述一个数值或一个数值范围时，此术语旨在涵盖在包括所述数值的+/-10％的范围内的数字。举例而言，技术用语“大约5nm”涵盖从4.5nm至5.5nm的尺寸范围。
本公开整体而言涉及半导体装置，更具体而言，涉及在同一基板上具有输入/输出(I/O)装置(或晶体管)与拥有纳米线通道的核心装置(或晶体管)的集成电路(IC)。在一实施例中，至少两个具有经过堆叠的纳米线通道的全绕式栅极(gate-all-around,GAA)装置被放置在集成电路的核心区域中，例如，分别用于实现高速应用与低功率(及/或低漏电流)应用，同时将第三个全绕式栅极装置放置在集成电路的输入/输出区域中，以实现输入/输出应用(包括静电放电(electrostatic discharge,ESD)应用)。
输入/输出区域的操作电压可以相似于外部电压(外部/周边电路的电压电平(voltage level))，并且高于核心区域的操作电压。为了适应更高的操作电压，与核心区域中的晶体管相比，输入/输出区域中的晶体管可具有较厚的栅极介电层。在核心区域，晶体管的栅极介电层的厚度与电路速度及漏电流性能相关。随着栅极介电层较薄，则全绕式栅极装置较适合于高速应用。随着栅极介电层较厚，则全绕式栅极装置较适合于低功率(及/或低漏电流)应用。在其他实施例中，用于高速应用的全绕式栅极装置具有比用于低功率(及/或低漏电流)应用的全绕式栅极装置更薄的栅极介电层。本公开的实施例提供了灵活的设计整合方案，以适应同一集成电路中的不同电路。根据本公开的制造方法可以容易地整合到现有的半导体制造流程中。参照图1A到图18描述本公开的各个实施例的细节。
请同时参照图1A及图1B，其中示出根据本公开的实施例所制造的半导体结构10(例如，集成电路10)的示意性方框图。集成电路10包括核心区域12及输入/输出区域14。核心区域12包括逻辑电路、存储器电路及其他核心电路。输入/输出区域14包括输入/输出单元、静电放电单元及其他电路。核心区域12包括装置区域16，且全绕式栅极装置18及全绕式栅极装置20形成于装置区域16中。在一些实施例中，如图1B所示出，全绕式栅极装置18与全绕式栅极装置20彼此相邻放置(或邻接)，其中图1B是局部剖面示意图。在一些其他实施例中，全绕式栅极装置18与全绕式栅极装置20彼此隔开，例如，通过位于两者之间或在核心区域12的不同装置区域中的其他全绕式栅极装置而彼此隔开。输入/输出区域14包括装置区域22，且第三全绕式栅极装置24形成于装置区域24中。全绕式栅极装置24位于与全绕式栅极装置18及20相距一间隔“S1”的位置。在所示出的实施例中，间隔S1是全绕式栅极装置18或20的栅极节距(gate pitch)的至少4倍或全绕式栅极装置18或20的通道节距(channelpitch)的至少4倍。可以使用两个相邻的栅极或通道之间的中心到中心距离(center-to-center distance)或边缘到边缘距离(edge-to-edge distance)，以定义栅极节距及通道节距。在图1B中示出例示性的通道节距P1，其为两个相邻通道之间的边缘到边缘距离。间隔S1被设计为通过在将装置区域16及22图案化时提供裕度(margin)，以简化工艺。
三个全绕式栅极装置18、20及24中的每一个均包括在基板27上方垂直堆叠的多个通道构件26。隔离结构36形成于基板27中且相邻于全绕式栅极装置18、20及24。在每一个全绕式栅极装置中的通道构件26的数量可以在2到10的范围内。每一个通道构件26包括硅或其他合适的半导体材料。全绕式栅极装置18的通道构件26被栅极介电层28a围绕，此栅极介电层28a可以包括界面层30a及高介电常数(high-k)介电层32a。全绕式栅极装置20的通道构件26被栅极介电层28b围绕，此栅极介电层28b可以包括界面层30b及高介电常数介电层32b。全绕式栅极装置24的通道构件26被栅极介电层28c围绕，此栅极介电层28c可以包括界面层30c及高介电常数介电层32c。栅极电极(未示出)包裹在每个栅极介电层28a、28b及28c周围或上方。栅极电极可以包括一个或多个功函数金属层及块材(bulk)金属层。在本实施例中，全绕式栅极装置18与20共用相同的栅极电极，并且全绕式栅极装置24具有分离的栅极电极。
全绕式栅极装置18、20及24具有不同的栅极介电层厚度。举例而言，输入/输出区域14中的全绕式栅极装置24包括具有第一厚度(电容等效厚度(capacitance equivalentthickness,CET))的栅极介电层28c，此第一厚度是适合于高电压应用的最厚的栅极介电层。核心区域12中的全绕式栅极装置20包括具有第二厚度的栅极介电层28b，此第二厚度是适合于低功率及低漏电流应用的中等厚度(中等电容等效厚度)。核心区域12中的全绕式栅极装置18包括具有第三厚度的栅极介电层28a，此第三厚度是最适合于高速应用的最薄的栅极介电层(最薄的电容等效厚度)。因此，集成电路10可以被称为三栅极晶体管(tri-gatetransistor)装置。在其他实施例中，在栅极介电层28a、28b及28c之中，高介电常数介电层32a、32b及32c可以具有实质上相同的物理厚度(例如，从大约
Figure BDA0002779338950000091
到大约
Figure BDA0002779338950000092
)，而界面层30a、30b及30c具有不同的物理厚度。作为示范例，界面层30b可以比界面层30a更厚约10％至约20％。如果界面层30b的厚度比界面层30a的厚度更厚的程度小于10％，则漏电流问题可能会开始降低电路性能；如果界面层30b的厚度比界面层30a的厚度更厚的程度大于20％，则核心装置的速度可能会减慢太多。界面层30c的厚度可以是界面层30a的厚度的约2倍至约4倍。如果界面层30c的厚度比界面层30a的厚度更厚的程度小于约2倍，则高电压性能将降低；界面层30c的厚度将降低。如果界面层30c的厚度比界面层30a的厚度更厚的程度大于4倍，则由于氧化物厚度很大，输入/输出装置的栅极驱动能力(gate drivecapability)变弱。在一个特定的例子中，界面层30a的厚度在从大约
Figure BDA0002779338950000094
(埃)到大约
Figure BDA0002779338950000093
之间的范围，界面层30b的厚度与界面层30a的厚度的比率为约1.1∶1到约1.2∶1，且界面层30c的厚度在从大约
Figure BDA0002779338950000095
到大约
Figure BDA0002779338950000096
之间的范围。
图2A及图2B是依据本公开的各个实施例的用于形成三栅极晶体管装置的方法100的流程图。下文将结合图3到图17描述图2A及图2B，其中图3到图17是根据方法100在制造的各个阶段的工件的局部剖面示意图。方法100仅是示例，并且不意图将本公开限制于权利要求中明确记载的范围之外。可以在方法100之前、之间及之后提供额外的步骤，并且对于方法100的附加实施例，可以移动、替换或省略所述的一些步骤。可以在图3到图17所示出的半导体装置中添加额外的部件，并且在半导体装置的其他实施例中，可以替换、修改或省略下文所描述的某些部件。
在操作步骤102中，方法100(图2A)提供包括第一区域202及第二区域204的半导体结构200(或半导体装置200)，如图3所示出。区域202及204中的每一个包括装置区域，此装置区域包括提供不同功能的晶体管。在一些实施例中，第一区域202是核心区域，且第二区域204是输入/输出(I/O)区域。在那些实施例中，核心装置区域是指包括逻辑单元(例如，逆变器(inverter)、反及闸(NAND)、反或闸(NOR)、及闸(AND)、或闸(OR)、触发器(Flip-Flop))以及存储器单元(例如，静态随机存取存储器(SRAM)的装置区域、动态随机存取存储器(DRAM)及快闪存储器(Flash))。输入/输出装置区域是指中介于核心装置区域与外部/周边电路(例如，位于印刷电路板(PCB)上有半导体装置200安装于其上的电路)之间的装置区域。在所示出的实施例中，核心区域202包括用于高速应用的全绕式栅极核心装置结构206a及用于低功率与低漏电流应用的全绕式栅极核心装置结构206b。输入/输出区域204包括用于输入/输出或静电放电应用的全绕式栅极输入/输出装置结构206c。
装置结构206a、206b及206c中的每一个包括基板208、隔离结构210、鳍片212a、212b或212c、以及虚置栅极结构216，其中鳍片212a、212b或212c包括垂直堆叠的交替的半导体层220及222(也称为经堆叠鳍片212a、212b或212c)，且虚置栅极结构216与经堆叠鳍片212a、212b或212c啮合。
在一些实施例中，基板208包括硅。替代地或额外地，基板208包括另一种元素半导体(例如，锗)；化合物半导体(例如，碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、锑化铟及/或锑化铟)；合金半导体(例如，硅锗(SiGe)、磷砷化镓(GaAsP)、砷化铟铝(AlInAs)、砷化镓铝(AlGaAs)、砷化铟镓(GaInAs)、磷化铟镓(GaInP)及/或砷磷化铟镓(GaInAsP))；或上述的组合。在一些实施例中，基板208包括一种或多种III-V族材料、一种或多种II-IV族材料或上述的组合。在一些实施例中，基板208是绝缘体上覆半导体(semiconductor-on-insulator)基板，例如，绝缘体上覆硅(silicon-on-insulator,SOI)基板、绝缘体上覆硅锗(silicongermanium-on-insulator,SGOI)基板或绝缘体上覆锗(germanium-on-insulator,GOI)基板。可通过使用氧注入隔离(separation by implantation of oxygen,SIMOX)、芯片接合及/或其他合适的方法，而制造绝缘体上覆半导体基板。基板208可包括依据半导体装置200的设计需求而配置的各种掺杂区域。P型掺杂区域可以包括p型掺质，例如，硼、铟、其他p型掺质或上述的组合。N型掺杂区可以包括n型掺质，例如，磷、砷、其他n型掺质或上述的组合。在一些实施例中，基板208包括由p型掺质及n型掺质的组合所形成的掺杂区域。各种掺杂区域可直接形成在基板208上及/或基板208中，例如，提供p型井结构、n型井结构、双重井(dual-well)结构、凸起结构或上述的组合。可进行离子布植工艺、扩散工艺及/或其他合适的掺杂工艺，以形成各种掺杂区域。在一些实施例中，在n型井之上形成p型全绕式栅极装置及p型鳍式场效晶体管装置，而在p型井之上形成n型全绕式栅极装置及n型鳍式场效晶体管装置。装置结构206a、206b及206c中的每一个可以各自独立地为n型或p型装置。
隔离结构210可以包括氧化硅、氮化硅、氮氧化硅、掺杂氟的硅酸盐玻璃(fluoride-doped silicate glass,FSG)、低介电常数(low-k)介电材料及/或其他合适的绝缘材料。隔离结构210可以是浅沟槽隔离(STI)特征。其他隔离结构也是可能的，例如，场氧化物(field oxide)、硅的局部氧化(local oxidation of silicon,LOCOS)及/或其他合适的结构。隔离结构210可以包括多层结构，例如，具有一个或多个热氧化物衬层。
经堆叠鳍片212a、212b及212c中的每一个具有交替堆叠的半导体层220及222。在材料及/或组成上，半导体层220中的第一半导体材料与半导体层222中的第二半导体材料是不同的。第一半导体材料及第二半导体材料中的每一个可以包括硅、锗、化合物半导体(其包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟及锑化铟)、或合金半导体(其包括硅锗(SiGe)、磷砷化镓(GaAsP)、砷化铟铝(AlInAs)、砷化镓铝(AlGaAs)、砷化铟镓(GaInAs)、磷化铟镓(GaInP)及砷磷化铟镓(GaInAsP))。在本实施例中，半导体层220包括硅，并且半导体层222包括锗或硅锗合金。经堆叠鳍片212a及212b中的半导体层220及222可以额外包括掺质(例如，磷、砷、硼及/或铟)，以改善后续形成的全绕式栅极晶体管的性能。
经堆叠鳍片212a、212b及212c可以通过在基板208上外延成长半导体层220及222而形成，然后通过任何合适的方法进行图案化以形成个别独立的经堆叠鳍片212a、212b及212c。举例而言，可使用一个或多个光刻工艺(photolithography process)，包括双重图案化工艺或多重图案化工艺，而将结构图案化。一般而言，双重图案化或多重图案化工艺结合了光刻工艺及自对准工艺(self-aligned process)，以创造具有较小节距(pitch)的图案，举例而言，此图案所具有的节距比使用单一直接光刻工艺所能够得到的节距更小。举例而言，在一实施例中，形成牺牲层于基板之上并使用光刻工艺将其图案化。使用自对准工艺形成间隔物于经过图案化的牺牲层旁。之后，移除牺牲层，然后可以通过蚀刻初始的半导体层220、222及基板208，而使用剩余之间隔物或心轴(mandrel)将经堆叠鳍片212a、212b及212c图案化。蚀刻工艺包括干式蚀刻、湿式蚀刻、反应性离子蚀刻(reactive ion etching,RIE)及/或其他合适的工艺。在所示出的实施例中，经堆叠鳍片212a、212b及212c在相同方向上纵向延伸(纵向轴线平行)。在一些实施例中，核心区域202中的经堆叠鳍片212a及212b在相同方向(例如，沿着y方向)上纵向延伸，而输入/输出区域204中的经堆叠鳍片212c可以在不同的方向上纵向延伸，例如，沿着垂直方向(例如，沿着x方向)或其他方向。
虚置栅极结构216保留用于金属栅极堆叠的区域，且虚置栅极结构216包括虚置界面层230、虚置栅极电极232、第一栅极硬掩模层234及第二栅极硬掩模层236。虚置界面层230形成在每一个经堆叠鳍片212a、212b及212c的顶表面及侧壁表面上，并且形成在隔离结构210的顶表面上。虚置界面层230可以包括介电材料，例如，氧化物层(例如，二氧化硅(SiO2))或氮氧化物层(例如，氮氧化硅(SiON))，并且可以通过化学氧化、热氧化、原子层沉积(ALD)、化学气相沉积(CVD)及/或其他合适的方法而沉积虚置界面层230。
虚置栅极电极232可以包括多晶硅(poly-Si)，并且可以通过合适当的沉积工艺而形成，例如，低压化学气相沉积(low-pressure chemical vapor deposition,LPCVD)及等离子体辅助化学气相沉积(plasma-enhanced CVD,PECVD)。栅极硬掩模层234及236中的每一个可以包括一层或多层介电材料，例如，氧化硅及/或氮化硅，并且可以通过化学气相沉积或其他合适的方法而形成。举例而言，第一栅极硬掩模层234可以包括与虚置栅极电极232相邻的氧化硅层，且第二栅极硬掩模层236可以包括氮化硅层。可以通过光刻及蚀刻工艺而将各种膜层230、232、234及236图案化。
为了使描述与附图更清楚，图4到图6包括沿着图3所示出的A-A剖线的全绕式栅极核心装置结构206a的局部剖面示意图，其中A-A剖线沿着经堆叠鳍片212a的长度方向(在Y-Z平面中)通过各个通道区域。在Y-Z平面中的全绕式栅极核心装置结构206b及全绕式栅极输入/输出装置结构206c的剖面示意图相似于图4到图6所示出的剖面示意图，因此，为了简洁起见，而将其省略。图7到图18包括沿着图3所示出的B-B剖线的半导体装置200的局部剖面示意图，其中B-B剖线沿着经堆叠鳍片212a、212b及212c的长度方向(在X-Z平面中)通过多个通道区域。
在操作步骤104中，方法100(图2A)形成栅极间隔物238于虚置栅极结构216的侧壁上，如图4所示出。栅极间隔物238可包括介电材料，例如，氧化硅、氮化硅、氮氧化硅、碳化硅、其他介电材料或上述的组合，并且可包括一层或多层材料。可以通过在半导体装置200上沉积作为覆盖层之间隔物材料，而形成栅极间隔物238。之后，通过非等向性蚀刻工艺而蚀刻间隔物材料。位于虚置栅极结构216侧壁上之间隔物材料的部分成为栅极间隔物238。操作步骤104进一步形成源极/漏极部件240于源极/漏极区域中，如第图5所示出。举例而言，操作步骤104可以蚀刻凹口于经堆叠鳍片212a、212b及212c中，并且在凹口中外延成长半导体材料。可以使半导体材料凸出于各个鳍片的顶表面上方。操作步骤104可以分别形成用于n型及p型装置的源极/漏极部件240。例如，操作步骤104可以形成具有n型掺杂硅的源极/漏极部件240而用于n型装置，并且形成具有p型掺杂硅锗的源极/漏极部件240而用于p型装置。操作步骤104可以进一步形成接触蚀刻停止层(CESL)242于源极/漏极部件240上，并且形成层间介电(ILD)层244于接触蚀刻停止层242上。接触蚀刻停止层242可以包括氮化硅、氮氧化硅、含氧(O)或碳(C)元素的氮化硅及/或其他材料；并且可以通过化学气相沉积、物理气相沉积(PVD)、原子层沉积或其他合适的方法而形成接触蚀刻停止层242。层间介电层244可以包括四乙氧基硅烷(tetraethylorthosilicate,TEOS)、未掺杂的硅酸盐玻璃、或经掺杂的氧化硅，例如，硼磷硅酸盐玻璃(borophosphosilicate glass,BPSG)、熔融硅石玻璃(fused silica glass,FSG)、磷硅酸盐玻璃(phosphosilicate glass,PSG)、硼掺杂硅玻璃(boron doped silicon glass,BSG)及/或其他合适的介电材料。可使用化学气相沉积或流动式化学气相沉积(flowable CVD,FCVD)或其他合适的方法而形成间介电层244。在操作步骤104之后可以进行化学机械研磨工艺以移除过多的介电材料。在一些实施例中，化学机械研磨工艺也移除栅极硬掩模234及236，并暴露出虚置栅极电极232。
在操作步骤106中，方法100(图2A)移除虚置栅极电极232，从而形成栅极沟槽246，如图6所示出。操作步骤106可以包括一种或多种蚀刻工艺，这些蚀刻工艺对虚置栅极电极232中的材料具有选择性。通过选择抵抗蚀刻栅极间隔物238及层间介电层244的蚀刻剂，相邻于虚置栅极电极232的栅极间隔物238及层间介电层244的部分被暴露于栅极沟槽246中，而没有实质的蚀刻损失。这可能增加光刻工艺的容忍度(tolerance)。蚀刻工艺可以包括任何合适的蚀刻技术，例如，湿式蚀刻、干式蚀刻、反应性离子蚀刻、灰化及/或其他蚀刻方法。在一实施例中，蚀刻工艺是使用氟基蚀刻剂(例如，全氟甲烷(CF4)、三氟甲烷(CHF3)、二氟甲烷(CH2F2)等)的干式蚀刻工艺。操作步骤106也包括从栅极沟槽246移除虚置界面层230，如图7所示出。
在操作步骤108中，方法100(图2A)从栅极沟槽246释放全绕式栅极装置结构206a、206b及206c的通道区域中的通道构件，如图8所示出。在所示出的实施例中，通道构件是纳米线。技术用语“纳米线”在本文中用于表示具有纳米级或甚至微米级尺寸并且具有细长形状的任何材料部分，而与此部分的剖面形状无关。因此，此技术用语指的是圆形与实质上圆形剖面的细长材料部分，以及，例如，包括圆柱形或实质上矩形的剖面的梁形或条形材料部分。为了简化与清楚起见，在操作步骤110之后将半导体层220表示为纳米线220。在本实施例中，半导体层220包括硅，并且半导体层222包括硅锗。可以选择性地移除多个半导体层222。在一些实施例中，选择性移除工艺包括使用合适的氧化剂(例如，臭氧)，以氧化多个半导体层222。之后，可以选择性地移除被氧化的半导体层222。在其他实施例中，操作步骤110包括干式刻蚀工艺以选择性地移除半导体层222，此干式刻蚀工艺是通过，例如，在500℃至700℃的温度下施加HCl气体或施加全氟甲烷(CF4)、六氟化硫(SF6)及三氟甲烷(CHF3)的气体混合物而进行。此时，如图8所示出，在全绕式栅极核心装置结构206a、206b的通道区域及全绕式栅极输入输出装置结构206c的通道区域中形成垂直堆叠的纳米线220。虽然图9示出每一个堆叠具有四个纳米线220，但是在其他实施例中可以存在更少或更多的垂直堆叠的纳米线220。举例而言，每一个全绕式栅极装置结构中的纳米线220的数量可以在2至10的范围内。
在操作步骤110中，方法100(图2A)形成界面层248，此界面层248包裹位于全绕式栅极装置结构206a、206b及206c中的所有纳米线220。界面层248可以包括介电材料，例如，氧化物层(例如，二氧化硅)或氮氧化物层(例如，氮氧化硅)，并且可以通过化学氧化、热氧化、原子层沉积、化学气相沉积及/或其他合适的方法而沉积界面层248。界面层248具有适合于输入/输出应用的厚度，例如，厚度在从大约
Figure BDA0002779338950000151
到大约
Figure BDA0002779338950000152
之间的范围。在所示出的实施例中，界面层248是通过等离子体辅助原子层沉积工艺而沉积的二氧化硅层，等离子体辅助原子层沉积工艺适合于成长相对较厚的氧化物层。等离子体辅助原子层沉积工艺可以在从大约100℃到大约200℃的温度范围内，以从大约500W到大约700W的射频功率施加包含氧气(O2)及氩气(Ar)的等离子体。在沉积之后，界面层248可以进一步经历氧化后退火(post oxide annealing,POA)工艺，以改善栅极氧化物的品质。如后续所示出，界面层248保留在全绕式栅极输入输出装置结构206c中的纳米线220上作为输入输出氧化物层，而界面层248的其他部分将从在全绕式栅极核心装置结构206a及206b中的其他纳米线220上被移除。
在操作步骤112中，方法100(图2A)在输入/输出区域上形成掩模层249，并从位于全绕式栅极核心装置结构206a及206b中的纳米线220上移除界面层248，如图10所示出。可以通过，例如，湿式蚀刻、干式蚀刻、反应性离子蚀刻或其他合适的蚀刻方法，而移除界面层248。举例而言，操作步骤108可以施加用于湿式蚀刻的基于氢氟酸(HF-based)的湿式蚀刻剂或用于干式蚀刻的氨(NH3)及氢气(H2)混合物。在此操作步骤期间，掩模层249覆盖位于全绕式栅极输入输出装置结构206c中的界面层248的部分。在下文的讨论中，界面层248的剩余部分被标示为界面层252c。在一些实施例中，掩模层249是光刻胶层，例如，底部抗反射涂层(bottom antireflective coating,BARC)。
在操作步骤114中，方法100在全绕式栅极核心装置结构206a及206b中形成另一个界面层以包裹纳米线220，如图11所示出。界面层252a包裹位于全绕式栅极核心装置结构206a中的纳米线220，而界面层252b包裹位于全绕式栅极核心装置结构206b中的纳米线220。界面层252a及252b可以包括介电材料，例如，氧化物层(例如，二氧化硅)或氮氧化物层(例如，氮氧化硅)，并且可以通过化学氧化、热氧化、原子层沉积、化学气相沉积及/或其他合适的方法而沉积界面层252a及252b。在一些实施例中，界面层252a及252b中的每一个可以具有适合于高速应用的厚度，例如，厚度在从大约
Figure BDA0002779338950000161
Figure BDA0002779338950000162
到大约
Figure BDA0002779338950000163
之间的范围。在一些实施例中，通过与用于形成界面层252c的工艺不同的工艺成长界面层252a及252b。在所示出的实施例中，界面层252a及252b是二氧化硅层，其在含过氧化氢(H2O2)的溶液(例如，SC1、SC2及SPM)中形成。在操作步骤114期间，掩模层249保护界面层252c不会发生厚度变化。在操作步骤114之后，可在蚀刻工艺或其他合适的工艺(例如，灰化或光刻胶剥离(resiststripping))中移除掩模层249。
在操作步骤116中，方法100(图2B)在栅极沟槽246中形成高介电常数介电层254，如图12所示出，而在全绕式栅极核心装置结构206a、全绕式栅极核心装置结构206b及全绕式栅极输入输出装置结构206c的通道区域中分别形成栅极介电层250a、250b及250c(统称为栅极介电层250)。栅极介电层250a包括界面层252a及高介电常数介电层254a，其中界面层252a包裹全绕式栅极核心装置结构206a的纳米线220，而高介电常数介电层254a包裹界面层252a。栅极介电层250b包括界面层252b及高介电常数介电层254b，其中界面层252b包裹全绕式栅极核心装置结构206b的纳米线220，而高介电常数介电层254b包裹界面层252b。栅极介电层250c包括界面层252c及高介电常数介电层254c，其中界面层252c包裹全绕式栅极输入输出装置结构206c的纳米线220，而高介电常数介电层254c包裹界面层252c。在所示出的实施例中，界面层252a、252b、252c及高介电常数介电层254a、254b、254c被沉积为实质上顺应性的膜层。高介电常数介电层254a、254b及254c的厚度可以实质上相同。可以使用任何合适的技术而沉积高介电常数介电层254，例如，原子层沉积、化学气相沉积、金属有机化学气相沉积(metal-organic CVD,MOCVD)、物理气相沉积、热氧化、上述的组合及/或其他合适的技术。高介电常数介电层254可以包括金属氧化物(例如，氧化镧(LaO)、氧化铝(AlO)、氧化锆(ZrO)、氧化钛(TiO)、五氧化二钽(Ta2O5)、三氧化二钇(Y2O3)、钛酸锶(SrTiO3,STO)、钛酸钡(BaTiO3,BTO)、氧化锆钡(BaZrO)、氧化锆铪(HfZrO)、氧化镧铪(HfLaO)、氧化钽铪(HfTaO)、氧化钛铪(HfTiO)、钛酸锶钡((Ba,Sr)TiO3,BST)、三氧化二铝(Al2O3)等)、金属硅化物(例如，氧化硅铪(HfSiO)、氧化硅镧(LaSiO)、氧化硅铝(AlSiO)等)、金属氮化物或半导体氮化物、金属氮氧化物或半导体氮氧化物、上述的组合及/或其他合适的材料。在一个特定的例子中，高介电常数介电层254的厚度在从大约
Figure BDA0002779338950000171
到大约
Figure BDA0002779338950000172
Figure BDA0002779338950000173
之间的范围。
在操作步骤118中，方法100(图2B)首先形成覆盖栅极介电层250a、250b及250c的盖层260，如图13所示出。厚度调整层260可以包括一个或多个材料层。在所示出的实施例中，厚度调整层260包括氮化钛(TiN)。在此实施例的进一步方案中，盖层260包括富含金属的氮化钛，例如，为约1.05：1或约2：1的钛氮比(Ti：N ratio)。沉积方法包括物理气相沉积、化学气相沉积、原子层沉积或其他合适的方法。随后，操作步骤120形成掩模层261覆盖全绕式栅极核心装置结构206a及全绕式栅极输入输出装置结构206c的纳米线220，并且从全绕式栅极核心装置结构206b移除盖层260，如图14所示出。可以通过，例如，湿式蚀刻、干式蚀刻、反应性离子蚀刻或其他合适的蚀刻方法而移除盖层260。在一些实施例中，掩模层261是光刻胶层，例如，底部抗反射涂层。在操作步骤120之后，可以通过，例如，蚀刻、灰化或光刻胶剥离而移除掩模层261。此时，盖层260仅保留在全绕式栅极核心装置结构206a的栅极介电层250a及全绕式栅极输入输出装置结构206c的栅极介电层250c上。
在操作步骤120中，方法100(图2B)进行退火工艺(通过图15中的箭号270表示)，以在界面层252b上启动氧化物再生工艺(oxide regrowth proces)。退火工艺包括尖峰退火(spike annealing)工艺，其具有含氮的环境，其初始温度在大约500℃到大约700℃之间，并且峰值温度在大约700℃到大约900℃之间。在一些实施例中，界面层252b的厚度可通过进一步的硅消耗而增加约10％至约20％。盖层260通过从环境阻挡氧气而限制界面层252a及252c的进一步成长。在操作步骤120之后，界面层252b的厚度TIL2大于界面层252a的厚度TIL1，但是仍然小于界面层252c的厚度TIL3。由于退火工艺是在含氮的环境中进行的，因此高介电常数介电层254b可以吸收氮，进而导致高介电常数介电层254b中的氮浓度高于高介电常数介电层254a或254c中的氮浓度。
在方法100的一些其他实施例中，盖层260是厚度调整层，例如，除氧层(oxygen-scavenging layer)260。相较于金属氧化物(位于高介电常数栅极介电层中)中的金属及硅(位于界面层中)，除氧层260具有更高的氧亲和力。除氧层260可以包括金属或金属化合物，例如，钛(Ti)、铪(Hf)、锆(Zr)、钽(Ta)、铝(Al)或上述的组合，例如，钛铝(TiAl)。除氧层260也可以由金属氮化物(例如，氮化钽(TaN)、氮化硅钽(TaSiN)、氮化硅钛(TiSiN))或金属合金的氮化物形成(例如，氮化钛铝(TiAlN))。在一些实施例中，除氧层260可以是硅层。在一个特定的例子中，除氧层260包括富含金属的氮化硅钛(例如，Ti：N比为大约1.05：1至大约2：1)。除氧层260具有在高温下从界面层252a清除氧的功能。在一些替代实施例中的操作步骤120中，方法100进行退火工艺(通过图16中的箭号271表示)以启动并实现氧的清除。可以使用尖峰退火而进行清除退火(scavenging anneal)，其中持续时间为毫秒等级，例如，在大约10毫秒与大约500毫秒之间。各个芯片的温度可以在大约400℃至大约1100℃之间的范围内。根据一些例示性的实施例，温度在大约700℃至大约1,000℃之间的范围内。
氧的清除工艺至少从界面层252a及252c的底部剥夺氧气，因此保留在界面层252a及252c中的硅，而在纳米线220的界面层252a及252c的结晶硅层的顶部形成另一层硅层。图16示出部分272的放大图。箭号274被示出而用以指示因清除而引起的氧原子的运动。因此，形成非晶硅层276。在从界面层252a(252c)的底部清除了氧气之后，另一层硅层由界面层252a(252c)残留的硅形成。在清除退火工艺期间，高介电常数介电层254a(254c)可以与界面层252a(252c)的顶部分及从界面层252a(252c)的底部分清除的氧相互混合，而形成互混化合物(intermix compound)，此互混化合物可以是金属硅酸盐。互混化合物可能具有增加的氧含量。例如，当高介电常数介电层254a包括二氧化铪(HfO2)时，互混化合物包括硅酸铪(HfSiO4)。当高介电常数介电层254a包括二氧化锆(ZrO2)时，互混化合物包括硅酸锆(ZrSiO4)。
氧的清除工艺化学性地减少界面层252a及252c。因此，界面层252a具有减小的厚度(例如，薄化约10％至约50％)，此减小的厚度小于界面层252b的厚度，或者甚至可以被消除(完全转化)。由于氧化物的再成长，界面层252b仍然可能成长。界面层252c也遭受厚度损失，但是仍然大于界面层252b的厚度。
在操作步骤122中，方法100(图2A)在选择性蚀刻工艺中移除盖层260，而在栅极沟槽246中暴露出栅极介电层250a、250b及250c，如图17所示出。选择性蚀刻工艺可以包括干式蚀刻、湿式蚀刻、反应性离子蚀刻及/或其他合适的工艺。因此，随着界面层厚度的变化，栅极介电层250a具有第一电容等效厚度，此第一电容等效厚度最薄而适合于高速应用；栅极介电层250b具有第二电容等效厚度，此第二电容等效厚度适中而适合于低功率及低漏电流应用；且栅极介电层250c具有最厚的电容等效厚度而适合于高电压应用。
在操作步骤124中，方法100(图2B)在栅极沟槽中形成栅极电极层282，在核心区域及输入/输出区域中包裹栅极介电层250a、250b及250c。在所示出的实施例中，全绕式栅极核心装置结构206a及206b相邻并共用相同的栅极电极层，而全绕式栅极输入输出装置结构206c具有分离的栅极电极层。栅极电极层282是导电层，其包括一个或多个金属层，例如，功函数金属层、导电阻障层级金属填充层。栅极电极层282可以针对的n型晶体管与p型晶体管分别形成，其中n型晶体管与p型晶体管可能使用不同金属层。功函数金属层可以是p型功函数金属层或n型功函数层。此p型功函数层包括具有足够大的有效功函数(effective workfunction)的金属，此金属选自于但不限于氮化钛(TiN)、氮化钽(TaN)、钌(Ru)、钼(Mo)、钨(W)、铂(Pt)或上述的组合。此n型功函数层包括具有足够低的有效功函数的金属，此金属选自于但不限于钛(Ti)铝(Al)、碳化钽(TaC)、氮碳化钽(TaCN)、氮硅化钽(TaSiN)、氮硅化钛(TiSiN)或上述的组合。栅极电极层282可以包括多个功函数金属层，例如，第一金属层及第二金属层。作为示范例，第一金属层可以包括氮化钛，且第二金属层可以包括钛铝合金(TiAl)或钛、钽、碳、铝的其他组合，例如，碳化铝钛(TiAlC)或碳化铝钽(TaAlC)。栅极电极层282亦包括金属填充层。金属填充层可以包括铝(Al)、钨(W)、钴(Co)及/或其他合适的材料。在各种实施例中，可以通过镀覆(plating)、原子层沉积、物理气相沉积、化学气相沉积、电子束蒸发(e-beam evaporation)或其他合适的工艺，而形成栅极电极层282的金属填充层。在各种实施例中，可以进行化学机械研磨工艺以从栅极堆叠的金属层移除过量的金属，而提供实质上平坦的顶表面。
在方法100(图2B)的操作步骤126中，可以对半导体装置200进行进一步的工艺以形成本领域已知的各种部件及区域。举例而言，后续的工艺可以形成接触件开口、接触件金属以及各种接触件/导通孔/导线及多层内连线部件(例如，金属层及层间介电质)，其被配置为连接各种部件以形成功能电路，此功能电路可以包括一个或多个多栅极(multi-gate)装置。在此示范例的进一步改进中，多层内连线可以包括垂直内连线及水平内连线，此垂直内连线可为，例如，导通孔或接触件，此水平内连线可为，例如，金属线之类。各种内连线部件可以采用各种导电材料，包括铜、钨及/或硅化物。在一示范例中，镶嵌及/或双镶嵌工艺用于形成与铜相关的多层内连线结构。再者，可以在方法100之前、之间及之后提供额外的工艺步骤，并且根据方法100的各种实施例可以替换或省略所述的一些工艺步骤。
虽然目的并非用以限制，但是本公开的一个或多个实施例为半导体装置及其形成提供了许多优点。例如，本公开的实施例提供在同一基板上及在同一集成电路中的全绕式栅极高速装置、全绕式栅极低功率/低漏电流装置及全绕式栅极高电压装置。全绕式栅极高速装置及全绕式栅极低功率/低漏电流装置位于集成电路的核心区域，例如，用于高速或低功率电路，而全绕式栅极高电压装置位于集成电路的输入/输出区域，用于实现输入输出电路或静电放电电路。全绕式栅极高速装置、全绕式栅极低功率/低漏电流装置及全绕式栅极高电压装置具有各不相同的栅极介电质厚度，而在三种类型的装置中产生性能差异。本实施例使电路设计者能够通过选择不同类型的装置而将位于集成电路的不同区域中的电路最佳化。
在一些示范性实施例中，提供一种集成电路。上述集成电路包括：基板，具有第一区域及第二区域；第一全绕式栅极装置，位于上述第一区域中，其中上述第一全绕式栅极装置包括：第一通道构件，在第一方向上纵向延伸；以及第一栅极结构，包裹上述第一通道构件的通道区域，其中上述第一栅极结构包括第一界面层，上述第一界面层具有在大致垂直于上述第一方向的第二方向上所测量到的第一厚度；第二全绕式栅极装置，位于上述第一区域中，其中上述第二全绕式栅极装置包括：第二通道构件，在上述第一方向上纵向延伸；以及第二栅极结构，包裹上述第二通道构件的通道区域，其中上述第二栅极结构包括第二界面层，上述第二界面层具有在上述第二方向上所测量到的第二厚度，且上述第二厚度大于上述第一厚度；以及第三全绕式栅极装置，位于上述第二区域中，其中上述第三全绕式栅极装置包括：第三通道构件，在上述第一方向上纵向延伸；以及第三栅极结构，包裹上述第三通道构件的通道区域，其中上述第三栅极结构包括第三界面层，上述第三界面层具有在上述第二方向上所测量到的第三厚度，且上述第三厚度大于上述第二厚度。在一些实施例中，其中上述第二厚度与上述第一厚度的比率在大约1.1与大约1.2之间。在一些实施例中，其中上述第一厚度在约
Figure BDA0002779338950000211
与
Figure BDA0002779338950000212
之间。在一些实施例中，其中上述第三厚度在大约
Figure BDA0002779338950000214
和
Figure BDA0002779338950000213
之间。在一些实施例中，其中上述第一界面层、上述第二界面层及上述第三界面层中的每一者包括二氧化硅。在一些实施例中，其中上述第一栅极结构还包括第一介电层，包裹上述第一界面层，其中上述第二栅极结构还包括第二介电层，包裹上述第二界面层，其中上述第三栅极结构还包括第三介电层，包裹上述第三界面层，且其中在上述第二方向上所测量到的上述第一介电层、上述第二介电层及上述第三介电层的厚度实质上相等。在一些实施例中，其中上述第一介电层、上述第二介电层及上述该第三介电层中的每一者包括一材料，且上述材料是选自由氮化硅(SiN)、氮氧化硅(SiON)、氮氧碳化硅(SiCON)、碳氧化硅(SiOC)、二氧化铪(HfO2)及三氧化二铝(Al2O3)所组成的群。在一些实施例中，其中上述第二介电层具有比上述第一介电层及上述第三介电层更高的氮浓度。在一些实施例中，其中上述第一全绕式栅极装置及上述第二全绕式栅极装置是上述集成电路的核心装置，且其中上述第三全绕式栅极装置是上述集成电路的输入/输出装置。在一些实施例中，其中上述第一全绕式栅极装置包括第一非晶硅层，位于上述第一界面层与上述第一通道构件之间，其中上述第二界面层与上述第二通道构件直接接触，且其中上述第三全绕式栅极装置包括第二非晶硅层，位于上述第三界面层与上述第三通道构件之间。
在另一些示范性实施例中，提供一种集成电路装置。上述集成电路装置包括：核心装置，包括：第一通道构件；第一栅极结构，与上述第一通道构件啮合，其中上述第一栅极结构包括第一界面层，其中上述第一界面层包裹上述第一通道构件的通道区域；第二通道构件；以及第二栅极结构，与上述第二通道构件啮合，其中上述第二栅极结构包括第二界面层，其中上述第二界面层包裹上述第二通道构件的通道区域，其中上述第二界面层在大致垂直于上述第二通道构件的纵轴的方向上的厚度大于上述第一界面层在大致垂直于上述第一通道构件的纵轴的方向上的厚度；以及输入/输出装置，包括：第三通道构件；以及第三栅极结构，与上述第三通道构件啮合，其中上述第三栅极结构包括第三界面层，其中上述第三界面层包裹上述第三通道构件的通道区域，其中上述第三界面层在大致垂直于上述第三通道构件的纵轴的方向上的厚度大于上述第二界面层的上述厚度。在一些实施例中，其中上述第二界面层的上述厚度与上述第一界面层的上述厚度的比率在大约1.1与大约1.2之间。在一些实施例中，其中上述第一界面层的上述厚度在约
Figure BDA0002779338950000221
与
Figure BDA0002779338950000222
之间。在一些实施例中，其中上述第一通道构件的纵轴、上述第二通道构件的纵轴及上述第三通道构件的纵轴彼此平行。在一些实施例中，其中上述第一界面层、上述第二界面层及上述第三界面层包括二氧化硅。
在另一些示范性实施例中，提供一种集成电路装置的制造方法。上述制造方法包括：提供基板，其中上述基板具有第一通道构件、第二通道构件及第三通道构件，其中上述第一通道构件及上述第二通道构件位于集成电路装置的核心区域中，且上述第三通道构件位于上述集成电路装置的输入/输出区域中；通过第一工艺以形成第一氧化物层及第二氧化物层，其中上述第一氧化物层包裹上述第一通道构件的通道区域，且上述第二氧化物层包裹上述第二通道构件的通道区域；通过不同于上述第一工艺的第二工艺，以形成第三氧化物层包裹上述第三通道构件的通道区域；分别形成第一介电层、第二介电层及第三介电层于上述第一氧化物层、上述第二氧化物层及上述第三氧化物层上；分别形成第一盖层、第二盖层及第三盖层于上述第一介电层、上述第二介电层及上述第三介电层上；移除上述第二盖层以暴露出上述第二介电层，其中在移除上述第二盖层之后，上述第一盖层及上述第三盖层分别保留于上述第一介电层及上述第三介电层上；以及在移除上述第二盖层之后，进行退火工艺以增加上述第二氧化物层的厚度。在一些实施例中，其中上述第二氧化物层的上述厚度相对于上述第一氧化物层的厚度的比率在大约1.1与大约1.2之间，且其中上述第三氧化物层的厚度大于上述第二氧化物层的上述厚度。在一些实施例中，其中上述第二工艺在上述第一工艺之前进行，且在进行上述第一工艺之前，上述制造方法还包括：通过上述第二工艺，以形成上述第三氧化物层包裹上述第一通道构件的上述通道区域及上述第二通道构件的上述通道区域；形成蚀刻掩模，以覆盖上述集成电路装置的上述输入/输出区域；当上述蚀刻掩模覆盖上述集成电路装置的上述输入/输出区域时，从上述第一通道构件的上述通道区域且从上述第二通道构件的上述通道区域移除上述第三氧化物层；以及移除上述蚀刻掩模，以暴露出上述第三氧化物层包裹上述第三通道构件的上述通道区域。在一些实施例中，其中上述第一工艺包括使用过氧化氢、硫酸或上述的组合处理上述第一通道构件及上述第二通道构件。在一些实施例中，其中上进行上述退火工艺包括尖峰退火工艺，其中上述尖峰退火工艺具有含氮的环境、初始温度在大约500℃到大约700℃之间以及峰值温度在大约700℃到大约900℃之间。
前述内文概述了许多实施例的部件，使本技术领域中技术人员可以从各个方面优选地了解本发明实施例。本技术领域中技术人员应可理解，且可轻易地以本发明实施例为基础来设计或修饰其他工艺及结构，并以此达到相同的目的及/或达到与在此介绍的实施例等相同的优点。本技术领域中技术人员也应了解这些相等的结构并未背离本发明的发明构思与范围。在不背离本发明的发明构思与范围的前提下，可对本发明进行各种改变、置换或修改。
虽然本发明已以数个优选实施例公开如上，然其并非用以限定本发明，任何所属技术领域中技术人员，在不脱离本发明的构思和范围内，当可作任意的变动与润饰，因此本发明的保护范围当视权利要求所界定者为准。

Claims (1)

1.一种集成电路，包括：
一基板，具有一第一区域及一第二区域；
一第一全绕式栅极装置，位于该第一区域中，其中该第一全绕式栅极装置包括：
一第一通道构件，在一第一方向上纵向延伸；以及
一第一栅极结构，包裹该第一通道构件的一通道区域，其中该第一栅极结构包括一第一界面层，该第一界面层具有在大致垂直于该第一方向的一第二方向上所测量到的一第一厚度；
一第二全绕式栅极装置，位于该第一区域中，其中该第二全绕式栅极装置包括：
一第二通道构件，在该第一方向上纵向延伸；以及
一第二栅极结构，包裹该第二通道构件的一通道区域，其中该第二栅极结构包括一第二界面层，该第二界面层具有在该第二方向上所测量到的一第二厚度，且该第二厚度大于该第一厚度；以及
一第三全绕式栅极装置，位于该第二区域中，其中该第三全绕式栅极装置包括：
一第三通道构件，在该第一方向上纵向延伸；以及
一第三栅极结构，包裹该第三通道构件的一通道区域，其中该第三栅极结构包括一第三界面层，该第三界面层具有在该第二方向上所测量到的一第三厚度，且该第三厚度大于该第二厚度。
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