CN112997262A - 微电子裸片上的电感器 - Google Patents

微电子裸片上的电感器 Download PDF

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Publication number
CN112997262A
CN112997262A CN201980070113.XA CN201980070113A CN112997262A CN 112997262 A CN112997262 A CN 112997262A CN 201980070113 A CN201980070113 A CN 201980070113A CN 112997262 A CN112997262 A CN 112997262A
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China
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conductor
lateral
seed layer
die
forming
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S·K·科杜里
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

一种装置(100)在裸片(102)上具有凸块接合件(130)及电感器(140)。所述装置(100)包含沿所述裸片(102)延伸的第一侧向导体(108)。所述第一侧向导体(108)中的一些与所述裸片(102)的端子(104)中的一些接触。所述装置(100)还包含位于所述第一侧向导体(108)上的导电柱(114)及位于所述导电柱(114)上的第二侧向导体(120)，所述第二侧向导体(120)与所述第一侧向导体(108)相对，在平面中侧向延伸。第一组(128)所述第一侧向导体(108)、所述导电柱(114)及所述第二侧向导体(120)提供所述装置的所述凸块接合件(130)。第二组(138)所述第一侧向导体(108)、所述导电柱(114)及所述第二侧向导体(120)串联地电耦合以形成所述电感器(140)。还描述形成所述装置(100)的方法。

Description

微电子裸片上的电感器
本发明涉及微电子装置领域，且更特定来说，涉及微电子装置上的电感器。
背景技术
微电子装置通常包含带有电感器的电路，其通常在0.5到5纳米亨利(nH)的范围内。在此范围内的电感器倾向于利用几百平方微米或更大的面积，从而不期望地增加微电子装置的大小及成本。在这些电感器中获得期望的Q值是具有挑战性的。
发明内容
本描述介绍一种微电子装置，所述装置具有裸片、在所述裸片上的凸块接合件及电感器。所述裸片含有延伸到所述裸片的端子表面的端子。所述微电子装置包含沿所述端子表面延伸的第一侧向导体，其中所述第一侧向导体的至少一部分与所述端子的至少一部分接触。所述微电子装置还包含位于所述第一侧向导体上的导电柱，所述导电柱从所述端子表面垂直延伸，及位于所述导电柱上的第二侧向导体，所述第二侧向导体与所述第一侧向导体相对，所述第二侧向导体在与所述端子表面平行的平面内侧向延伸。所述第二侧向导体具有定位成与所述导电柱相对的裸片附接表面。第一组所述第一侧向导体、所述导电柱及所述第二侧向导体提供所述微电子装置的所述凸块接合件。第二组所述第一侧向导体、所述导电柱及所述第二侧向导体串联地电耦合以形成所述电感器。还描述形成所述微电子装置的方法。
附图说明
图1是实例微电子装置的横截面，所述实例微电子装置具有裸片、及在所述裸片上的凸块接合件及电感器。
图2A到图2L是在形成的实例方法的阶段中描绘的微电子装置的横截面，所述微电子装置具有裸片、及在所述裸片上的凸块接合件及电感器。
图3A到图3F是在另一形成的实例方法的阶段中描绘的微电子装置的横截面，所述微电子装置具有裸片、及在所述裸片上的凸块接合件及电感器。
图4是实例微电子装置的俯视图，所述实例微电子装置具有裸片及在所述裸片上的电感器。
图5是另一实例微电子装置的俯视图，所述实例微电子装置具有裸片及在所述裸片上的包含两个电感器的变压器。
图6是另一实例微电子装置的俯视图，所述实例微电子装置具有裸片及在所述裸片上的包含两个电感器的变压器。
具体实施方式
参考附图描述实例。这些附图可能不按比例绘制。描述不受所说明的动作或事件的顺序的限制，且并非需要所有说明动作或事件来实施描述中的方法。尽管通过针对有源装置的实例来说明所述描述，但这些说明并不限制这些实例的范围或适用性，且所述装置不限于所说明的物理结构。
一种微电子装置，其包含裸片，且在所述裸片上具有凸块接合件及电感器。所述裸片含有端子，例如，延伸到所述裸片的端子表面的接合垫。端子表面不一定是平面的。所述微电子装置包含在所述裸片外部沿所述端子表面延伸的第一侧向导体。所述第一侧向导体中的一些与所述端子中的一些接触。
所述微电子装置包含第一侧向导体上的导电柱，所述导电柱从所述端子表面垂直延伸。所述导电柱中的一些可在与对应的第一侧向导体接触的端子侧向位移的位置处与所述对应的第一侧向导体接触。因此，所述导电柱中的一些不位于它们通过对应的第一侧向导体电耦合到的端子的正上方。
所述微电子装置包含位于导电柱上的第二侧向导体，其与第一侧向导体相对，所述第二侧向导体在与所述端子表面平行的平面内侧向延伸。第二侧向导体具有定位成与导电柱相对的裸片附接表面。焊料或导电粘合剂可经安置在第二侧向导体的至少一部分的裸片附接表面上。
第一组第一侧向导体、导电柱及第二侧向导体提供微电子装置的凸块接合件。第二组第一侧向导体、导电柱及第二侧向导体串联地电耦合以形成电感器。电感器可具有线性配置、环形配置或其它配置。电感器的一或多个节点可在端子表面接触端子。电感器的一或多个节点可延伸到第二侧向导体以用于与封装的外部引线进行电连接。电感器可为变压器的一部分。
术语“侧向”是指与裸片的端子表面的平面平行的方向。术语，例如“在……上方”及“在……下方”，用于提供结构或元件之间的空间关系。被称为“连接”或“耦合”到另一元件的元件可直接连接或直接耦合到另一元件，或可存在中间元件。
图1是实例微电子装置的横截面，所述实例微电子装置具有裸片、及在所述裸片上的凸块接合件及电感器。微电子装置100包含裸片102，其可为例如离散半导体装置、集成电路或微电机械系统(MEMS)装置。裸片102具有延伸到裸片102的端子表面106的端子104。例如，端子104可主要包含铝或铜。端子104可为接合垫，在裸片102的顶部互连层级之上，或可为顶部互连层级的部分。端子104可在端子表面106处包含凸块下金属(UBM)层。UBM层可包含例如镍、钯、铂、金、铜、钛、钨、铬等金属。裸片102可具有由电绝缘材料形成的保护性外套(PO)层(图1中未展示)，其延伸到端子104之间的端子表面106。PO层可包含二氧化硅、氮化硅、氮氧化硅、聚酰亚胺等。
微电子装置100包含沿端子表面106延伸的第一侧向导体108。第一侧向导体108中的一些及任选地全部与端子104的中一些及任选地全部接触。个别第一侧向导体108可接触端子104中的一或多者。在此实例中，第一侧向导体108是端子表面106上的第一导体晶种层110，及第一导体晶种层110上的第一主导体112。第一主导体112侧向延伸到第一侧向导体108的侧向边界。第一主导体112可沿直线延伸，或可具有一或多个侧向倾斜。第一导体晶种层110可包含在端子表面106上的含有例如钛、钨、铬或镍等金属的粘合层，及在粘合层上的铜的电镀层。以实例的方式，第一导体晶种层110可具有10纳米到1微米的厚度。第一主导体112是导电的且可包含电镀铜，任选地带有例如金、银或镍等其它金属。以实例的方式，第一主导体112可具有3微米到30微米的厚度。
微电子装置100包含安置在第一侧向导体108上的导电柱114。导电柱114垂直于端子表面106从第一侧向导体108延伸。术语“垂直”涵盖在形成微电子装置100时遇到的制造及测量公差范围内基本上垂直的定向。导电柱114中的一些可在与对应的第一侧向导体108接触的端子104侧向位移的位置处与对应的第一侧向导体108接触。导电柱114的另一部分可接触在对应的第一侧向导体108所接触的端子104的正上方的第一侧向导体108。图1描绘导电柱114的两个部分的例子。在此实例中，导电柱114是第一侧向导体108上的柱晶种层116及柱晶种层116上的主柱118。主柱118导电并延伸到导电柱114的顶部，其与第一侧向导体108相对。柱晶种层116可包含在端子表面106上的含有例如钛、铬或镍等金属的粘合层，及在粘合层上的铜的电镀层。以实例的方式，柱晶种层116可具有10纳米到1微米的厚度。主柱118可包含电镀铜，任选地带有例如金、银或镍等其它金属，且可具有类似于第一主导体112的组合物。以实例的方式，主柱118可具有垂直于端子表面106测量的30微米到100微米的高度。导电柱114可具有各种横截面形状。导电柱114的一些例子可具有圆形横截面形状，或具有圆角的方形横截面形状。导电柱114的其它例子可具有椭圆形或矩形横截面形状。导电柱114的其它横截面形状在此实例的范围内。以实例的方式，主柱118可具有平行于端子表面106测量的25微米到50微米的宽度，且可具有平行于端子表面106测量的25微米到300微米的长度。
微电子装置100进一步包含安置在导电柱114上的第二侧向导体120。第二侧向导体120及第一侧向导体108位于导电柱114的相对端部。第二侧向导体120中的一些在与端子表面平行的平面中侧向延伸超过其安置在其上的对应导电柱114。在此实例中，第二侧向导体120是导电柱114上的第二导体晶种层122，及第二导体晶种层122上的第二主导体124。第二主导体124侧向延伸到第二侧向导体120的侧向边界。第二主导体124可沿直线延伸，或可具有一或多个侧向倾斜。第二导体晶种层122可包含导电柱114上的含有例如钛、铬或镍等金属的粘合层，及粘合层上的铜的电镀层。以实例的方式，第二导体晶种层122可具有10纳米到1微米的厚度。第二主导体124可包含电镀铜，任选地带有例如金、银或镍等其它金属，且可具有类似于第一主导体112的组合物。以实例的方式，第二主导体124可具有3微米到30微米的厚度。第二侧向导体120具有定位成与第一侧向导体108相对的裸片附接表面126。
第一组128第一侧向导体108、导电柱114及第二侧向导体120提供微电子装置100的凸块接合件130。裸片附接材料132经安置在凸块接合件130的裸片附接表面126上。裸片附接材料132可包含例如呈焊膏形式的焊料，或使用熔融的焊料浴形成的焊料层。替代地，裸片附接材料132可包含导电粘合剂，例如带有金属微粒的环氧树脂。用于裸片附接材料132的其它组合物在此实例的范围内。凸块接合件130中的一或多者可包含裸片附接表面126上的绝缘层134，以界定裸片附接材料132的区域。绝缘层134可包含例如聚酰亚胺或聚酯的聚合物绝缘材料，或可包含例如陶瓷或玻璃料的无机绝缘材料。
图1描绘附接到外部引线136的微电子装置100。外部引线136可为含有微电子装置100的封装的一部分，或可为微电子装置100安装在其上的载体或电路板的一部分。外部引线136通过裸片附接材料132电耦合到凸块接合件130。在凸块接合件130中具有第一侧向导体108及第二侧向导体120可实现端子104在裸片102上的所期望的布置，并将端子104连接到外部引线136的所期望的布置。囊封材料，例如环氧树脂(图1中未展示)，可经安置在端子表面106上，覆盖第一侧向导体108，并环绕导电柱114。
第二组138第一侧向导体108、导电柱114及第二侧向导体120串联电配置以提供电感器140。如图1所描绘，电感器140可具有线性配置，其中电感器140的第一侧向导体108、导电柱114及第二侧向导体120布置在线性阵列中。替代地，电感器140可具有环形配置或其它配置。由于第一侧向导体108、导电柱114及第二侧向导体120中的低电阻，电感器140可具有期望高的质量因数，通常称为Q因数。具有包含厚度为3微米到30微米的铜的第一侧向导体108可在100兆赫(MHz)的频率下提供大于1的Q因数，这可能难以使用裸片102中的较薄的重布层(RDL)或互连件来实现。电感器140的低电阻可使得能够在电源电路及信号电路中使用，这可降低由较薄RDL层形成的电感器中的可靠性。电感器140可包含与第一侧向导体108或第二侧向导体120平行的额外导电元件，以进一步改进Q因数。例如，裸片102的互连件可与第二组138中的第一侧向导体108平行地电耦合。外部引线136的例子可与第二组138中的第二侧向导体120并联地电耦合。如图1所描绘，电感器140的一或多个节点可接触端子104中的一或多者。电感器140的一或多个节点可延伸到裸片附接表面126以用于与封装的外部引线的电连接。电感器140可为变压器的一部分。
图2A到图2L是在实例形成方法的阶段中描绘的微电子装置的横截面，所述微电子装置具有裸片、及在所述裸片上的凸块接合件及电感器。参考图2A，微电子装置200包含裸片202，其可经实施为离散半导体装置、集成电路、MEMS装置或其它此类微电子裸片。裸片202可为含有额外裸片的半导体晶片的一部分。裸片202具有延伸到裸片202的端子表面206的端子204。例如，端子204可主要由铝或铜形成，且可具有在端子表面206处形成的UBM层以在制造期间保护端子204，因此提供与端子204的低电连接。UBM层可例如通过溅射工艺或无电极电镀工艺形成。裸片202可具有延伸到端子204之间的端子表面206的PO层。PO层可包含参考图1的PO层描述的任何电绝缘材料，且可例如通过等离子体增强化学气相沉积(PECVD)工艺或光刻工艺形成。
第一导体晶种层210形成在端子表面206上，与端子204接触。第一导体晶种层210可包含形成在端子表面206上、与端子204接触的粘合层，及粘合层上的电镀层。粘合层可包含一或多种金属，其在邻近于端子204的端子表面206处与端子204及裸片202的材料(例如PO层)具有所期望的粘合。例如，粘合层可包含钛、钛钨、铬或镍，且可通过一或多种溅射工艺形成。电镀层可主要包含铜，且可通过溅射工艺形成。
在第一导体晶种层210上形成第一导体电镀掩模242，从而在用于随后形成的第一侧向导体208的区域中暴露所述第一导体晶种层210，如图2B所示。在此实例的一个版本中，第一导体电镀掩模242可包含光致抗蚀剂或其它光敏聚合物，且可通过光刻工艺形成。在另一版本中，第一导体电镀掩模242可包含聚合物材料，且可通过加成工艺(例如材料喷射工艺)形成。在进一步版本中，第一导体电镀掩模242可包含例如聚酰亚胺、聚酯或聚甲基丙烯酸甲酯(PMMA)等可热腐蚀材料，且可通过激光烧蚀工艺形成。用于第一导体电镀掩模242的其它材料及用于形成第一导体电镀掩模242的方法在此实例的范围内。
参考图2B，在第一导体晶种层210上由第一导体电镀掩模242暴露的位置处形成第一主导体212。第一主导体212可具有参考图1的第一主导体112所描述的组合物。第一主导体212可通过铜电镀工艺形成，或任选地通过铜无电极电镀操作形成。第一导体晶种层210及第一主导体212提供微电子装置200的第一侧向导体208。
参考图2C，在第一侧向导体208上且在第一导体电镀掩模242上方形成柱晶种层216。柱晶种层216可包含形成在第一侧向导体208上且形成在第一导体电镀掩模242上方并与第一侧向导体208接触的粘合层，及粘合层上的电镀层。粘合层可包含一或多种金属，其与第一侧向导体208中的金属及第一导体电镀掩模242的材料具有所期望的粘合。例如，粘合层可包含钛、铬或镍，且可通过一或多种溅射工艺形成。电镀层可主要包含铜，且可通过溅射工艺形成。
参考图2D，在柱晶种层216上形成柱电镀掩模244，在用于随后形成的导电柱214的区域中暴露所述柱晶种层216，如图2E所示。柱电镀掩模244可通过参考第一导体电镀掩模242所描述的任何方法形成。用于柱电镀掩模244的其它材料及用于形成柱电镀掩模244的方法在此实例的范围内。
参照图2E，在柱晶种层216上由柱电镀掩模244暴露的位置处形成主柱218。主柱218可具有参考图1的主柱118所述的组合物。主柱218可通过铜电镀工艺形成，或任选地通过铜无电极电镀操作形成。柱晶种层216及主柱218提供微电子装置200的导电柱214。
参考图2F，在导电柱214上及柱电镀掩模244上形成第二导体晶种层222。第二导体晶种层222可包含形成在导电柱214上且形成在柱电镀掩模244上方并与导电柱214接触的粘合层，及粘合层上的电镀层。粘合层可包含一或多种金属，其与导电柱214中的金属及柱电镀掩模244的材料具有所期望的粘合。例如，粘合层可包含参考柱晶种层216的粘合层所描述的任何金属，且可通过一或多种溅射工艺形成。电镀层可主要包含铜，且可通过溅射工艺形成。
在第二导体晶种层222上形成第二导体电镀掩模246，从而在用于随后形成的第二侧向导体220的区域中暴露所述第二导体晶种层222，如图2G所示。第二导体电镀掩模246可通过参考第一导体电镀掩模242所描述的任何方法形成。用于第二导体电镀掩模246的其它材料及用于形成第二导体电镀掩模246的方法在此实例的范围内。
参考图2G，在第二导体晶种层222上由第二导体电镀掩模246暴露的位置处形成第二主导体224。第二主导体224可具有参考图1的第二主导体124所描述的组合物。第二主导体224可通过铜电镀工艺形成，或任选地通过铜无电极电镀操作形成。第二导体晶种层222及第二主导体224提供微电子装置200的第二侧向导体220。
参考图2H，移除图2G的第二导体电镀掩模246，将第二侧向导体220留在适当位置。第二导体电镀掩模246可通过使用氧自由基的干式工艺(例如灰化工艺或臭氧工艺)移除。替代地，可通过使用例如n-甲基-2-吡咯烷(NMP)或二甲基亚砜(DMSO)等溶剂的湿式工艺移除第二导体电镀掩模246。用于移除第二导体电镀掩模246的抗蚀剂移除化学品的专有配方可从若干供应商处购得。
参考图2I，在由第二主导体224暴露的位置处移除第二导体晶种层222，将第二导体晶种层222留在第二主导体224下方的适当位置。第二导体晶种层222可通过使用酸浴的湿式蚀刻工艺移除。可在移除第二导体晶种层222期间移除第二主导体224的一小部分。
参考图2J，移除图2I的柱电镀掩模244，将主柱218留在适当位置。柱电镀掩模244可通过与用于移除图2G的第二导体电镀掩模246的工艺类似的工艺来移除。用于移除柱电镀掩膜244的其它方法在此实例范围内。
在由主柱218暴露的位置处移除柱晶种层216。柱晶种层216可通过与用于移除第二导体晶种层222的工艺类似的工艺来移除。用于移除柱晶种层216的其它方法在此实例的范围内。柱晶种层216的移除可导致在由主柱218暴露的位置处移除第二主导体224上的第二导体晶种层222，如图2J所描绘。
随后，移除第一导体电镀掩模242，将第一主导体212留在适当位置。可通过与用于移除第二导体电镀掩模246的工艺类似的工艺来移除第一导体电镀掩模242。用于移除第一导体电镀掩模242的其它方法在此实例范围内。
在由第一主导体212暴露的位置处移除第一导体晶种层210，将第一导体晶种层210留在第一主导体212与端子表面206之间适当位置。可通过与用于移除第二导体晶种层222的工艺类似的工艺来移除第一导体晶种层210。用于移除第一导体晶种层210的其它方法在此实例的范围内。
第二侧向导体220具有定位成与第一侧向导体208相对的裸片附接表面226。第一侧向导体208、导电柱214及第二侧向导体220的第一组228提供微电子装置200的凸块接合件230。第二组238第一侧向导体208、导电柱214及第二侧向导体220串联电配置以提供电感器240。同时形成第一组228及第二组238的第一侧向导体208、导电柱214及第二侧向导体220，和与凸块接合件230分开形成电感器240相比，可降低制造成本及复杂性。
参考图2K，囊封材料248可形成在裸片202上，环绕第一侧向导体208及导电柱214，并延伸到第二侧向导体220。以实例的方式，囊封材料248可包含环氧树脂，且可通过注射成型或模压成型形成。囊封材料248可包含磁性粒子250，例如含有铁、镍或钴的铁氧体颗粒或铁磁性粒子。磁性粒子250可提供大于1的囊封材料248的平均相对磁导率(真空的相对磁导率为1)，从而增加电感器240的电感。
参考图2L，可在第二主导体224上形成绝缘层234，以界定用于随后安置的裸片附接材料232的区域，并隔离第二组238中的第二主导体224。绝缘层234可包含参考图1的绝缘层134描述的任何材料。绝缘层234可通过几种方法中的任何一种形成。在此实例的一个版本中，绝缘层234可通过用光敏聚合物材料(例如聚酰亚胺)旋涂微电子装置200，并将光敏聚合物材料暴露于图案化紫外线(UV)光，然后显影光敏聚合物材料来形成。在另一版本中，绝缘层234可通过丝网印刷工艺形成。在进一步版本中，绝缘层234可通过加成工艺(例如材料挤出工艺)形成。用于形成绝缘层234的其它方法在此实例的范围内。
裸片附接材料232形成在凸块接合件230的裸片附接表面226上。裸片附接材料232可包含呈焊膏形式的焊料，其通过丝网印刷工艺或材料挤出工艺形成。裸片附接材料232可包含使用熔融的焊料浴形成的呈焊料层形式的焊料。裸片附接材料232可包含通过丝网印刷工艺或材料挤压工艺形成的导电粘合剂。用于裸片附接材料232的其它组合物及用于形成的方法在此实例的范围内。绝缘层234可用于界定用于裸片附接材料232的区域。
微电子装置200通过将凸块接合件230通过裸片附接材料232电耦合到外部引线236而附接到外部引线236。外部引线236可为含有微电子装置200的封装(例如引线框架或芯片载体)的一部分。替代地，外部引线236可为微电子装置200安装在其上的部分或电路衬底，例如印刷电路板(PCB)。在其中裸片附接材料232包含焊料的此实例的版本中，微电子装置200可通过焊料回流工艺附接到外部引线236。在其中裸片附接材料232包含粘合剂的此实例的版本中，微电子装置200可通过粘合剂固化工艺附接到外部引线236。由第一侧向导体208、导电柱214及第二侧向导体220形成的电感器240可足够稳健，以经受将微电子装置200附接到外部引线236的工艺，而会不发生显著退化。
图3A到图3F是在另一实例形成方法的阶段中描绘的微电子装置的横截面，所述微电子装置具有裸片、及在所述裸片上的凸块接合件及电感器。参考图3A，微电子装置300包含裸片302，其可经实施为离散半导体装置、集成电路、MEMS装置或其它此类微电子裸片。裸片302具有由导电材料形成的端子304，其延伸到裸片302的端子表面306。
在此实例中，端子304可包含一或多个细长端子304a，其跨越用于电感器340的区域中的较低绕组的长度。裸片302的一或多个互连件352也可跨越较低绕组的长度，且可以通过裸片302的通孔354电耦合到细长端子304a。互连件352及通孔354可为裸片302的互连网络的部分。
第一导体晶种层310形成在裸片302上，与端子304接触。第一导体晶种层310可具有如参考图2A的第一导体晶种层210所描述的层结构及组合物，且可如参考第一导体晶种层210所描述那样形成。
在第一导体晶种层310上形成第一导体电镀掩模342，从而暴露用于第一侧向导体308的区域。第一导体电镀掩模342可具有如参考图2A的第一导体电镀掩模242所描述的组合物，且可如参考第一导体电镀掩模242所描述那样形成。
使用第一铜电镀浴356在第一导体晶种层310上由第一导体电镀掩模342暴露的位置处形成第一主导体312。第一铜电镀浴356可在电镀工艺或无电极电镀工艺中实施。在此实例中，在形成第一主导体312之后，第一导体电镀掩模342留在适当位置。第一导体晶种层310在第一主导体312与端子表面306之间的一部分与第一主导体312组合，提供微电子装置300的第一侧向导体308。
参考图3B，在第一导体电镀掩模342及第一侧向导体308上形成柱电镀掩模344，从而暴露第一侧向导体308上用于导电柱314的区域。柱电镀掩模344可具有如图2D的柱电镀掩模244所描述的组合物，且可通过针对柱电镀掩模244所描述的任何方法形成。
在柱电镀掩模344上形成第二导体晶种层358，从而在由柱电镀掩模344暴露的位置与第一侧向导体308接触。第二导体晶种层358可具有如参考图2C的柱晶种层216或图2F的第二导体晶种层222所描述的层结构及组合物，且可如参考柱晶种层216或第一导体晶种层210所描述那样形成。
在第二导体晶种层358上形成第二导体电镀掩模346，从而暴露用于第二侧向导体320的区域。第二导体电镀掩模346可具有如针对图2F的第二导体电镀掩模246所描述的组合物，且可通过针对第二导体电镀掩模246所描述的任何方法形成。
使用第二铜电镀浴362在第二导体晶种层358上由第二导体电镀掩模346暴露的位置处形成第二主导体360。第二铜电镀浴362可在电镀工艺或无电极电镀工艺中实施，且可使用图3A的第一铜电镀浴356的装备及电镀液实施。由柱电镀掩模344侧向环绕的第二导体晶种层358的一部分与由柱电镀掩模344侧向环绕的第二主导体360的一部分组合，提供微电子装置300的导电柱314。由第二导体电镀掩模346侧向环绕的第二导体晶种层358的一部分，与由第二导体电镀掩模346侧向环绕的第二主导体360的一部分组合，提供微电子装置300的第二侧向导体320。与使用单独的电镀浴形成导电柱314及第二侧向导体320相比，从使用一个电镀浴形成的第二主导体360的部分提供导电柱314及第二侧向导体320可降低制造成本及复杂性。
参考图3C，第二侧向导体320具有定位成与第一侧向导体308相对的裸片附接表面326。势垒层364可任选地形成在第二侧向导体320上，覆盖裸片附接表面326。势垒层364可包含一或多种金属，其减少铜及锡的扩散以抑制铜-锡金属间化合物的形成。势垒层364可包含例如镍、钴或钼。当含有锡的焊料(例如银锡焊料)经安置在第二侧向导体320上时，势垒层364可特别有利。势垒层364可通过电镀工艺形成，例如反向脉冲电镀工艺，所述工艺可使势垒层364中的金属达到期望比率，所述比率使用直流(DC)电镀将是难以获得的。
随后移除第二导体电镀掩模346。第二导体电镀掩模346可通过参考图2H所描述的用于移除第二导体电镀掩模246的任何方法移除。
在通过移除第二导体电镀掩模346而暴露的位置处移除第二导体晶种层358。第二导体晶种层358可通过参考图2I描述的用于移除第二导体晶种层222的任何方法移除。
移除柱电镀掩模344。柱电镀掩模344可通过参考图2J所描述的用于移除柱电镀掩模244的任何方法移除。
在通过移除柱电镀掩模344而暴露的位置处移除第一导体晶种层310。可通过参考图2J描述的用于移除第一导体晶种层210的任何方法来移除第一导体晶种层310。第一导体晶种层310的移除可导致通过移除柱电镀掩模344而暴露的第二导体晶种层358的部分的移除。
参考图3D，第一组328第一侧向导体308、导电柱314及第二侧向导体320提供微电子装置300的凸块接合件330。第二组338第一侧向导体308、导电柱314及第二侧向导体320串联电配置以提供电感器340。细长端子304a及互连件352并联地电耦合到电感器340的第一侧向导体308，从而降低电感器340的电阻，且因此增加电感器340的Q因数。
如果存在，那么在势垒层364上在裸片附接表面326上方形成裸片附接材料332。裸片附接材料332可具有针对图2L的裸片附接材料232所描述的任何组合物。裸片附接材料332可通过参考裸片附接材料232所描述的任何方法形成。
可在电感器340的导电柱314之间形成具有大于1的相对磁导率的磁性材料366，其可增加电感器340的电感。磁性材料366可包含例如在聚合物粘结剂(例如环氧树脂)中的铁氧体粒子或含有铁、镍或钴的铁磁性粒子。磁性材料366可使用加成工艺(例如如图3D所描绘的材料挤出工艺368)在电感器340中形成。
参考图3E，微电子装置300通过将凸块接合件330及电感器340通过裸片附接材料332电耦合到外部引线336来附接到外部引线336。外部引线336可为含有微电子装置300的封装的部分，或可为微电子装置300安装在其上的部分或电路衬底。微电子装置300可如参考图2L所描述那样附接到外部引线336。在此实例中，电耦合到电感器340的外部引线336可进一步减少电感器340的电阻，且因此增加电感器340的Q因数。由第一侧向导体308、导电柱314及第二侧向导体320形成的电感器340及凸块接合件330可足够稳健，以经受将微电子装置300附接到外部引线336的工艺，而不会丧失机械完整性，即使电感器340及凸块接合件330未由囊封材料机械支撑。
参考图3F，囊封材料348(可称为底部填充材料)可形成在裸片302上，环绕第一侧向导体308、导电柱314、第二侧向导体320及裸片附接材料332，并延伸到外部引线336。囊封材料348可包含环氧树脂，且可通过注射成型形成。囊封材料348可为第一侧向导体308、导电柱314及第二侧向导体320提供机械支撑。
图4是实例微电子装置的俯视图，所述实例微电子装置具有裸片及在所述裸片上的电感器。微电子装置400包含裸片402，且所述裸片402具有端子表面406。微电子装置400在端子表面406上包含第一侧向导体408、导电柱414及第二侧向导体420。第一组(图4中未展示)第一侧向导体408、导电柱414及第二侧向导体420提供微电子装置400的凸块接合件(图4中未展示)。第二组438第一侧向导体408、导电柱414及第二侧向导体420串联电配置以提供电感器440。在此实例中，电感器440具有环形配置，使得电感器440的第一侧向导体408、导电柱414及第二侧向导体420布置在闭环阵列上。具有大于1的相对磁导率的磁性材料466可位于电感器440中、在第一侧向导体408上方且在第二侧向导体420下方。环形配置可在端子表面406上的紧凑空间中为电感器440提供所期望的电感。电感器440的一或多个节点可电耦合到裸片402中的组件，或电耦合到外部引线(图4中未展示)。
图5是另一实例微电子装置的俯视图，所述实例微电子装置具有裸片及所述裸片上的包含两个电感器的变压器。微电子装置500包含裸片502，且所述裸片502具有端子表面506。微电子装置500在端子表面506上包含第一侧向导体508、导电柱514及第二侧向导体520。第一组(图5中未展示)第一侧向导体508、导电柱514及第二侧向导体520提供微电子装置500的凸块接合件(图5中未展示)。第一第二组538a第一侧向导体508、导电柱514及第二侧向导体520串联电配置以提供第一电感器540a。第二第二组538b第一侧向导体508、导电柱514及第二侧向导体520串联电配置以提供第二电感器540b。具有大于1的相对磁导率的磁性材料566位于第一电感器540a及第二电感器540b中，在第一侧向导体508上方并在第二侧向导体520下方。在此实例中，第一电感器540a具有线性配置，使得第一侧向导体508、导电柱514及第二侧向导体520布置在围绕磁性材料566的圆柱体的表面上。类似地，第二电感器540b具有围绕磁性材料566的线性配置。第一电感器540a及第二电感器540b是变压器570的元件。图5描绘具有围绕磁性材料566的相同数量的绕组的第一电感器540a及第二电感器540b，然而，具有不相等数量的绕组的变压器570的其它配置在此实例的范围内。变压器570可实现在第一电感器540a与第二电感器540b之间传输信号或功率，而不消耗裸片502中的空间。
图6是另一实例微电子装置的俯视图，所述实例微电子装置具有裸片及所述裸片上的包含两个电感器的变压器。微电子装置600包含裸片602，且所述裸片602具有端子表面606。微电子装置600在端子表面606上包含第一侧向导体608、导电柱614及第二侧向导体620。第一组(图6中未展示)第一侧向导体608、导电柱614及第二侧向导体620提供微电子装置600的凸块接合件(图6中未展示)。第一第二组638a第一侧向导体608、导电柱614及第二侧向导体620串联电配置以提供第一电感器640a。第二第二组638b第一侧向导体608、导电柱614及第二侧向导体620串联电配置以提供第二电感器640b。在此实例中，第一电感器640a及第二电感器640b具有线性配置，且相互交叉指以形成变压器670。变压器670的交叉配置可实现在第一电感器640a与第二电感器640b之间传输信号或功率，而无需在第一电感器640a或第二电感器640b中安置磁性材料。
本文所描述的实例的各种特征可组合在实例微电子装置的其它表现形式中。例如，图1的微电子装置100可通过参考图2A到2L的方法所描述的步骤、参考图3A到3F的方法所描述的步骤或另一方法形成。本文所描述的微电子装置可使用任何方法形成，例如在2018年9月7日申请的具有专利申请案序列号16/030371、代理人案号TI-78661的共同转让专利申请案中描述的方法，其通过引用的方式并入本文中，但不被承认为与描述有关的现有技术。图1的凸块接合件130可具有图3C的势垒层364。图1的微电子装置100可包含具有磁性粒子250的囊封材料248，如参考图2K所描述，或可包含磁性材料366，如参考图3D所描述。
尽管上文已描述本描述的各种实施例，但它们仅作为实例而不是限制来呈现。在本文的描述中可对所描述的实施例进行许多改变，而不脱离描述的精神或范围。因此，描述的广度及范围不应受到上述任何实施例的限制。而是，描述的范围应在所附权利要求及其等效物中界定。

Claims (20)

1.一种微电子装置，其包括：
裸片，其具有延伸到所述裸片的端子表面的端子；
第一侧向导体，其沿所述端子表面延伸，其中所述第一侧向导体的至少一部分电耦合到所述端子的至少一部分；
导电柱，其位于所述第一侧向导体上，所述导电柱从所述端子表面垂直延伸；及
第二侧向导体，其位于所述导电柱上，所述第二侧向导体定位成与所述第一侧向导体相对，所述第二侧向导体在与所述端子表面平行的平面内侧向延伸；
其中第一组所述第一侧向导体、所述导电柱及所述第二侧向导体提供所述微电子装置的凸块接合件；且
其中第二组所述第一侧向导体、所述导电柱及所述第二侧向导体串联地电耦合以形成所述微电子的电感器。
2.根据权利要求1所述的微电子装置，其中所述第一侧向导体包含铜。
3.根据权利要求2所述的微电子装置，其中所述第一侧向导体中的每一者包含所述端子表面上的第一导体晶种层，所述第一导体晶种层包含从由钛、钨、铬及镍组成的群组中选择的至少一种金属。
4.根据权利要求1所述的微电子装置，其中所述第一侧向导体具有3微米到30微米的厚度。
5.根据权利要求1所述的微电子装置，其中所述导电柱包含铜，且具有平行于所述端子表面测量的25微米到50微米的宽度，具有也平行于所述端子表面测量的25微米到300微米的长度，并具有垂直于所述端子表面测量的30微米到100微米的高度。
6.根据权利要求1所述的微电子装置，其中所述导电柱中的每一者包含所述第一侧向导体上的柱晶种层，所述柱晶种层包含从由钛、铬及镍组成的群组中选择的至少一种金属。
7.根据权利要求1所述的微电子装置，其中：
所述第二侧向导体包含铜；且
所述第二侧向导体中的每一者包含所述导电柱上的第二导体晶种层，所述第二导体晶种层包含从由钛、铬及镍组成的群组中选择的至少一种金属。
8.根据权利要求1所述的微电子装置，其中所述第二侧向导体具有3微米到30微米的厚度。
9.根据权利要求1所述的微电子装置，其包含所述第二侧向导体的至少一部分上的裸片附接材料，所述裸片附接材料选自由焊料及粘合剂组成的群组。
10.根据权利要求1所述的微电子装置，其包含定位于所述电感器中的磁性材料，所述磁性材料具有大于1的平均相对磁导率，其中真空的相对磁导率为1。
11.根据权利要求10所述的微电子装置，其中所述磁性材料包含定位于所述裸片上的具有磁性粒子的囊封材料。
12.根据权利要求10所述的微电子装置，其中所述电感器具有线性配置，在所述线性配置中所述电感器的所述第一侧向导体、所述导电柱及所述第二侧向导体经布置成线性阵列。
13.根据权利要求10所述的微电子装置，其中所述电感器具有环形配置，在所述环形配置中所述电感器的所述第一侧向导体、所述导电柱及所述第二侧向导体经布置成闭环阵列。
14.一种形成微电子装置的方法，其包括：
获得裸片，所述裸片具有延伸到所述裸片的端子表面的端子；
形成沿所述端子表面延伸的第一侧向导体，使得所述第一侧向导体的至少一部分与所述端子的至少一部分接触；
在所述第一侧向导体上形成导电柱，使得所述导电柱从所述端子表面垂直延伸；及
在所述导电柱上形成第二侧向导体，所述第二侧向导体定位成与所述第一侧向导体相对，使得所述第二侧向导体在与所述端子表面平行的平面内侧向延伸；
其中第一组所述第一侧向导体、所述导电柱及所述第二侧向导体提供所述微电子装置的凸块接合件；且
其中第二组所述第一侧向导体、所述导电柱及所述第二侧向导体串联地电耦合以形成所述微电子装置的电感器。
15.根据权利要求14所述的方法，其中形成所述第一侧向导体包含：
在所述端子表面上形成第一导体晶种层，使得所述第一导体晶种层与所述端子接触，所述第一导体晶种层包含从由钛、钨、铬及镍组成的群组中选择的至少一种金属；
在所述第一导体晶种层上方形成第一导体电镀掩模，使得所述第一导体电镀掩模在用于所述第一侧向导体的区域中暴露所述第一导体晶种层；
使用电镀工艺，在所述第一导体晶种层上由所述第一导体电镀掩模暴露的位置处形成第一主导体；
移除所述第一导体电镀掩模；及
在由所述第一主导体暴露的位置处移除所述第一导体晶种层，使得所述第一主导体及在所述第一主导体与所述端子表面之间的所述第一导体晶种层提供所述第一侧向导体。
16.根据权利要求14所述的方法，其中形成所述导电柱包含：
形成与所述第一侧向导体接触的柱晶种层，所述柱晶种层包含从由钛、铬及镍组成的群组中选择的至少一种金属；
在所述柱晶种层上方形成柱电镀掩模，使得所述柱电镀掩模在用于所述导电柱的区域中暴露所述柱晶种层；
使用电镀工艺，在所述柱晶种层上由所述柱电镀掩模暴露的位置处形成主柱；
移除所述柱电镀掩模；及
在由所述主柱暴露的位置处移除所述柱晶种层，使得所述主柱及在所述主柱与所述第一侧向导体之间的所述柱晶种层提供所述导电柱。
17.根据权利要求14所述的方法，其中形成所述第二侧向导体包含：
形成与所述导电柱接触的第二导体晶种层，所述第二导体晶种层包含从由钛、钨、铬及镍组成的群组中选择的至少一种金属；
在所述第二导体晶种层上方形成第二导体电镀掩模，使得所述第二导体电镀掩模在用于所述第二侧向导体的区域中暴露所述第二导体晶种层；
使用电镀工艺，在所述第二导体晶种层上由所述第二导体电镀掩模暴露的位置处形成第二主导体；
移除所述第二导体电镀掩模；及
在由所述第二主导体暴露的位置处移除所述第二导体晶种层，使得所述第二主导体及在所述第一主导体与所述导电柱之间的所述第二导体晶种层提供所述第二侧向导体。
18.根据权利要求14所述的方法，其中形成所述导电柱及形成所述第二侧向导体包含：
在所述第一侧向导体上方形成柱电镀掩模，使得所述柱电镀掩模在用于所述导电柱的区域中暴露所述第一侧向导体；
在所述柱电镀掩模上形成第二导体晶种层，使得所述第二导体晶种层在由所述柱电镀掩模暴露的位置处与所述第一侧向导体接触；
在所述第二导体晶种层上方形成第二导体电镀掩模，使得所述第二导体电镀掩模在用于所述第二侧向导体的区域中暴露所述第二导体晶种层；
使用电镀工艺，在所述第二导体晶种层上由所述第二导体电镀掩模暴露的位置处形成第二主导体，使得：
由所述柱电镀掩模侧向环绕的所述第二导体晶种层的一部分与由所述柱电镀掩模侧向环绕的所述第二主导体的一部分组合，提供所述导电柱；及
由所述第二导体电镀掩模侧向环绕的所述第二导体晶种层的一部分与由所述第二导体电镀掩模侧向环绕的所述第二主导体的一部分组合，提供所述第二侧向导体；
移除所述第二导体电镀掩模；
在由所述第二主导体暴露的位置处移除所述第二导体晶种层；及
移除所述柱电镀掩模。
19.根据权利要求14所述的方法，其包含在所述电感器中形成磁性材料，所述磁性材料具有大于1的平均相对磁导率，其中真空的相对磁导率为1。
20.根据权利要求14所述的方法，其包含：
在所述第二侧向导体的至少一部分上形成裸片附接材料，所述裸片附接材料选自由焊料与粘合剂组成的群组；及
通过所述裸片附接材料将所述凸块接合件电耦合到外部引线。
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