CN112953516B - 一种低功耗小数分频锁相环电路 - Google Patents

一种低功耗小数分频锁相环电路 Download PDF

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CN112953516B
CN112953516B CN202110110734.5A CN202110110734A CN112953516B CN 112953516 B CN112953516 B CN 112953516B CN 202110110734 A CN202110110734 A CN 202110110734A CN 112953516 B CN112953516 B CN 112953516B
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高翔
金高锋
冯飞
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Zhejiang University ZJU
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
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    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/099Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/10Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/101Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop
    • H03L7/102Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop the additional signal being directly applied to the controlled loop oscillator
    • H03L7/103Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop the additional signal being directly applied to the controlled loop oscillator the additional signal being a digital signal
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    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract

本发明公开一种低功耗小数分频锁相环电路,其包括鉴相模块、电压到电流转换模块、环路滤波器、压控振荡器、分频器和数字逻辑模块;鉴相模块、电压到电流转换模块、环路滤波器、压控振荡器、分频器依次连接;参考信号从鉴相模块输入,鉴相模块将参考信号和分频器输出的带有量化误差的反馈信号进行鉴相,并补偿小数分频产生的量化相位误差,输出补偿后的鉴相结果给电压到电流转换模块;小数分频产生的量化误差通过数字域转换到电压域或者直接耦合到鉴相模块中的相位误差信号完成量化误差的补偿。本发明通过将量化误差补偿和采样鉴相两个过程中的边沿转换过程进行合并,减少边沿转换的次数,从而减小功耗,完成小数分频量化误差的补偿。

Description

一种低功耗小数分频锁相环电路
技术领域
本发明涉及到射频集成电路中频率的产生和综合领域,具体涉及一种低功耗小数分频锁相环电路。
背景技术
锁相环在电子系统中被广泛应用,可以在通信系统中作为本振信号,在数模转换中作为采样时钟等等。锁相环是一种负反馈系统,通过比较参考信号与反馈信号的相位误差,并控制压控振荡器调整输出信号的频率,实现输出信号频率是参考信号的固定倍数,相位与参考信号保持同步,也就是将输出信号锁定到参考信号。
在锁相环的反馈回路中,分频器将相对于参考信号频率固定倍数的振荡信号进行分频反馈给鉴相模块。为了实现小数分频,会将分频器的分频比进行调制,用一组整数的分频比序列,等效地动态实现小数分频。分频比的动态调整通过累加微分调制器进行,累加积分调制器将小数部分进行累加并量化得到实时的分频比。在量化的过程中,实际的分频比会与理想的小数分频比存在误差,在反馈信号中表现为存在量化的相位误差,导致锁相环输出的信号频谱中存在量化噪声。
如图1所示,在传统的小数锁相环中,反馈回路或参考路径会插入数字到时间转换器,补偿由于小数分频带来的量化误差。在数字到时间转换器中,数字逻辑模块生成的补偿信号会控制边沿产生的过程,对相位进行补偿。补偿后的信号再在采样鉴相器中完成与另一路信号的相位比较,转换为数字域或者电压域的控制信号。在补偿的过程中,数字到时间转换器会产生带有一定斜率的边沿,之后会转换为陡峭的边沿,在采样鉴相器中,陡峭的边沿会再次产生带有一定斜率的边沿。在补偿和鉴相的过程中,有多次边沿转换的操作,会增加一定的功耗。
发明内容
针对现有技术的不足,本发明提供一种低功耗小数分频锁相环电路,该电路能够在有效的对小数分频带来的量化误差进行补偿的情况下,减小功耗。
本发明的目的通过如下的技术方案来实现:
一种低功耗小数分频锁相环电路,该电路包括鉴相模块、电压到电流转换模块、环路滤波器、压控振荡器、分频器和数字逻辑模块;所述鉴相模块、电压到电流转换模块、环路滤波器、压控振荡器、分频器依次连接;参考信号从鉴相模块输入,鉴相模块将所述参考信号和所述分频器输出的带有量化误差的反馈信号进行鉴相,并补偿小数分频产生的量化相位误差,输出补偿后的鉴相结果给电压到电流转换模块;
所述小数分频产生的量化误差通过数字域转换到电压域或者直接调整鉴相模块中的电流或者电容完成量化误差的补偿。
进一步地,所述鉴相模块为固定斜率采样电路,其包括电流源、充电开关、充电电容、预充电开关、数字到电压转换器、保持开关和保持电容,所述电流源与充电开关的一端连接,数字到电压转换器与预充电开关的一端相连,保持电容的一端与保持开关的一端相连,所述充电开关、预充电开关、保持开关的另一端均与充电电容的一端相连;充电电容和保持电容的另一端均接地;数字到电压转换器的另一端与数字逻辑模块相连;
所述数字到电压转换器输出不同的电压调整充电电容的起始电压值,对小数分频产生的量化误差进行补偿;控制电流源对充电电容的充电时间,完成参考信号与反馈信号的相位比较。
进一步地,所述鉴相模块的时序逻辑具体为:
当反馈信号或参考信号中的一个的上升沿到来时,充电信号控制充电开关闭合,使电流源对充电电容进行充电;
当反馈信号或参考信号中的另外一个的上升沿到来时,充电信号控制充电开关断开,停止电流源对充电电容进行充电,同时采样信号控制保持开关闭合,保持电容对充电电容上的电压进行采样保持;
在采样保持结束之后,采样信号控制断开保持开关,预充电信号控制预充电开关闭合,将数字到电压转换器输出连接到充电电容,数字到电压转换器接收所述数字逻辑模块的补偿信号,调整充电电容上的起始充电电压;完成预充电后,预充电信号控制断开预充电开关,等待充电开关闭合。
进一步地,所述鉴相模块为可变斜率采样电路,包括可变电流源、可变充电电容、保持电容、充电开关、复位开关和保持开关;其中,可变电流源与充电开关的一端连接,保持电容与保持开关的一端连接,充电开关、保持开关、复位开关的另一端均与可变充电电容的一端连接,可变充电电容、复位开关、保持电容的另一端均接地;
通过调整可变电流源输出电流的大小或者可变充电电容的大小改变充电斜坡的斜率,对小数分频产生的量化误差进行补偿;控制可变电流源对可变充电电容的充电时间,完成参考信号与反馈信号的相位比较。
进一步地,所述鉴相模块的时序逻辑具体为:
当反馈信号或参考信号其中之一的上升沿到来时,充电信号控制闭合充电开关,使可变电流源对可变充电电容进行充电;
当反馈信号或参考信号另外一个的上升沿到来时,充电信号控制断开充电开关,停止可变电流源对可变充电电容充电,同时采样信号控制闭合保持开关,保持电容对可变充电电容上的电压进行采样保持;
在采样保持结束之后,采样信号控制断开保持开关,复位信号控制闭合复位开关,将可变充电电容连接到地,使起始充电电压复位为零;接收所述数字逻辑模块的补偿信号,调整可变充电电容的电容值或可变电流源的电流;复位信号控制断开复位开关,等待充电开关闭合。
进一步地,所述的压控振荡器为环形振荡器或LC振荡器。
本发明的有益效果如下:
本发明的低功耗小数分频锁相环电路通过将量化误差补偿和采样鉴相两个过程中的边沿转换过程进行合并,减少边沿转换的次数,从而减小功耗,完成小数分频量化误差的补偿。
附图说明
图1为传统的小数分频锁相环电路的结构示意图;
图2为本发明的低功耗小数分频锁相环电路的结构示意图;
图3为本发明鉴相模块的其中一种实施方式原理示意图;
图4为本发明鉴相模块的其中一种实施方式中各路控制信号的时序示意图;
图5为本发明鉴相模块的另一个实施方式的原理示意图;
图6为本发明鉴相模块的另一个实施方式中各路控制信号的时序示意图。
具体实施方式
下面根据附图和优选实施例详细描述本发明,本发明的目的和效果将变得更加明白,应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。
如图2所示,本发明的低功耗小数分频锁相环电路包括鉴相模块、电压电流转换模块、环路滤波器、压控振荡器、分频模块和数字逻辑模块。所述鉴相模块、电压到电流转换模块、环路滤波器、压控振荡器、分频器依次连接;参考信号从鉴相模块输入,鉴相模块将所述参考信号和所述分频器输出的带有量化误差的反馈信号进行鉴相,并补偿小数分频产生的量化相位误差,输出补偿后的鉴相结果给电压到电流转换模块;电压到电流转换模块将鉴相模块输出的鉴相结果采样电压与输入的参考电压进行比较,输出电流;所述环路滤波器将所述电压到电流转换模块输出的电流进行积分,并对其滤波,得到控制电压信号,用于控制所述压控振荡器输出对应频率的振荡信号;所述分频器对压控振荡器输出的振荡信号进行分频,并在数字逻辑模块调制的分频比下实现小数分频,产生的分频信号反馈回所述鉴相模块,进行反馈调节。
所述数字逻辑模块输出经过调制的整数分频比序列到分频模块,完成小数分频,并将量化误差继续计算得到补偿信号,再输出到鉴相模块;
所述小数分频产生的量化误差通过数字域转换到电压域或者直接调整鉴相模块中的电流或者电容完成量化误差的补偿。
压控振荡器为环形振荡器或LC振荡器。
该系统结构相较于传统的小数分频锁相环,将数字到时间转换器与采样鉴相器进行结合,能够在实现鉴相的同时完成量化误差的补偿,减少了边沿转换的次数。从而,该结构有效的实现了量化噪声的补偿和相位误差的检测,并减小了功耗。
作为其中一种实施方式,如图3所示,鉴相模块为固定斜率采样电路,其包括电流源、充电开关、充电电容、预充电开关、数字到电压转换器、保持开关和保持电容,电流源与充电开关的一端连接,数字到电压转换器与预充电开关的一端相连,保持电容的一端与保持开关的一端相连,所述充电开关、预充电开关、保持开关的另一端均与充电电容的一端相连;充电电容和保持电容的另一端均接地;数字到电压转换器的另一端与数字逻辑模块相连。
电流源对充电电容进行充电,保持电容负责保持充电结束时刻的电压,数字到电压转换器接收数字逻辑模块的补偿信号,输出通过预充电开关与充电电容相连,调整每次充电的起始电压。所述鉴相模块通过时序逻辑进行控制,利用参考信号和反馈信号产生时序信号控制电流源、保持电容和数字到电压转换器工作,如图4所示,时序逻辑的控制过程如下:
当反馈信号或参考信号的一个的上升沿到来时,充电信号控制充电开关闭合,使电流源对充电电容进行充电;
当反馈信号或参考信号另外一个的上升沿到来时,充电信号控制充电开关断开,停止电流源对充电电容进行充电,采样信号控制保持开关闭合,保持电容对充电电容上的电压进行采样保持;
在采样保持结束之后,采样信号控制断开保持开关,预充电信号控制预充电开关闭合,将数字到电压转换器输出连接到充电电容,数字到电压转换器接收所述数字逻辑模块的补偿信号,调整充电电容上的起始充电电压;完成预充电后,预充电信号控制断开预充电开关,等待充电开关闭合。
数字到电压转换器采用R2R结构,包括二进制电阻阵列以及温度计码电阻阵列,根据数字逻辑反馈的补偿信号输出相应的补偿电压。
通过数字到电压转换器输出不同的电压调整充电电容的起始电压值,对小数分频产生的量化误差进行补偿,再通过控制电流源对充电电容的充电时间完成参考信号与反馈信号的相位比较,减少了在参考路径或者反馈路径中插入数字到时间转换器的采样型小数分频锁相环中的边沿转换次数,有效地降低了功耗,减少了噪声和非线性度的来源。
如图5所示,作为另一种实施方式,鉴相模块为可变斜率采样电路,包括可变电流源、可变充电电容、保持电容、充电开关、复位开关和保持开关;其中,可变电流源与充电开关的一端连接,保持电容与保持开关的一端连接,充电开关、保持开关、复位开关的另一端均与可变充电电容的一端连接,可变充电电容、复位开关、保持电容的另一端均接地。
通过调整可变电流源输出电流的大小或者可变充电电容的大小改变充电斜坡的斜率,对小数分频产生的量化误差进行补偿;控制可变电流源对可变充电电容的充电时间,完成参考信号与反馈信号的相位比较。
如图6所示,鉴相模块的时序逻辑具体为:
当反馈信号或参考信号其中之一的上升沿到来时,充电信号控制闭合充电开关,使可变电流源对可变充电电容进行充电;
当反馈信号或参考信号另外一个的上升沿到来时,充电信号控制断开充电开关,停止可变电流源对可变充电电容充电,同时采样信号控制保持开关闭合,保持电容对可变充电电容上的电压进行采样保持;
在采样保持结束之后,采样信号控制断开保持开关,复位信号控制闭合复位开关,将可变充电电容连接到地,使起始充电电压复位为零;接收所述数字逻辑模块的补偿信号,调整可变充电电容的电容值或可变电流源的电流;复位信号控制断开复位开关,等待充电开关闭合。
电流源可以采用可变电流源阵列,根据数字信号逻辑反馈的补偿信号调整输出电流的大小。充电电容可以采用可变电容阵列,根据数字信号逻辑反馈的补偿信号调整充电电容的大小。
通过调整可变电流源输出电流的大小或者可变充电电容的大小改变充电斜坡的斜率,对小数分频产生的量化误差进行补偿,再通过控制电流源对充电电容的充电时间完成参考信号与反馈信号的相位比较,减少了在参考路径或者反馈路径中插入数字到时间转换器的采样型小数分频锁相环中的边沿转换次数,有效地降低了功耗,减少了噪声和非线性度的来源。
本领域普通技术人员可以理解,以上所述仅为发明的优选实例而已,并不用于限制发明,尽管参照前述实例对发明进行了详细的说明,对于本领域的技术人员来说,其依然可以对前述各实例记载的技术方案进行修改,或者对其中部分技术特征进行等同替换。凡在发明的精神和原则之内,所做的修改、等同替换等均应包含在发明的保护范围之内。

Claims (4)

1.一种低功耗小数分频锁相环电路,其特征在于,该电路包括鉴相模块、电压到电流转换模块、环路滤波器、压控振荡器、分频器和数字逻辑模块;所述鉴相模块、电压到电流转换模块、环路滤波器、压控振荡器、分频器依次连接;参考信号从鉴相模块输入,鉴相模块将所述参考信号和所述分频器输出的带有量化误差的反馈信号进行鉴相,并补偿小数分频产生的量化相位误差,输出补偿后的鉴相结果给电压到电流转换模块;
所述小数分频产生的量化误差通过数字域转换到电压域或者直接调整鉴相模块中的电流或者电容完成量化误差的补偿;
所述鉴相模块为固定斜率采样电路,其包括电流源、充电开关、充电电容、预充电开关、数字到电压转换器、保持开关和保持电容,所述电流源与充电开关的一端连接,数字到电压转换器与预充电开关的一端相连,保持电容的一端与保持开关的一端相连,所述充电开关、预充电开关、保持开关的另一端均与充电电容的一端相连;充电电容和保持电容的另一端均接地;数字到电压转换器的另一端与数字逻辑模块相连;
所述数字到电压转换器输出不同的电压调整充电电容的起始电压值,对小数分频产生的量化误差进行补偿;控制电流源对充电电容的充电时间,完成参考信号与反馈信号的相位比较;
所述鉴相模块的时序逻辑具体为:
当反馈信号或参考信号中的一个的上升沿到来时,充电信号控制充电开关闭合,使电流源对充电电容进行充电;
当反馈信号或参考信号中的另外一个的上升沿到来时,充电信号控制充电开关断开,停止电流源对充电电容进行充电,同时采样信号控制保持开关闭合,保持电容对充电电容上的电压进行采样保持;
在采样保持结束之后,采样信号控制断开保持开关,预充电信号控制预充电开关闭合,将数字到电压转换器输出连接到充电电容,数字到电压转换器接收所述数字逻辑模块的补偿信号,调整充电电容上的起始充电电压;完成预充电后,预充电信号控制断开预充电开关,等待充电开关闭合。
2.根据权利要求1所述的低功耗小数分频锁相环电路,其特征在于,所述的压控振荡器为环形振荡器或LC振荡器。
3.一种低功耗小数分频锁相环电路,其特征在于,该电路包括鉴相模块、电压到电流转换模块、环路滤波器、压控振荡器、分频器和数字逻辑模块;所述鉴相模块、电压到电流转换模块、环路滤波器、压控振荡器、分频器依次连接;参考信号从鉴相模块输入,鉴相模块将所述参考信号和所述分频器输出的带有量化误差的反馈信号进行鉴相,并补偿小数分频产生的量化相位误差,输出补偿后的鉴相结果给电压到电流转换模块;
所述小数分频产生的量化误差通过数字域转换到电压域或者直接调整鉴相模块中的电流或者电容完成量化误差的补偿;
所述鉴相模块为可变斜率采样电路,包括可变电流源、可变充电电容、保持电容、充电开关、复位开关和保持开关;其中,可变电流源与充电开关的一端连接,保持电容与保持开关的一端连接,充电开关、保持开关、复位开关的另一端均与可变充电电容的一端连接,可变充电电容、复位开关、保持电容的另一端均接地;
通过调整可变电流源输出电流的大小或者可变充电电容的大小改变充电斜坡的斜率,对小数分频产生的量化误差进行补偿;控制可变电流源对可变充电电容的充电时间,完成参考信号与反馈信号的相位比较;
所述鉴相模块的时序逻辑具体为:
当反馈信号或参考信号其中之一的上升沿到来时,充电信号控制闭合充电开关,使可变电流源对可变充电电容进行充电;
当反馈信号或参考信号另外一个的上升沿到来时,充电信号控制断开充电开关,停止可变电流源对可变充电电容充电,同时采样信号控制闭合保持开关,保持电容对可变充电电容上的电压进行采样保持;
在采样保持结束之后,采样信号控制断开保持开关,复位信号控制闭合复位开关,将可变充电电容连接到地,使起始充电电压复位为零;接收所述数字逻辑模块的补偿信号,调整可变充电电容的电容值或可变电流源的电流;复位信号控制断开复位开关,等待充电开关闭合。
4.根据权利要求3所述的低功耗小数分频锁相环电路,其特征在于,所述的压控振荡器为环形振荡器或LC振荡器。
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