CN112951904B - NPN transistor with low on-resistance and high amplification factor and preparation method thereof - Google Patents
NPN transistor with low on-resistance and high amplification factor and preparation method thereof Download PDFInfo
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- CN112951904B CN112951904B CN202110336608.1A CN202110336608A CN112951904B CN 112951904 B CN112951904 B CN 112951904B CN 202110336608 A CN202110336608 A CN 202110336608A CN 112951904 B CN112951904 B CN 112951904B
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- 238000003199 nucleic acid amplification method Methods 0.000 title claims abstract description 28
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- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 47
- 239000011574 phosphorus Substances 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims abstract description 30
- 238000005468 ion implantation Methods 0.000 claims abstract description 24
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- 238000002513 implantation Methods 0.000 claims description 107
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- 238000002347 injection Methods 0.000 claims description 27
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- 238000000137 annealing Methods 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 230000004913 activation Effects 0.000 claims description 8
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
Abstract
The invention discloses a low-on-resistance and high-amplification-factor NPN transistor and a preparation method thereof.A BNW area is formed on a P-type substrate through N-type ion implantation; forming a DNW area with a certain thickness at the bottom of the BNW area; a closed loop field region isolation is respectively formed at the edge and the inner part of the upper end surface of the BNW region; a closed-loop deep phosphorus region is formed on the BNW region, the deep phosphorus region is communicated with the DNW region, and the deep phosphorus region is positioned between the two field region isolations; forming a base region on the BNW region, wherein the base region is positioned in the deep phosphorus region; forming closed-loop polycrystalline isolation on the upper end face of the base region; forming an emitter region on the base region, forming a closed-loop collector region on the BNW region, wherein the emitter region is positioned in the polycrystalline isolation, the collector region is positioned between the two field region isolations, and the collector region is overlapped with the deep phosphorus region; and forming a closed-loop base region contact region on the base region, wherein the base region contact region is positioned outside the polycrystalline isolation. The NPN formed by the invention has small on-resistance, high amplification factor and simple process flow.
Description
Technical Field
The invention belongs to the field of manufacturing of semiconductor devices, and particularly relates to an NPN transistor with low on-resistance and high amplification factor and a preparation method thereof.
Background
The main parameters of the bipolar transistor are amplification factor and CE junction breakdown voltage, and the main process factors influencing the amplification factor comprise the impurity concentration ratio of an emitter region/a base region and the width of the base region; the CE junction breakdown voltage is mainly affected by the collector region concentration and the base region width. The BiCMOS in the industry adopts a P-type single crystal substrate of the CMOS, and a longitudinal NPN tube is a mainly adopted device; and the transverse PNP tube is a parasitic device completely, the amplification factor is small, and the circuit design is less adopted.
The longitudinal NPN tube is realized through a CMOS process flow, a collector region of the longitudinal NPN tube is formed by means of an N-well injection process of a PMOS tube, an emitter region is formed by means of N-type source-drain doping injection, and a base region is an independent injection process. The on-resistance of the vertical NPN device thus obtained is large.
In order to obtain a high-performance vertical NPN transistor, corresponding process levels must be added to adjust key process parameters affecting the vertical NPN transistor, forming CMOS and bipolar devices on the epitaxy. The BiCMOS with the epitaxy can realize complete isolation of bipolar devices, has small on-resistance and good characteristics, but the whole process flow is complicated by adding an epitaxy module, and the on-state and isolation of the epitaxy need to be considered.
In addition, in the traditional BiCMOS process, source-drain annealing or hole dielectric layer backflow is adopted as an NPN transistor injection doping activating means. The temperature of source-drain annealing or hole dielectric layer reflux is 800-1000 ℃, the activation rate of injection doping is low, and the longitudinal NPN transistor has large on-resistance and smaller amplification factor.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides the NPN transistor with low on-resistance and high amplification factor and the preparation method thereof, the on-resistance is small, and the process flow is simple.
In order to solve the technical problems, the invention is realized by the following technical scheme:
a preparation method of a low on-resistance and high amplification factor NPN transistor comprises the following steps:
providing a P-type substrate, and forming a BNW region on the P-type substrate through N-type ion implantation and drive-in;
forming a DNW region with a certain thickness at the bottom of the BNW region through N-type ion implantation;
a closed loop field region isolation is formed at the edge and the inner part of the upper end surface of the BNW region respectively;
forming a closed-loop deep phosphorus region on the BNW region through N-type ions by multiple step implantation, wherein the deep phosphorus region is communicated with the DNW region and is positioned between the two field region isolations;
forming a base region on the BNW region through P-type ion implantation, wherein the base region is positioned in the deep phosphorus region;
forming closed-loop polycrystalline isolation on the upper end face of the base region;
forming side walls on two side walls of the polycrystalline isolation;
forming an emitter region on the base region and a collector region of a closed loop on the BNW region by N-type ion implantation, wherein the emitter region is positioned in the polycrystalline isolation, the collector region is positioned between the two field region isolations, and the collector region is overlapped with the deep phosphorus region;
forming a closed-loop base region contact area on the base region through P-type ion implantation, wherein the base region contact area is positioned outside the polycrystalline isolation;
and (5) performing high-temperature rapid annealing to complete the activation of the injected impurities.
Further, by N-type ion implantation, the DNW region is formed at the bottom of the BNW region, specifically: the implantation element is P, the implantation energy is 2-4 MeV, and the implantation dosage is 1-2 x 10 13 cm -2 。
Further, the field region isolation is formed by silicon nitride/silicon oxide deposition, silicon nitride/silicon oxide lithography and etching, oxidation, and silicon nitride/silicon oxide lift-off.
Further, forming the deep phosphorus region on the BNW region by multiple step-by-step implantation of N-type ions, specifically, the following five steps:
the first step, the implantation element is P, the implantation energy is 2-2.5 MeV, and the implantation dosage is 1-2 x 10 15 cm -2 (ii) a The second step, the implantation element is P, the implantation energy is 1.5MeV, and the implantation dose is 1-2 × 10 15 cm -2 (ii) a Thirdly, the implantation element is P, the implantation energy is 1MeV, and the implantation dosage is 1-2 multiplied by 10 15 cm -2 (ii) a The fourth step, the implantation element is P, the implantation energy is 500keV, and the implantation dosage is 1-2 × 10 15 cm -2 (ii) a The fifth step, the implantation element is P, the implantation energy is 100keV, and the implantation dosage is 1-2 × 10 15 cm -2 。
Further, the poly-isolation is formed by poly-deposition, poly-lithography and etching.
Further, the side wall is formed through side wall deposition and etching.
Furthermore, the activation of the injection doping is completed by high-temperature rapid annealing at the temperature of 1000-1100 ℃ for 10-30 s.
An NPN transistor with low on-resistance and high amplification factor is manufactured by applying the manufacturing method;
the BNW type substrate comprises a P type substrate, wherein a BNW area is formed on the P type substrate; forming a DNW region with a certain thickness at the bottom of the BNW region; a closed loop field region isolation is formed at the edge and the inner part of the upper end surface of the BNW region respectively; a closed-loop deep phosphorus region is formed on the BNW region and is communicated with the DNW region, and the deep phosphorus region is positioned between the two field region isolations; a base region is formed on the BNW region and is positioned in the deep phosphorus region; a closed-loop polycrystalline isolation is formed on the upper end face of the base region; forming side walls on two side walls of the polycrystalline isolation; an emitter region is formed on the base region, a closed-loop collector region is formed on the BNW region, the emitter region is positioned in the polycrystalline isolation, the collector region is positioned between the two field region isolations, and the collector region and the deep phosphorus region are overlapped; and a closed-loop base region contact area is formed on the base region, and the base region contact area is positioned outside the polycrystalline isolation.
Further, the emitter region is located at the center of the base region.
Compared with the prior art, the invention has at least the following beneficial effects: the invention effectively reduces the buried layer resistance of the substrate and the series resistance of the NPN collector region through DNW implantation and deep phosphorus multiple step implantation. The NPN on-resistance is mainly formed by serially connecting the buried layer resistance of the substrate and the series resistance of the NPN collector region, so that the NPN on-resistance is reduced as a whole. Compared with an epitaxial-based BiCMOS process, the process has the advantages of simple process and less defects. Specifically, the invention provides a novel NPN transistor structure aiming at the influence mechanism of the on-resistance of an NPN transistor in a BiCMOS process. This new NPN transistor is formed by selective ion implantation: a thicker buried layer is formed below the bipolar device through DNW implantation, the buried layer resistance of the substrate is effectively reduced, a thicker and continuous collector region is formed through multiple stepped deep phosphorus implantation, and the series resistance of an NPN collector region is effectively reduced. Meanwhile, the invention increases the activation rate of injection doping by adding high-temperature rapid annealing with the temperature of 1000-1100 ℃ and the time of 10-30 s, thereby reducing the on-resistance of the NPN transistor and improving the amplification factor of the NPN transistor. The NPN transistor with the traditional structure and the novel NPN transistor with low on-resistance and high amplification factor provided by the invention are respectively tested: the on-resistance of the novel NPN transistor is 60% of that of the NPN transistor with the traditional structure, and the amplification factor of the novel NPN transistor is 5 times of that of the NPN transistor with the traditional structure.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a longitudinal cross-sectional view of an NPN transistor of a conventional structure;
FIG. 2 is a top view of FIG. 1;
FIG. 3 is a longitudinal cross-sectional view of a low on-resistance, high magnification NPN transistor of the present invention;
FIG. 4 is a top view of FIG. 3;
fig. 5 to 18 are schematic diagrams illustrating a manufacturing process of a low on-resistance and high amplification NPN transistor according to the present invention.
In the figure: 1-BNW region; a 2-DNW region; 3-field isolation; 4-deep phosphorus region; 5-base region; 6-polycrystalline isolation; 7-side wall; 8-an emission area; 9-a collector region; 10-base region contact area; 11-P type substrate; 21-a first photoresist; 41-second photoresist.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Through comparison between fig. 1 and fig. 2 and fig. 3 and fig. 4, the present invention adds three process steps of bipolar DNW doping, deep phosphorus doping and high temperature rapid annealing based on the conventional NPN transistor process, and completes a novel low on-resistance and high amplification NPN transistor.
As a specific embodiment of the present invention, with reference to fig. 5 to 18, a method for manufacturing a low on-resistance and high amplification NPN transistor specifically includes the following steps:
as shown in fig. 5, a P-type substrate 11 is provided, and a BNW region 1 is formed on the P-type substrate 11 by photolithography and N-type ion implantation according to the conventional process, so as to perform BNW region 1 well-pushing, in which the BNW region in the present invention is also referred to as a bipolar nwell region;
as shown in fig. 6, a DNW region 2 doping window is formed on the BNW region 1 by photolithography, and the first photoresist 21 is an implantation mask layer;
as shown in FIG. 7, by N-type ion implantation, the implantation element is P, the implantation energy is 2 to 4MeV, and the implantation dose is 1 to 2X 10 13 cm -2 A DNW region 2 with a certain thickness is formed at the bottom of the BNW region 1, and the DNW region in the invention is also called a deep N-well region;
as shown in fig. 8, the first photoresist 21 on the surface of the silicon wafer is removed;
as shown in fig. 9, according to the conventional process, a closed-loop field region isolation 3 is formed at the edge and inside of the upper end surface of the BNW region 1 by silicon nitride/silicon oxide deposition, silicon nitride/silicon oxide lithography and etching, oxidation, and silicon nitride/silicon oxide stripping, respectively;
as shown in fig. 10, at the edge of the BNW region 1, a deep phosphorus region 4 doping window is formed by photolithography, and the second photoresist 41 is an implantation mask layer;
as shown in fig. 11, a closed-loop deep phosphorus region 4 is formed on the BNW region 1 by N-type ion implantation, the deep phosphorus region 4 is communicated with the DNW region 2, and the deep phosphorus region 4 is located between two field regions 3; the method comprises the following five steps:
the first step, the implantation element is P, the implantation energy is 2-2.5 MeV, and the implantation dosage is 1-2 × 10 15 cm -2 (ii) a The second step, the implantation element is P, the implantation energy is 1.5MeV, and the implantation dosage isIs 1 to 2X 10 15 cm -2 (ii) a Thirdly, the implantation element is P, the implantation energy is 1MeV, and the implantation dosage is 1-2 multiplied by 10 15 cm -2 (ii) a The fourth step, the implantation element is P, the implantation energy is 500keV, and the implantation dosage is 1-2 × 10 15 cm -2 (ii) a The fifth step, the implantation element is P, the implantation energy is 100keV, and the implantation dosage is 1-2 × 10 15 cm -2 (ii) a Because the implantation is distributed according to Gauss, the deep phosphorus region 4 with continuous concentration is formed by step-by-step implantation;
as shown in fig. 12, the second photoresist 41 on the surface of the silicon wafer is removed;
as shown in fig. 13, according to the conventional process, a base region 5 is formed on a BNW region 1 by photolithography and P-type ion implantation, and the base region 5 is located inside a deep phosphorus region 4;
as shown in fig. 14, a closed-loop polycrystalline isolation 6 is formed on the upper end face of the base region 5 by polycrystalline deposition, polycrystalline lithography and etching;
as shown in fig. 15, side walls 7 are formed on both side walls of the poly-isolation 6 by side wall deposition and etching;
as shown in fig. 16, according to the conventional process, an emitter region 8 is formed on a base region 5 by photolithography and N-type ion implantation, a closed-loop collector region 9 is formed on a BNW region 1, the emitter region 8 is located in a polycrystalline isolation 6, the collector region 9 is located between two field region isolations 3, and the collector region 9 overlaps with a deep phosphorus region 4;
as shown in fig. 17, according to the conventional process, a closed-loop base contact region 10 is formed on the base region 5 by photolithography and P-type ion implantation, and the base contact region 10 is located outside the polycrystalline isolation 6;
as shown in fig. 18, the activation of the implantation doping is completed by high-temperature rapid annealing at 1000 to 1100 ℃ for 10 to 30 seconds.
Referring to fig. 3 and 4, a low on-resistance and high amplification NPN transistor of the present invention includes a P-type substrate 11, a BNW region 1 formed on the P-type substrate 11; a DNW region 2 with a certain thickness is formed at the bottom of the BNW region 1; a closed loop field region isolation 3 is respectively formed at the edge and the inner part of the upper end surface of the BNW region 1; a closed-loop deep phosphorus region 4 is formed on the BNW region 1, the deep phosphorus region 4 is communicated with the DNW region 2, and the deep phosphorus region 4 is positioned between the two field region isolations 3; a base region 5 is formed on the BNW region 1, and the base region 5 is positioned in the deep phosphorus region 4; a closed-loop polycrystalline isolation 6 is formed on the upper end face of the base region 5; forming side walls 7 on two side walls of the polycrystalline isolation 6; an emitter region 8 is formed on the base region 5, a closed-loop collector region 9 is formed on the BNW region 1, the emitter region 8 is positioned in the polycrystalline isolation 6, the emitter region 8 is positioned at the center of the base region 5, the collector region 9 is positioned between the two field region isolations 3, and the collector region 9 is overlapped with the deep phosphorus region 4; a closed-loop base contact region 10 is formed on the base region 5, and the base contact region 10 is located outside the polycrystalline isolation 6.
As shown in the following table, the NPN transistors of the conventional structure and the novel low on-resistance and high amplification NPN transistors proposed by the present invention were tested separately: the on resistance of the novel NPN transistor is 60% of that of the NPN transistor with the traditional structure, and the amplification factor of the novel NPN transistor is 5 times of that of the NPN transistor with the traditional structure.
Example 1:0.35 mu m silicon gate BiCMOS process
(1) Oxide growth on native silicon wafer
An oxide layer;
(2) In that
On the oxide layer, CVD deposition growth
Silicon nitride;
(3) Masking by photoresist, dry etching of field region
Silicon nitride;
(4) Oxidizing to form field isolation;
(5) Fully stripping silicon nitride;
(6) Carrying out doping photoetching and injection on the BNW area and carrying out a drive well on the BNW area;
(7) Performing PMOS well injection by photoetching the N well region, wherein the PMOS well injection comprises well injection, punch-through prevention injection and threshold injection;
(8) Performing NMOS well injection by photoetching the P well region, wherein the NMOS well injection comprises well injection, punch-through prevention injection and threshold injection;
(9) Increasing DNW region photoetching, completing DNW region doping by adopting ion implantation, wherein the implantation element is P, the implantation energy is 2.5MeV, and the implantation dose is 1 multiplied by 10 13 cm -2 ；
(10) Adding deep phosphorus region photoetching, completing deep phosphorus region doping by adopting high-energy ion implantation, wherein the implantation is multi-step implantation, the first step is that the implantation element is P, the implantation energy is 2MeV, and the implantation dosage is 1 multiplied by 10 15 cm -2 (ii) a The second step, the implantation element is P, the implantation energy is 1.5MeV, and the implantation dose is 1 × 10 15 cm -2 (ii) a The third step, the implantation element is P, the implantation energy is 1MeV, and the implantation dose is 1 × 10 15 cm -2 (ii) a The fourth step, the implantation element is P, the implantation energy is 500keV, and the implantation dose is 1 × 10 15 cm -2 (ii) a The fifth step, the implantation element is P, the implantation energy is 100keV, and the implantation dose is 2X 10 15 cm -2 (ii) a Injecting step by step to form a deep phosphorus region with continuous concentration;
(11) Base region doping photoetching and injection;
(12) Oxide growth
SiO 2 A gate oxide layer;
(13) CVD deposition formation
A polycrystalline silicon layer, N-type polycrystalline diffusion doping;
(14) CVD deposition formation
WSi x A layer;
(15) Photoetching and etching Polycide polycrystal;
(16) Photoetching and injecting the N-type lightly doped source and drain regions;
(17) Photoetching and injecting a P-type lightly doped source/drain region;
(18) CVD deposition formation
The side wall oxide layer of (1);
(19) Etching the side wall oxide layer;
(20) Photoetching and injecting the N-type source drain region, and simultaneously forming emitter region doping and collector region contact doping;
(21) Photoetching and injecting a P-type source drain region, and forming base region contact doping at the same time;
(22) The high temperature of 1050 ℃ and 15s are increased for rapid annealing to complete the activation of injection doping;
(23) Ti silicide deposition and formation.
(24) CVD deposition formation
A USG layer;
(25) CVD deposition formation
A BPSG layer;
(26) Medium backflow;
(27) Chemical mechanical polishing
A BPSG layer;
(28) CVD deposition formation
USG layer such that the equivalent ILD thickness over the active region is
(29) Photoetching and etching the ohmic hole;
(30) Formed by sputtering
Ti and
TiN；
(31) CVD deposition formation
A metal tungsten layer;
(32) Chemical mechanical polishing
A metal tungsten layer;
(33) Formed by sputtering
Ti and
TiN；
(34) Formed by sputtering
An AlSiCu metal layer;
(35) Metal photoetching and etching;
(36) CVD deposition formation
Si 3 N 4 A passivation layer;
(37) Carrying out passivation photoetching and etching;
(38) Alloying;
(39) And testing the chip.
Example 2:0.5 μm silicon gate CMOS BiCMOS process
(1) Oxide growth on native silicon wafer
An oxide layer;
(2) In that
On the oxide layer, CVD deposition growth
Silicon nitride;
(3) Masking by photoresist, dry etching of field region
Silicon nitride;
(4) Photoetching the N well region to perform PMOS well injection;
(5) Photoetching the P well region to perform NMOS well injection;
(6) Carrying out doping photoetching and injection on the BNW area and carrying out a drive well on the BNW area;
(7) Oxidizing to form field isolation and a drive well;
(8) Fully stripping silicon nitride;
(9) Increasing DNW region photoetching, completing DNW region doping by adopting ion implantation, wherein the implantation element is P, the implantation energy is 3MeV, and the implantation dose is 1 multiplied by 10 13 cm -2 ；
(10) Adding deep phosphorus region photoetching, completing deep phosphorus region doping by adopting high-energy ion implantation, wherein the implantation is multi-step implantation, the first step is that the implantation element is P, the implantation energy is 2.2MeV, and the implantation dosage is 1 multiplied by 10 15 cm -2 (ii) a The second step, the implantation element is P, the implantation energy is 1.5MeV, and the implantation dose is 1 × 10 15 cm -2 (ii) a The third step, the implantation element is P, the implantation energy is 1MeV, and the implantation dose is 1 × 10 15 cm -2 (ii) a The fourth step, the implantation element is P, the implantation energy is 500keV, and the implantation dose is 1 × 10 15 cm -2 (ii) a The fifth step, the implantation element is P, the implantation energy is 100keV, and the implantation dose is 2X 10 15 cm -2 (ii) a Injecting step by step to form a deep phosphorus region with continuous concentration;
(11) Base region doping photoetching and injection;
(12) Adjusting photoetching and injection by using a threshold value;
(13) Oxidative growth
SiO 2 A gate oxide layer;
(14) CVD deposition formation
A polycrystalline silicon layer, N-type polycrystalline diffusion doping;
(15) CVD deposition formation
WSi x A layer;
(16) Photoetching and etching Polycide polycrystal;
(17) Photoetching and injecting the N-type lightly doped source and drain regions;
(18) Photoetching and injecting a P-type lightly doped source/drain region;
(19) CVD deposition formation
The side wall oxide layer;
(20) Etching the side wall oxide layer;
(21) Photoetching and injecting an N-type source drain region, and forming emitter region doping and collector region doping at the same time;
(22) Photoetching and injecting a P-type source drain region, and forming base region contact doping at the same time;
(23) The high temperature of 1050 ℃ and the high temperature of 20s are increased for rapid annealing to complete the activation of the injection doping;
(24) A source drain push junction;
(25) CVD deposition formation
A USG layer;
(26) CVD deposition formation
A BPSG layer;
(27) Medium backflow;
(28) Chemical mechanical polishing
A BPSG layer;
(29) CVD deposition formation
USG layer such that the equivalent ILD thickness over the active region is
(30) Photoetching and etching the ohmic hole;
(31) Formed by sputtering
Ti and
TiN；
(32) CVD deposition formation
A metal tungsten layer;
(33) Chemical mechanical polishing
A metal tungsten layer;
(34) Sputter forming
Ti and
TiN；
(35) Sputter forming
An AlSiCu metal layer;
(36) Metal photoetching and etching;
(37) CVD deposition formation
Si 3 N 4 A passivation layer;
(38) Carrying out passivation photoetching and etching;
(39) An alloy;
(40) And testing the chip.
Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present invention, which are used for illustrating the technical solutions of the present invention and not for limiting the same, and the protection scope of the present invention is not limited thereto, although the present invention is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the embodiments of the present invention, and they should be construed as being included therein. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (8)
1. A preparation method of a low on-resistance and high amplification NPN transistor is characterized by comprising the following steps:
providing a P-type substrate (11), and forming a BNW region (1) on the P-type substrate (11) through N-type ion implantation and drive-in;
forming a DNW region (2) with a certain thickness at the bottom of the BNW region (1) through N-type ion implantation;
a closed-loop field region isolation (3) is respectively formed at the edge and the inner part of the upper end surface of the BNW region (1);
forming a closed-loop deep phosphorus region (4) on the BNW region (1) through N-type ions by multiple fractional implantation, wherein the deep phosphorus region (4) is communicated with the DNW region (2), and the deep phosphorus region (4) is positioned between the two field regions (3);
forming a base region (5) on the BNW region (1) through P-type ion implantation, wherein the base region (5) is positioned in the deep phosphorus region (4);
a closed-loop polycrystalline isolation (6) is formed on the upper end face of the base region (5);
forming side walls (7) on two side walls of the polycrystalline isolation (6);
forming an emitter region (8) on the base region (5) and a collector region (9) of a closed loop on the BNW region (1) by N-type ion implantation, wherein the emitter region (8) is positioned in the polycrystalline isolation (6), the collector region (9) is positioned between the two field region isolations (3), and the collector region (9) is overlapped with the deep phosphorus region (4);
forming a closed-loop base region contact region (10) on the base region (5) through P-type ion implantation, wherein the base region contact region (10) is positioned outside the polycrystalline isolation (6);
the activation of the injection doping is completed by high-temperature rapid annealing at the temperature of 1000-1100 ℃ for 10-30 s.
2. Method for manufacturing a low on-resistance, high amplification NPN transistor according to claim 1 characterized in that the DNW region (2) is formed at the bottom of the BNW region (1) by N-type ion implantation, in particular: the implantation element is P, the implantation energy is 2-4 MeV, and the implantation dosage is 1-2 × 10 13 cm -2 。
3. A method of manufacturing a low on-resistance, high amplification NPN transistor according to claim 1 characterized in that the field isolation (3) is formed by silicon nitride/silicon oxide deposition, silicon nitride/silicon oxide lithography and etching, oxidation and silicon nitride/silicon oxide lift-off.
4. The method for manufacturing a low on-resistance, high amplification NPN transistor according to claim 1 wherein the deep phosphorus region (4) is formed on the BNW region (1) by multiple step implantation of N-type ions, specifically five steps as follows:
the first step, the implantation element is P, the implantation energy is 2-2.5 MeV, and the implantation dosage is 1-2 × 10 15 cm -2 (ii) a The second step, the implantation element is P, the implantation energy is 1.5MeV, and the implantation dose is 1-2 × 10 15 cm -2 (ii) a Thirdly, the implantation element is P, the implantation energy is 1MeV, and the implantation dosage is 1-2 multiplied by 10 15 cm -2 (ii) a The fourth step, the implantation element is P, the implantation energy is 500keV, and the implantation dosage is 1-2 × 10 15 cm -2 (ii) a The fifth stepThe implantation element is P, the implantation energy is 100keV, and the implantation dosage is 1-2 x 10 15 cm -2 。
5. A method for manufacturing a low on-resistance, high amplification NPN transistor according to claim 1 characterized in that the poly crystalline isolation (6) is formed by poly crystalline deposition, poly crystalline lithography and etching.
6. The method for manufacturing a low on-resistance and high amplification NPN transistor according to claim 1, characterized in that the side walls (7) are formed by side wall deposition and etching.
7. A low on-resistance, high amplification NPN transistor, characterized in that it is manufactured by the method of any of claims 1 to 6;
the BNW type semiconductor device comprises a P type substrate (11), wherein a BNW region (1) is formed on the P type substrate (11); a DNW area (2) with a certain thickness is formed at the bottom of the BNW area (1); a closed-loop field region isolation (3) is respectively formed at the edge and inside of the upper end face of the BNW region (1); a closed-loop deep phosphorus region (4) is formed on the BNW region (1), the deep phosphorus region (4) is communicated with the DNW region (2), and the deep phosphorus region (4) is positioned between the two field isolation regions (3); a base region (5) is formed on the BNW region (1), and the base region (5) is positioned in the deep phosphorus region (4); a closed-loop polycrystalline isolation (6) is formed on the upper end face of the base region (5); forming side walls (7) on two side walls of the polycrystalline isolation (6); an emitter region (8) is formed on the base region (5), a closed-loop collector region (9) is formed on the BNW region (1), the emitter region (8) is positioned in the polycrystalline isolation (6), the collector region (9) is positioned between the two field region isolations (3), and the collector region (9) is overlapped with the deep phosphorus region (4); a closed-loop base contact area (10) is formed on the base area (5), and the base contact area (10) is located outside the polycrystalline isolation (6).
8. A low on-resistance, high amplification NPN transistor according to claim 7, characterized in that the emitter region (8) is located in the center of the base region (5).
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| JPH0258230A (en) * | 1988-08-23 | 1990-02-27 | Toshiba Corp | Manufacture of bipolar transistor |
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