CN1129355A - Method of manufacturing a thin film semiconductor device - Google Patents

Method of manufacturing a thin film semiconductor device Download PDF

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CN1129355A
CN1129355A CN95118605A CN95118605A CN1129355A CN 1129355 A CN1129355 A CN 1129355A CN 95118605 A CN95118605 A CN 95118605A CN 95118605 A CN95118605 A CN 95118605A CN 1129355 A CN1129355 A CN 1129355A
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silicon
etching
film
mask
described step
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CN1158695C (en
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须泽英臣
竹村保彦
山崎舜平
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02672—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1277—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using a crystallisation promoting species, e.g. local introduction of Ni catalyst
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure

Abstract

The patent relates to a thin-film transistor to reduce a leakage current between source/drain of a thin-film transistor. Etch the silicon by means of a liquid or a non-ionized gas, to form an island-shaped silicon semiconductor regionhaving a tapered edge.Alternatively, the island-shaped silicon semiconductor region having the tapered edge is formed by means of a dry etching process, a part damaged by plasma is removed through etching of the edge part by means of the above-mentioned liquid or gas.A leakage current between source/drain caused by a part can be reduced. Failures such as disconnection occurring when a gate electrode crosses the island-shaped silicon region can also be reduced.

Description

The manufacture method of thin-film semiconductor device
The present invention relates to be used in the structure of a kind of circuit element in the thin film integrated circuit, a for example thin-film transistor (TFT), and corresponding method of manufacture.The thin-film transistor that utilizes the present invention to make can be formed on the dielectric substrate that glass or its analog make, also can be formed on the insulator on the Semiconductor substrate that monocrystalline silicon or its analog make, and be used as the active matrix circuit of LCD, drive circuit of image sensor or the like.
In recent years, need under 750 ℃ or lower temperature, produce thin-film transistor.The manufacture process of thin-film transistor is such, promptly utilize silicon area (active layer) that etching forms an island afterwards, form a gate insulating film and a gate electrode thereon at the Si semiconductor film that is formed on the dielectric film made from silica, silicon nitride or analog.Yet, in habitual semiconductor integrated circuit technology, under this low temperature, can not obtain gate insulating film with thermal oxidation process.Therefore, up to the present, this dielectric film mainly is to form with chemical vapor deposition method (CVD method) or physical vapor deposition (PVD method).
Yet the step cladding thickness of the dielectric film that usefulness CVD method or PVD method form is less, and this can impair reliability, output and the characteristic of dielectric film.In other words, under the situation of the cross section of edge portion perpendicular, the cladding thickness of gate insulating film can be reduced to such degree significantly, and under typical situation, the thickness of its edge portion at most also has only half of planar portions thickness.
The island silicon area all obtains by silicon fiml is carried out dry etching as usual.In common dry etch technique, the selection ratio owing between the substrate that need improve silicon and silica or silicon nitride has adopted reaction ionic etching method.In this case, the cross section of island silicon area is vertical basically.
Therefore, the electric field of gate electrode is applied to the edge portion in thin film semiconductor zone by the concentrated area.In other words, because the thickness of the edge portion of gate insulating film is its planar portions thickness half, the electric field strength of edge portion can reach two times of planar portions.As a result, the withstand voltage of edge portion will descend, thereby causes dielectric breakdown and leakage current between grid and source, or causes dielectric breakdown and leakage current at grid and between leaking.In addition, because step is very steep, gate electrode often disconnects in the edge of island silicon area portion.
From above-mentioned angle, the someone advises that it is not vertical making the edge portion of island silicon area, but has the formation (taper) of angled section, therefore, even the step cladding thickness of dielectric film reduces to some extent, also can not go wrong.
Fig. 3 is the schematic diagram of a typical TFT, can see that from the top it has the tapered edges edge, and shows the cross section of the TFT that sees along A-A ' and B-B ' line respectively.The thin film silicon semiconductor regions that is formed on the TFT on the substrate is separated into extrinsic region (embodying the source region and the drain region of P type or N type conductivity) 24 and 25, and a raceway groove shaped region 21, and it is intrinsic basically.And be positioned under the gate electrode 23.Also be provided with a gate insulating film 22 in addition, cover the Si semiconductor zone with it.Although do not illustrate in the drawings, also have an interlevel insulator 59 that covers them, and form lead thereon.Lead is connected to extrinsic region 24 and 25 by the contact holes that is formed in the interlevel insulator.
As can be seen from Fig. 3, owing to adopted the Si semiconductor zone of tapered edges, can make the thickness of gate insulating film 22 of edge portion and planar portions identical, so just can improve the withstand voltage of edge portion along portion.Thereby can improve characteristic and the output thereof of TFT significantly.
Yet this measure does not fundamentally address the above problem.If taper is made by the edge portion in Si semiconductor zone, sure minimizing disconnects phenomenon.But still have many indeterminable problems.Wherein the most serious problem is exactly the leakage current between source and the leakage.Even apply predetermined drain voltage in the source of TFT and between leaking,, just can not form raceway groove if the current potential of gate electrode is identical with source potential.Correspondingly, there is not electric current to flow in the source and between leaking.In other words, logical cut-off current should be below 0.1pA.
But can find the leakage current (being called " cut-off current (off-current) " hereinafter) that 10pA is above actually.In addition, find that also leakage current almost is uniformly unexpectedly, and wide irrelevant with the raceway groove of TFT.This cut-off current is a fatal problem, and particularly when TFT was used as the switching transistor of active matrix circuit, this moment, desired cut-off current was set to below the 10pA, preferably below the 2pA.
To further the discovering of cut-off current cause, electric current 27 is to flow through along the edge portion of silicon area in the channel formation region territory 21 of intrinsic basically by the inventor.So just can prove that above-mentioned phenomenon is because the damage of edge portion causes, thereby utilizing the dry etch technique etch silicon film to form in the process of island silicon area, because too much plasma has caused this damage.
Confirm following true by various electricity and physical measurement.Be that the position 26 that sustains damage in the method etching process is formed on edge portion 28 places.An azygous key (dangling bonds) appears in this one 26.In addition, the degree of oxidation of silicon face is low, thereby has formed the inferior silicon oxide layer of characteristic.The silicon oxide film that dangling bonds and characteristic are inferior can not provide characteristic of semiconductor, and its conductivity approaches conductor.It is this because the taper edge that the damage that plasma causes not only occurs adopting dry etch technique to form under the situation of island silicon area, also can appear at all positions, edge.
Because impaired position 26 only appears in the regional area much at one that has nothing to do with channel width, value and channel width that cut-off current also has much at one are irrelevant.Therefore, in order further to reduce cut-off current, need to eliminate damaged part 26.Otherwise just need to adopt a kind of special engraving method, make the not damage of subject plasma fully of edge portion.
The present invention proposes at the problems referred to above, and its objective is provides a kind of method, be used to form to have the island silicon area of tapered edges along portion, and fully can be owing to plasma damage arrives the position, edge.
In order to address the above problem, to make in the method for thin-film semiconductor device according to first aspect present invention a kind of, the island silicon semiconductor device with tapered edges edge carries out etched non-plasma technology to silicon and forms by a kind of.
Above-mentioned structure is one of described herein basic structure key element of the present invention.Do not use plasma when forming the island silicon area, but come etch silicon film with wet etch technique, etchant comprises liquid and (for example has a NH 2Hydrazine (the NH of group 2NH 2) or ethylenediamine (NH 2(C 2H 4) NH 2), or the mixed solution of hydrofluoric acid and nitric acid), liquid has etched effect to silicon fiml, or adopts the gas etch technology, and this gas has etching action (for example various chlorofluoride) to silicon under the nonionic state.
Thin-film semiconductor device manufacture method according to second aspect present invention may further comprise the steps: (1) uses the plasma etching silicon film, forms an island Si semiconductor zone; (2) etch away the zone that has been subjected to plasma damage in the above-mentioned Si semiconductor zone with non-plasma technology.
Said structure is one of basic structure key element of the present invention.After the island silicon area that utilizes plasma etching to form to have the taper edge, just come etch silicon film, thereby remove that part that when plasma etching, is damaged by the wet etch technique of employing liquid or the gas etch technology of the gas of employing nonionic state.
In addition, the thin-film semiconductor device manufacture method according to third aspect present invention may further comprise the steps: (1) forms thickness on dielectric film be the silicon fiml of 100 to 1000 , forms a mask thereon again; (2) silicon fiml that adopts aforementioned mask is carried out etching, utilize liquid or island thin film silicon semiconductor regions of the gas of nonionic state formation of silicon being had etching action with tapered edges edge.
Have again,,, form the island silicon area, adopted to comprise a NH by silicon fiml is carried out wet etching in order to address the above problem according to the thin-film semiconductor device manufacture method of fifth aspect present invention 2Group (hydrazine (NH for example 2NH 2), ethylenediamine (NH 2(C 2H 4) NH 2) or analog) material.In other words, this method comprises: (1) forms thickness on dielectric film be the silicon fiml of 100 to 1000 , forms a mask thereon again; (2) silicon fiml that adopts aforementioned mask is carried out etching, utilize to comprise a NH 2The fluent material of group forms the island thin film silicon semiconductor regions with tapered edges edge.
Thin-film semiconductor device manufacture method according to seventh aspect present invention may further comprise the steps: (1) forms a silicon fiml that thickness is 100 to 1000 on dielectric film, form the mask that one deck mainly comprises silica or silicon nitride (silicon nitride that also comprises oxidation) thereon selectively, or form the mask that one deck consists predominantly of the machine material; (2) silicon fiml that adopts aforementioned mask is carried out etching, utilizing has the liquid of etching action or gas to form island thin film silicon semiconductor regions to silicon.
In the thin-film semiconductor device manufacture method aspect the present invention the 3rd, five, seven with said structure, be to form the island silicon area by the wet etch techniques etch silicon film of utilizing liquid, or the gas of employing nonionic state, form the island silicon area with the gas etch technology.
In above-mentioned steps (1), the thickness of silicon fiml has been made the restriction of 100 to 1000 , this be for the cross section that makes edge portion enough level and smooth.If the thickness of silicon fiml meets or exceeds 1000 , the shape in cross section, edge just near vertical, can't obtain this island silicon area of the present invention in this case.
The gas etch technology of the gas of wet etch technique and employing nonionic state can not cause plasma damage, and because these two kinds of technology all are known isotropic etching technology, if silicon fiml has possessed above-mentioned thickness, the shape in etching cross section is very level and smooth.Therefore, gate electrode can not be disconnected, and is enough to reduce cut-off current.So that further improve output, the thickness that is formed on the gate insulating film on the island silicon area preferably can be set at 2 to 10 times of silicon film thickness in order to improve the ladder area.
In said method, a kind of suitable etching solution (liquid that silicon is had etching action) as using in the wet etching has used acid solution herein, and for example the mixed solution of hydrofluoric acid and nitric acid (fluoro nitric acid) has a NH 2The for example hydrazine or the ethylenediamine (NH of group 2(C 2H 4) NH 2) solution, or have the alkaline solution of quaternary ammonium oxide solution.Specifically, has NH in use 2During the solution of group, if use and water (H that solution mixes by proper proportion 2O), then can be more effective, also use propyl alcohol, butanols, isopropyl alcohol (CH simultaneously together 3CHUOHCH 3), or catechol (C 6H 4(OH) 2).
In said method, if adopt the gas etch technology, preferably adopt the compound of fluorine and chlorine, the material that for example has strong fluorination is such as chlorine monofluoride (ClF), chlorine trifluoride (ClF 3), or chlorine pentafluoride (ClF 5).In other words, when silicon touches these gases, will be fluoridized.Its result makes silicon become the fluorinated silicon compound of gas, carries out etching then.Particularly chlorine trifluoride chemically is being stable, and is easy to deposit and use.In addition, because the chlorine trifluoride is difficult to etch away silica, can be with silica as mask.It should be noted, because chlorine trifluoride and silica all are difficult for and organic substance reacts, so the organic substance of photoetching agent one class can not be used as mask.
With chlorine trifluoride to the etching speed of polysilicon at room temperature and 3.5 torr (ClF 3/ N 2Under=300sccm/900sccm) the condition is about 650 /min.Under similarity condition, using plasma CVD manufacturing technology is respectively about 15 /min and 100 /min the etching speed of silica and silicon nitride.
Followingly said process (2) is described with reference to accompanying drawing 4A to 4D and 7A to 7D.
In the process shown in Fig. 4 C and the 7C is to form the process of island to zone 36.In this course, use mask 35, silicon fiml 32 is carried out etching, form island silicon area 36.Mask 35 forms as follows.On the whole surface of a layer 33 of the silicon nitride that mainly comprises silica, silicon nitride or oxidation (SiOxNy), coat photoresist, thereby form the mask 34 of photoresist by known photoetching technique.The layer 33 that utilizes 34 pairs of masks to be located under it carries out etching (process is seen Fig. 4 B and 7B).
Then, in the process shown in Fig. 4 B, separate the mask 34 of photoresist from mask 35.This is mainly to comprise silica because really play the having only of effect of mask in the process shown in Fig. 4 C, the mask 35 of the silicon nitride of silicon nitride or oxidation, and the mask 34 of organic photoetching agent is used to the treatment fluid of etching silicon or handles gas damage significantly, for example hydrazine or chlorine trifluoride.
Like this, finished after layer 33 the etching that mainly comprises silica or silicon nitride, the mask 34 of photoresist is just useless.Yet when photoresist was separated, the surface oxidation of silicon 32 can be very thin, and when the difference of the etching speed of silicon 32 and silica was very big, its etching action was very low.Therefore, in process shown in Fig. 7 C, in order to obtain enough etching actions, the mask 34 of photoresist still attached to the condition on the film 35 under etch silicon film 32.
Should be noted that, mainly comprise silica, the layer 33 of the silicon nitride of silicon nitride or oxidation utilizes chemical vapor deposition method (CVD method) preparation, for example using plasma CVD technology and low pressure chemical vapor deposition technology, or adopt physical vapor deposition (PVD method) prepared layer 33 such as sputtering technology.If allow to be heated to more than 500 ℃, also can adopt thermal oxidation technique.
Thin-film semiconductor device manufacture method according to fourth aspect present invention comprises following basic step: (1) forms has the island thin film silicon semiconductor regions of tapered edges along portion, forms mask thereon, utilizes the dry etch technique etch silicon film; (2) use the edge portion that silicon fiml is had the liquid (treatment fluid) or the gas of nonionic state (processing gas) the processing thin film silicon semiconductor regions of etching action; And (3) form the horizontal gate electrode in zone with thin film semiconductor.
Thin-film semiconductor device manufacture method according to sixth aspect present invention may further comprise the steps: (1) forms has the island thin film silicon semiconductor regions of tapered edges along portion, forms mask thereon, utilizes the dry etch technique etch silicon film; (2) utilization has a NH 2The edge portion of the material processed thin film silicon semiconductor regions of group; And (3) form the horizontal gate electrode in zone with thin film semiconductor.
Thin-film semiconductor device manufacture method according to eighth aspect present invention, may further comprise the steps: (1) forms has the island thin film silicon semiconductor regions of tapered edges along portion, the layer that forms the mask that is made of the layer that mainly comprises silica or silicon nitride thereon and consist predominantly of the machine material is used the dry etch technique etch silicon film; (2) adopt the liquid (hydrazine (NH for example that silicon fiml is had etching action 2NH 2), have a NH 2Ethylenediamine (the NH of group 2(C 2H 4) NH 2Or the mixed liquor of hydrofluoric acid and nitric acid (hereinafter being called " treatment fluid "), or adopt the edge portion that has the gas (for example various chlorine of fluoridizing hereinafter are called " processing gas ") of the nonionic state of etching action to handle the thin film silicon semiconductor regions to silicon; And (3) form the horizontal gate electrode in zone with thin film semiconductor.
In method with said structure according to the present invention the 4th, six and eight, after the employing dry etch technique had formed the island silicon area with tapered edges edge, silicon is had the liquid of etching action in use or the gas etch of nonionic state falls the position that sustains damage in the dry etching process.
Device making method according to the thin film semiconductor of the present invention the 4th, six, eight aspect, thickness to silicon fiml does not have particular restriction, and this dry etch technique is compared the tapered edges edge that can obtain high-quality with wet etching or gas etch that first aspect present invention is adopted.Obviously, between above-mentioned steps (2) and (3), can also increase a step that is used to form gate insulating film.
As a kind of silicon there is the liquid of etching action, can uses acid solution, the mixed liquor of hydrofluoric acid and nitric acid (hydrogen fluorine nitric acid) for example, hydrazine or ethylenediamine (NH 2(CH 2) 2NH 2), or have the alkaline solution of quaternary ammonium oxide solution.Specifically, the water (H that under latter event, mixes by proper proportion as if use and solution 2O) then can be more effective, also use propyl alcohol, butanols, isopropyl alcohol (CH simultaneously together 3CHOHCH 3) or catechol (C 6H 4(OH) 2).
As the nonionic attitude gas that silicon is had etching action, chlorine fluoride is best, chlorine monofluoride (CLF) for example, chlorine trifluoride (ClF 3) or chlorine pentafluoride (CHF 5).Particularly chlorine trifluoride has chemical stability and is convenient to preserve and use.In addition, because chlorine trifluoride is difficult to etching oxidation silicon, can make mask with silica.
Be noted that because these liquids and gases to the etching action of silicon, just need a kind of like this structure, promptly adopt coating (mask) to cover the island silicon area, only have the position, edge to expose to the open air with mask effect.Otherwise, be not only edge portion, whole island silicon area all can be subjected to etching.
Therefore, according to a fourth aspect of the present invention, if used hydrazine when etch silicon film, ethylenediamine or chlorine fluoride owing to can not make mask with organic substance, have just used silica, and the silicon nitride of silicon nitride or oxidation (SiOxNy) is as coating.This coating is by obtaining such as the such chemical vapor deposition method (CVD method) of plasma CVD technology and low pressure chemical vapor deposition technology or such as the such physical vapor deposition of sputtering technology (PVD method).If allow to use the temperature more than 500 ℃, also can adopt thermal oxidation technique.
In addition, in a sixth aspect of the present invention, because the mask with above-mentioned effect has been arranged, along with having a NH 2The material organic corrosion such to for example photoresist of group, when dismantling photoresist, the oxidation that silicon face is subjected to is very thin.Therefore, has above-mentioned NH 2The etching action of the material of group has been lowered.So will be with having NH 2Keep the mask of photoresist during the material etch silicon film of group thereon.
In a eighth aspect of the present invention, be subjected to the corrosion of above-mentioned treatment fluid or processing gas such as the such organic substance of photoresist as mask, and the oxidation that this surface is subjected to when dismantling photoresist on silicon face is very thin, has consequently reduced above-mentioned treatment fluid or has handled the etching action of gas.Correspondingly, mask is made of sandwich construction, comprising a layer that consists predominantly of the machine material, and in photoresist a main layer that comprises silica and silicon nitride, and have mainly contain material the layer condition under carry out etching.
Of the present invention the 4th, six and eight aspect in, if carrying out heat treatment under the condition more than 400 ℃ between above-mentioned steps (1) and (2), contained heavy metal one class material will condense upon that position that has been subjected to dry etching damage in the silicon fiml.Subsequently, because this cohesion portion is subjected to etching in follow-up step (2), just can improve the purity of silicon fiml.In heat treatment, in order to prevent to react with silicon fiml, processing procedure should be carried out in the environment of hydrogen or nitrogen.
More particularly, a kind of element (catalyst element) that impels recrystallized amorphous silicon in use is nickel (Ni) for example, cobalt (Co), iron (Fe), platinum (Pt) or palladium (Pd) make under the situation of silicon fiml crystallization, it should be noted that the adverse effect of remaining catalyst element to element characteristic.When using these catalyst elements, can reduce crystallization temperature, and can shorten crystallization time.Yet, need in silicon fiml, add density and be at least 1 * 10 17Atom/cm 3The catalyst element.
Reduce the density of this catalyst element in silicon fiml by above-mentioned heat treatment process, and make it condense upon edge portion.Remove this edge portion by etching then.Heat treated temperature is high more, and this effect is strong more.Yet, must consider the influence of temperature to other materials.When using glass material to do substrate, heat treated temperature preferably is set at it below deformation point.Typical best design temperature is 400 to 550 ℃.
Figure 1A to 1E shows the basic structure that occurs according to fourth aspect present invention in the process of step (2).At first, form the shallow layer 3 of silica or silicon nitride material on the surface that is formed on crystal on the insulating surfaces 1 or noncrystalline silicon film 2, coating 3 can be by the treatment fluid etching of using in the step (2).Form a mask 4 (Figure 1A) with photoresist by known photoresist process thereon then.
Then, coating 3 and the silicon fiml 2 that uses mask 4 carried out etching, adopt dry etch technique, the mask 6 by etching becomes mask 4 to have the tapered edges edge has so just formed island silicon area 5.Although the edge of island silicon area is taper, there is the position 7 (Figure 1B) that has been subjected to plasma damage in its surface.
Remove the mask 4 of photoresist then.But on island silicon area 5, still leave the mask 8 (Fig. 1 C) that newly forms by etching to coating 3.
Since treatment fluid or handle gas can not etching mask 8, state in the use in the etching process of treatment fluid or gas, etching is that the edge from silicon fiml laterally carries out, like this with regard to etching comprise the zone 9 at the position 7 that is subjected to plasma damage.The distance X of etching progress rate should be able to be removed the position 7 that is subjected to plasma damage fully.In order to produce in enormous quantities and to be convenient to control, distance X should be 100 to 10000 , preferably 300 to 3000 .Use alkaline solution for example hydrazine as treatment fluid, or with chlorine fluoride when handling gas, before handling with treatment fluid, preferably remove silicon nitride film, because the silicon oxide film that is present on the edge face has hindered etched carrying out (Fig. 1 D) with etchant (for example buffered hydrofluoric acid) with hydrofluoric acid one class.
Remove mask 8 then, and form gate insulating film 10 with PVD technology or CVD technology.In forming the process of gate insulating film 10, can be by making gate insulating film 10 be subjected to thermal oxidation with the temperature below 750 ℃, thereby on the surface of gate insulating film 10 thin heat oxide film of formation.
Should be noted that in the process of etching mask 8, insulating surfaces 1 also can be subjected to etching simultaneously, and be subjected to etched depth 1/2 to depend primarily on the material of mask 8, the thickness Y of mask 8 1And the material of insulating surfaces 1 (Fig. 1 E).
If treatment fluid that uses in step (2) or processing gas can not corrode the organic substance of photoresist one class, the sort of photoresist mask used when etching island silicon area still can serve as mask in step (1).Process in this case is shown in Fig. 1 F to 1H.It is identical with method among Fig. 1 to form the method for taper island silicon area 12 on insulating surfaces 11.The mask 13 that on the surface of island silicon area, keeps photoresist.On the surface on tapered edges edge, also exist and be subjected to the position 14 (Fig. 1 F) that plasma decreases.
Then, after the island silicon area being handled with treatment fluid or processing gas, because the existence of photoresist mask 13, etching is after this carried out along the position from tapered edges, and etches away the zone 15 (Fig. 1 G) that comprises the position 14 that is subjected to plasma damage.
Remove photoresist mask 13 then, thereby form gate insulating film 16 (Fig. 1 H).
Fig. 2 A to 2D shows according to the basic structure in the step (2) of the present invention the 6th and eight aspect.At first form a shallow layer 3 on the surface that is formed on crystal on the insulating surfaces 1 or noncrystalline silicon film 2, it mainly comprises silica or silicon nitride, and can or not handle gas etch by the treatment fluid that uses in the step (2).Carve the mask 4 (Fig. 2 A) that glue forms photoresist by known lithography process then.
Then the coating 3 and the silicon fiml 2 of mask 4 carry out etching to making with photoresist, utilize dry etch technique that mask 4 is etched into the photoresist mask 6 with tapered edges edge, thereby form island silicon area 5.Although the edge of island areas 5 is tapers, still there is the position (Fig. 2 B) that has been subjected to plasma damage in its surface.
Handle exposing to the open air with treatment fluid or processing gas then at the position of its side.In this example, etching is laterally carried out from the edge of silicon fiml, thereby etches away the zone 9 that comprises the position 7 that is subjected to plasma damage.Etched progress distance X should be able to be removed the position 7 that is subjected to plasma damage fully, and in order to produce in enormous quantities and to be convenient to control, distance X should be 100 to 10000 , preferably 3000 .With having a NH 2The treatment fluid of group should be removed silicon oxide film with the etchant with hydrofluoric acid one class (for example buffered hydrofluoric acid), because the silicon oxide film that is present on the edge face has hindered etched carrying out before handling.Although any variation of photoresist mask 6 is not shown in the drawings,, can melt or oxidize away mask 6 (Fig. 2 C) fully if select the treatment fluid of suitable kind or handle gas.
Under the situation that still leaves photoresist, just it is dismantled, and before forming gate insulating film 10, further remove the main silicon oxide-containing that below photoresist, forms or the film 8 of silicon nitride by PVD technology or CVD technology.In forming the process of gate insulating film 10, can be by under the temperature below 750 ℃, making gate insulating film 10 heated oxides in advance, thus on the face of the exhausted film 10 of grid, form a thin heat oxide film.
Be noted that at the mask 8 to main silicon oxide-containing and silicon nitride and carry out the etched while, insulating surfaces 1 also can be subjected to etching, and its degree of depth Y 2Depend primarily on the material of mask 8, thickness Y 1, and the material of insulating surfaces 1 (Fig. 2 D).
In order to reduce degree of depth Y 2, must do the above-mentioned film 3 of main silicon oxide-containing and silicon nitride enough thinly.In this case, because photoresist directly contacts to each other with silicon fiml, silicon fiml may be polluted.
The accompanying drawing part and the literal of book has as an illustration illustrated embodiments of the invention together, can be used for explaining purpose of the present invention, advantage and principle.In the drawings,
Figure 1A to 1H shows the schematic diagram according to the TFT manufacturing process of first embodiment of the invention;
Fig. 2 A to 2D shows the schematic diagram according to the TFT manufacturing process of another embodiment of the present invention;
Fig. 3 is a schematic diagram that is used to illustrate the habitual existing problem of TFT;
Fig. 4 A to 4D is the sectional view according to the TFT manufacturing process of the present invention first to the 5th embodiment;
Fig. 5 A to 5E is the sectional view according to the TFT manufacturing process of sixth embodiment of the invention;
Fig. 6 A to Fig. 6 E is the sectional view according to the TFT manufacturing process of seventh embodiment of the invention;
Fig. 7 A to 7D is the sectional view according to the TFT manufacturing process of the present invention the 8th to the 11 embodiment;
Fig. 8 A to 8E is the sectional view according to the TFT manufacturing process of twelveth embodiment of the invention; And
Fig. 9 A to 9E is the sectional view according to the TFT manufacturing process of thriteenth embodiment of the invention.
Below embodiments of the present invention will be described in detail with reference to the accompanying drawings.(example 1)
First embodiment relates to a kind of method that forms the island silicon area with wet etch technique.Fig. 4 A to 4D represents present embodiment.At first on the glass substrate (not shown), form the bed course film made from silica 31 that thickness is 2000 with sputtering technology.Depositing a thickness thereon with the plasma CVD technology then is 100 to 1000 , for example the amorphous state silicon fiml 32 of 500 .By under 350 to 55 ℃, silicon fiml 32 being annealed 0.5 to 8 hour contained excessive hydrogen in the discharging membrane 32.
After this, irradiation KrF excitation laser beam (wavelength 248nm, pulsewidth 20nsec) makes its crystallization on silicon fiml 32, and the suitable energy density of laser beam is 250 to 400mJ/cm 2
After crystallization treatment, deposit one deck is as the silicon oxide film 33 of diaphragm on silicon fiml 32 with sputtering technology, and thickness is 200 .On whole of silicon oxide film 33, coat photoresist then, and with known photoetching technique composition, thereby the mask 34 (Fig. 4 A) that constitutes by photoresist formed.
The then diaphragm 33 made by silica of mask 34 usefulness the 1/10BHF etchings of making by photoresist, the mask 35 that formation is made by silica.1/10BHF is that the content ratio of a kind of etching acid and ammonium fluoride is 1: 10 a solution.
Peel off photoresist mask 34 from diaphragm 35 then, the mask 35 that silica is made exposes out (Fig. 4 B) to the open air.
After this use the aqueous solution etch silicon film of hydrazine.The ratio of hydrazine and water (mole ratio) is decided to be 36: 74.Existence can be not etched by the zone of the mask 35 that silica is made, and other zones are then by etching gradually.The result has just formed the island silicon area 36 (Fig. 4 C) that has near the edge of taper.
Follow the mask made from 1/10BHF etching oxidation silicon 35.In this example, the silicon oxide film 402 of bed course and mask 407 also form with sputtering technology.Because the etching speed of 1/10BHF (23 ℃) is 900 to 1000 /min, even consider the problem of over etching, when etching, the etched degree of depth of thermosphere oxide-film is 250 to 350 , and is identical with the degree of mask 407.
Forming a layer thickness thereon with the plasma CVD technology then is 1000 to 1500 , for example the silicon oxide film 37 of 1200A.TEOS (tetrem oxosilane, Si (OC 2H 5) 4) and oxygen (O 2) being used as unstrpped gas, the formation temperature of film is decided to be 250 to 400 ℃, for example 350 ℃.The silicon oxide film 37 of Xing Chenging has just constituted gate insulating film (Fig. 4 D) thus.(example 2)
Second embodiment relates to the method that forms the island silicon area with wet etch technique.Fig. 4 A to 4D represents present embodiment.At first on the glass substrate (not shown), form the silica thermosphere film 31 that thickness is 2000 with sputtering technology.Then with the plasma CVD technology thereon deposition thickness be 100 to 1000 , the amorphous state silicon fiml 32 of 500 for example.Utilize 350 to 550 ℃ to silicon fiml 32 annealing 0.5 to 8 hour, contained excess hydrogen in the discharging membrane 32.
After this activate laser (wavelength 248mm, pulsewidth 20nsec) irradiation silicon fiml with KrF and make its crystallization.The suitable energy density of laser beam is 250 to 400mJ/cm 2
Different therewith, the crystallization treatment in the present embodiment also can adopt 550 to 950 ℃ temperature that silicon fiml 32 is carried out thermal annealing.Make silicon fiml 32 crystallizations by thermal annealing after, also available above-mentioned laser beam irradiation silicon fiml 32.
After crystallization treatment, be that the silicon oxide film 33 of 200 is as diaphragm with sputtering technology deposit one layer thickness on silicon fiml 32.On whole of silicon oxide film 33, coat photoresist again, and with known photoetching technique composition, thereby the mask 34 (Fig. 4 A) that photoresist is made formed.
The then diaphragm 33 made of mask 34 usefulness the 1/10BHF etching oxidation silicon of making by photoresist, thereby the mask 35 that the formation silica is made.1/10BHF is that the content ratio of a kind of etching acid and ammonium fluoride is 1: 10 a solution.
After this peel mask 34 off from diaphragm 35, the mask 35 that silica is made comes out.Use hydrofluoric acid then, the mixed liquor etch silicon film of nitric acid and aldehydic acid.The ratio of having used hydrofluoric acid, nitric acid and acetic acid in this example is 1: 5: the solution of 10-20.In etching process, exist the zone of silicon oxide masking film 35 can be not etched, and other zone be etched gradually.Though etching speed depends on temperature, still can in 10 seconds to 1 minute, etch away the silicon fiml of 500 .The result has just formed the island silicon area (Fig. 4 C) with approximate tapered edges edge.
Follow the mask made from 1/10BHF etching oxidation silicon 35.In this example, bed course silicon oxide film 402 and mask 407 also form with sputtering technology.Even consider the problem of over etching, because the etching speed of 1/10BHF (23 ℃) is 900 to 1000 /min, in etching process, it is 250 to 350 that the thermosphere oxide-film is subjected to etched depth, identical with the etching degree of mask 407.
Forming thickness thereon with the plasma CVD technology then is 1000 to 1500 , for example the silicon oxide film 37 of 1200 .TEOS (tetrem oxosilane), Si (OC 2H 5) 4)) and oxygen be used as unstrpped gas, the formation temperature of film is decided to be 250 to 400 ℃, for example 350 ℃.The silicon oxide film 37 of Xing Chenging has just constituted a gate insulating film (Fig. 4 D) thus.(example 3)
The 3rd embodiment relates to the method that forms the island silicon area with wet etch technique, and Fig. 4 A to 4D represents present embodiment.At first with the sputtering technology pad film 31 that one 2000 thick silica of of deposit is made on the glass substrate (not shown).And one 500 thick amorphous state silicon fiml 32 of .In the oxygen environment, silicon fiml 32 is carried out 1 hour thermal annealing then, thereby on the silicon fiml face, form one deck silica diaphragm 33 as thin as a wafer with 550 ℃.Coating concentration with the rotation paint-on technique on diaphragm 33 again is 1 to 100ppm nickel acetate aqueous solution.
After this, under 550 ℃,, make its crystallization to silicon fiml 32 annealing 5 to 8 hours.After crystallization treatment, form photoresist mask 34 (Fig. 4 A) with known photoetching technique.
Then, make the mask made from photoresist 34, the diaphragm of making by silica with the 1/10BHF etching 33, thus form silicon oxide masking film 35 (Fig. 4 B).
Then peel off mask 34 from diaphragm 35, the mask 35 that silica is made comes out.Use hydrofluoric acid then, the mixed liquor etch silicon film of nitric acid and acetic acid.In this example, hydrofluoric acid in the solution of use, the ratio of nitric acid and acetic acid is 1: 5: 10-20.The result has just formed the island silicon area 36 (Fig. 4 C) at the edge with approximate taper.
And then the mask made from 1/10BHF etching oxidation silicon 35.In this example, bed course silicon oxide film 402 and mask 407 also form with sputtering technology.Even consider the etched factor of transition, because the etching speed of 1/10BHF (23 ℃) is 900 to 1000 /min, the etch depth of bed course oxide-film is 250 to 350 , and the etching degree of mask 407 too.
Then form the thick silicon oxide film of 1200 37 in the above with the plasma CVD technology.Single silane (SiH 4) and nitrous oxide (N 2O) be used as unstrpped gas, the formation temperature of film is decided to be 350 to 500 ℃, for example 430 ℃.So the silicon oxide film 37 that forms is used as gate insulating film (Fig. 4 D).(example 4)
The 4th embodiment relates to the gas that uses the nonionic state forms the island silicon area by the gas etch technology method.Fig. 4 A to 4D has represented present embodiment.Be the silicon oxide pad film 31 of 2000 at first, and thickness is the amorphous state silicon fiml 32 of 1000 with gas etch technology deposition thickness on the glass substrate (not shown).
Under 600 to 750 ℃ temperature, silicon fiml 32 is carried out thermal annealing then, make its crystallization.After crystallization treatment, the thick silicon oxide film 33 of deposit one deck 200 is as protective layer.Form the mask (Fig. 4 A) that photoresist is made with known photoetching technique then.
The diaphragm 33 that the mask 34 usefulness 1/10BHF etching oxidation silicon that then adopt photoresist to make are made, thereby the mask 35 (Fig. 4 B) of formation silica.
Peel the mask 34 of photoresist subsequently off from diaphragm 35, the mask 35 that silica is made comes out.Then substrate is placed the inside of a silicon dioxide tube of 1 to 100 holder of reducing pressure, intraductal atmospheric pressure for example is 3.5 holders, and chlorine trifluoride (ClF 3) and the mist of nitrogen import silicon dioxide tube.In this example, the flow velocity of chlorine trifluoride is decided to be 300sccm, and the flow velocity of nitrogen is decided to be 900sccm.After substrate is placed under this state through 2 to 5 minutes, the stop supplies chlorine trifluoride.The result has just formed the island silicon area 36 (Fig. 4 C) with approximate tapered edges edge.
The mask made from 1/10BHF etching oxidation silicon 35 subsequently.In this example, bed course silicon oxide film 402 and mask 407 also form with sputtering technology.Even consider the etched problem of transition, because the etching speed of 1/10BHF (23 ℃) is 900 to 1000 /min, when etching, it is 250 to 350 that the bed course oxide-film is subjected to etched depth, and the etching degree of mask 407 too.
Then forming thickness in the above with the plasma CVD technology is 1000 to 1500 , for example the silicon oxide film 37 of 1200 .With single silane (SiH 4) and oxygen (O 2) make unstrpped gas.And the formation temperature of film is decided to be 350 to 500 ℃, for example 400 ℃.The silicon oxide film 37 of Xing Chenging is used as gate insulating film (Fig. 4 D) thus.(the 5th embodiment)
The 5th embodiment relates to a kind of method that forms the island silicon area by the gas etch technology of using nonionic state gas.Fig. 4 A to 4D represents this embodiment.At first, by gas etch technology deposit is made by silica on the glass substrate (not shown) pad film 31 and silicon fiml 32, the former thickness is 2000 , and latter's thickness is 500 .And be in noncrystalline state.Then, by means of the thermal annealing that in oxygen atmosphere, under 550 ℃, silicon fiml 32 is carried out a hour, on the surface of silicon fiml, form silane diaphragm 33 as thin as a wafer.Coating concentration by the rotation paint-on technique on diaphragm 33 then is 1 to the nickel acetate aqueous solution of 100ppm.
After this, silicon fiml 32 was annealed under 550 ℃ 5 to 8 hours, thereby by crystalization.After the crystal processing, form photoresist mask 34 (Fig. 4 A) by known photoetching technique.
Then, use the mask of being made by photoresist 34, the diaphragm of silica being made with 1/10BHF 33 carries out etching, thereby forms the mask 35 (Fig. 4 B) of silica.
After this, Etching mask 34 is from diaphragm 35 decortications, thereby the mask 35 that silica is made is exposed.Then, substrate is placed in and is depressurized to 1 to 100 holder, the inside of silicon dioxide tubes of 5 holders for example, and make chlorine trifluoride (ClF 3) and the mist of nitrogen flow to silicon dioxide tube.In the present embodiment, the flow of chlorine trifluoride is set as 100sccm, and the flow of nitrogen is set as 900sccm.Making after substrate is retained in this state 2 to 5 minutes, stop the supply of chlorine trifluoride.As a result, form island silicon area 36 (Fig. 4 C) with approximate tapered edge.
Then, the mask 35 usefulness 1/10BHF that made by silica carry out etching.Then, form silicon oxide film 37 thereon by the plasma CVD technology, its thickness is 1000 to 1500A, for example 1200 .Use single silane (SiH 4) and nitrous oxide (N 2O), and the film formation temperature is set at 350 to 500 ℃, for example 430 ℃ as unstrpped gas.The silicon oxide film 37 of Xing Chenging is as gate insulating film (Fig. 4 D) like this.(the 6th embodiment)
Fig. 5 A to 5E is the sectional view that the TFT process is made in expression, forms the island silicon area according to the present invention therein, and is used as the switching transistor of the active matrix circuit that uses the island silicon area.At first, on glass substrate 401, form the silica bed course 402 that thickness is 2000 by sputtering technology.By plasma CVD technology deposit silicon fiml 403 on bed course 402, its thickness is 300 to 1500 again, 1000 for example, and be noncrystalline state.Then, be that the silicon oxide film 404 of 200 is as diaphragm by the sputtering technology deposition thickness.
Then, in the atmosphere that reduces, made silicon fiml 403 crystalization in 48 hours by annealing down at 600 ℃.Can by means of use high light for example the system of laser beam carry out the crystal processing.After this, on the whole surface of silicon oxide film 404, coat photoresist, and be shaped, form photoresist mask 405 (Fig. 5 A) by known photoetching technique.
Then, use the mask of being made by photoresist 405, the diaphragm of silica being made with 1/10BHF 404 carries out etching.The 1/10BHF that is used is a kind of solution (contains ratio be 1: 10 hydrogen fluoride and ammonium fluoride).
Then, silicon fiml 403 is etched, thereby forms the island silicon area 406 with tapered edge.Use dry etching to carry out etching.At this moment etching condition is as follows:
RF power 500W
Pressure 100m holder
Gas flow
CF 4： 50sccm
O 2： 45sccm
As a result, shown in 5B, obtained island silicon area 406.But, its marginal portion is taper, as shown in the figure.The angle of tapering part is 20 to 60 °.When etching, work as gas flow ratio CF 4/ O 2(going up in the example is 40/45) then can not obtain to have the edge of aforementioned tapering part when increasing.Should illustrate that the end face of photoresist is etched into taper.The surface at tapered processed edge has been destroyed widely by plasma.
Then, in order to remove the oxide-film as thin as a wafer that has been formed on the surface of the tapering part of plasma collapse, oxide-film is carried out 5 to 30 seconds of etching by 1/10BHF.At this moment, because there is photoresist mask 405, the silicon oxide layer 407 that extends on island silicon area 406 can etched (Fig. 5 (B)).
After this, photoresist mask 405 makes the silicon oxide layer that has been retained on the island silicon area 406 be exposed from silicon oxide layer 407 decortications.
Then, use the hydrate (N of hydrazine 2H 4H 2O) etch silicon film.At this moment, because there is the diaphragm 407 of silica on the island silicon area, etching is only carried out from its edge.In the present embodiment, etching is carried out (Fig. 5 C) till the X=1000 .
After this, the diaphragm of making by silica with the 1/10BHF etching 407.In the present embodiment, form bed course silicon oxide film 402 and diaphragm 407 by sputtering technology equally.Because the etch-rate (23 ℃) by 1/1BHF is 900 to 1000 /min, even considered etching, the etch depth of bed course oxide-film also has only 250 to 350 when etching, and is identical with the etch depth of diaphragm 407.
Then, forming thickness thereon by the plasma CVD technology is 1000 to 1500 , for example the silicon oxide film 408 of 1200 .With single silane (SiH 4) and nitrous oxide (N 2O), and the film formation temperature is made as 380 to 500 ℃, for example 430 ℃ as unstrpped gas.The silicon oxide film 408 of Xing Chenging is used as gate insulating film like this.
In addition, form the polysilicon film of increase conductivity by the low pressure chemical vapor deposition technology by means of supporting by the arm phosphorus, and carry out etching, thereby form grid 409.Then, use grid 409, in the island silicon area, introduce n type impurity (phosphorus) in the self-adjusting mode, so as to forming n type impurity range 410 by the ion technology of mixing up as mask.Then, 500 to 550 ℃ of annealing down, so as to activating n type impurity (Fig. 5 D).
Then, be the intermediate insulating layer (silica) 412 of 4000 by plasma CVD deposition techniques thickness, and selectively form the nesa coating that thickness is 500 thereon, so as to forming pixel capacitors 413.
Like this, on intermediate insulating layer 412, form contact hole, and be the titanium film of 500 and the aluminium film that thickness is 4000 , and etched, thereby form source electrode 414 and the drain electrode 415 of TFT by the sputtering technology deposition thickness.In this way, can make active matrix circuit (Fig. 5 E).(the 7th embodiment)
Fig. 6 A to 6E represents to make the sectional view of the process of TFT, wherein forms island areas according to the seventh embodiment of the present invention.The same with first embodiment, deposition thickness is that bed course silicon oxide film 502 and the thickness of 2000 are 300 to 1000 on glass substrate 501, the silicon fiml 503 of 500 for example, and be noncrystalline state.Then, their by in oxygen atmosphere at 500 to 600 ℃, for example heat-treated 1 hour under 550 ℃, thereby form silica diaphragm 504 as thin as a wafer on its surface.The thickness of supposing silicon oxide film is 100 or littler, but thicker shown in the figure for simplicity.
Then, silicon fiml is optionally mixed up phosphorus, so as to forming n type impurity range 505.Intrinsic region between n type extrinsic region 505 506 forms the channel formation region territory of TFT then.
After this, be that 1 to 100ppm nickel acetate aqueous solution forms nickel acetate film as thin as a wafer thereon by the rotation paint-on technique by means of on substrate surface, applying concentration.Then, under 500 to 580 ℃, carried out thermal annealing 2 to 12 hours, for example annealed 4 hours down, make nickel be diffused in the amorphous silicon film, so as to making the silicon fiml crystalization at 550 ℃.In the crystal process, the n type impurity (phosphorus) that has been doped in advance can be activated simultaneously.
After carrying out above-mentioned processing, form photoresist mask 507 (Fig. 6 A) by known photoetching technique.
Then, make mask 507 with photoresist, with 1/10BHF etching oxidation silicon fiml 504.In addition, as first embodiment, silicon fiml 503 is carried out etching, thereby form island silicon area 508 with tapered edge by dry etching.In the 3rd embodiment, (Fig. 6 B) destroyed on the surface that has been processed to the edge of taper widely by plasma.
After this, the mask 507 of photoresist is peeled from silicon oxide film 504 in nitrogen, thereby exposes the silicon oxide film 509 that is retained on the island silicon area 508.Thermal annealing for example carries out under 450 ℃ under 400 to 500 ℃.In this course, suppose that the nickel that contains is condensed in silicon fiml in the part of being destroyed by the dry etching processing of before having carried out.
Then, substrate is placed in the inside of silicon dioxide tube, and makes chlorine trifluoride (ClF under the pressure of room temperature and 6 holders 3) and the mist of nitrogen flow to silicon dioxide tube.In the present embodiment, the flow of every kind of gas is made as 50sccm.Because on the island silicon area, there is silica diaphragm 509, so etching is only carried out from its edge.Supposition in the present embodiment is because chlorine trifluoride was provided for 1 to 2 second, so the etching X=1000 (Fig. 6 C) that carries out.
After this, with 1/10BHF silica diaphragm 509 is carried out etching.In this embodiment, because silicon oxide film 509 is extremely thin, be approximately 100 , thereby bed course silicon oxide layer 502 is etched hardly.
Then, by the plasma CVD technology, forming thickness thereon is for example silicon oxide films 510 of 1200 of 1000 to 1500 .With single silane (SiH 4) and oxygen (O 2) as unstrpped gas, and underlayer temperature is set at 350 to 530 ℃ for example 430 ℃.The silicon oxide film 510 of Xing Chenging is used as gate insulating film like this.
Then, by sputtering technology thereon deposition thickness be 3000 to 6000 , the aluminium film of 5000 and carry out etching for example, thus form grid 511.When containing a spot of silicon or scandium (Sc) in the aluminium film, thermal resistance can be enhanced.In addition, grid is broken to be formed like this, and feasible and drain electrode leaves one apart from Z, thereby grid and source electrode are overlapped, as shown in the figure.Doing like this is in order to reduce leakage current (Fig. 6 D).
Then, forming thickness by the plasma CVD technology is the silicon nitride film of 4000 , as first layer insulation 511.Then, in first layer insulation 511, form contact hole.At this moment, not only form contact hole 512 at source electrode, and in drain electrode.Then, be the aluminium film of 4500 by the sputtering technology deposition thickness, and etched to form source electrode 513.At this moment, there is not electrode to form in drain side.
In addition, forming thickness by the plasma CVD technology is that the silicon oxide film of 2000 is as second layer insulation 514.Then, the inside of the contact hole 512 that formerly forms forms contact hole.Then, be the nesa coating of 500 and etched by the sputtering technology deposition thickness, thereby form pixel capacitors 515.Utilize aforementioned processing, can form the switching transistor and additional pixel capacitors (Fig. 6 E) thereon of active matrix circuit.(the 8th embodiment)
The 8th embodiment relates to a kind of method that forms the island silicon area by wet lithography.Fig. 7 represents this embodiment.At first, forming thickness by sputtering technology (not shown) on glass substrate is the silicon oxide pad film 31 of 2000 .In addition, the thickness that is noncrystalline state by the plasma CVD deposition techniques is for example silicon fimls 32 of 500 of 100 to 1000 .By means of being annealed down at 350 to 550 ℃, silicon fiml made it discharge contained excess hydrogen in film in 0.5 to 8 hour.
Then, make silicon fiml 32 crystalization by means of irradiation KrF excimer laser beam (wavelength is 248nm, and pulsewidth is 20nsec).The suitable energy density of laser beam is 250 to 400mJ/cm 2
In addition, can be applied under 550 to 950 ℃ the temperature present embodiment silicon fiml 32 is carried out the method for thermal annealing as the crystal processing method.In addition, after silicon fiml 32 being carried out the crystal processing by thermal annealing, can be to the aforesaid laser beam of silicon fiml 32 irradiations.
After the crystal processing, be that the silicon oxide film 33 of 200 is as diaphragm by sputtering technology deposition thickness on silicon fiml 32.Then, on the whole surface of silicon oxide film 33, coat photoresist and also be shaped, so as to forming the mask 34 (Fig. 7 A) that photoresist is made by known photoetching technique.
Then, use the mask of making by photoresist 34, the diaphragm of making by silica with the 1/10BHF etching 33, thereby the mask 35 that formation is made by silica.Used 1/10BHF is that a kind of ratio that contains is 1: 10 the hydrogen fluoride and the solution of ammonium fluoride.
After this, with the aqueous solution etch silicon film of hydrazine, simultaneously attached thereto the mask 34 of photoresist.Hydrazine is set at 36: 74 to the ratio (mol ratio) of water.The zone that the mask of being made by photoresist 34 exists is not etched, and other zone is by etching gradually.As a result, formed island silicon area 36 (Fig. 7 C) with approximate tapered edge.
Then, the mask 34 of photoresist is from mask 35 decortication, and the mask made from 1/10BHF etching oxidation silicon 35.In aforementioned etching process, the mask 34 of photoresist is peeled according to the kind of used Treatment Solution or is dissolved fully.In the present embodiment, bed course silicon oxide film 402 and mask 407 form by sputtering technology equally.Figure is that the etch-rate (23 ℃) of 1/10BHF is 900 to 1000 /min, thus when etching, the etch depth of bed course oxidation, also the etch depth with mask 407 was identical even considered etching, was 250 to 350 .
Then, forming thickness thereon by the plasma CVD technology is for example silicon oxide films 37 of 1200 of 1000 to 1500 .TEOS (tetrem oxosilane, Si (OC 2H 5) 4) and oxygen (O 2) being used as unstrpped gas, the film formation temperature is made as 250 to 400 ℃, for example 350 ℃.The silicon oxide film 37 of Xing Chenging is used as gate insulating film (Fig. 7 D) like this.(the 9th embodiment)
The 9th embodiment relates to the method that forms the island silicon area by wet etch technique.Fig. 7 represents this embodiment.At first, on glass substrate (not shown) to form the thickness be noncrystalline state be the silicon fiml 32 of 500 and the silicon oxide pad film 31 that thickness is 2000 .Then, by means of in oxygen to silicon fiml 32 550 ℃ of following thermal annealings 1 hour, on the silicon fiml surface, form silica diaphragm 33 as thin as a wafer.Then, being coated with on diaphragm 33 with concentration by the rotation paint-on technique is 1 to 100ppm nickel acetate aqueous solution.
Nickel (Ni) is a kind of element (catalyst element) that is used for promoting the crystalization of amorphous silicon, is 1 * 10 by means of silicon fiml is added density 17Atom/cm 3Or more catalyst element, can reduce the crystal temperature, the result shortens the crystal time.Other catalyst element can be cobalt (Co), iron (Fe), platinum (Pt), palladium (Pd) and analog thereof.In the present embodiment, silicon fiml 32 is annealed 0.5 to 8 hour down so that crystalization at 550 ℃.After the crystal processing, form photoresist mask 34 (Fig. 7 A) by known photoetching technique.
Then, make mask 34 with photoresist, with the diaphragm 33 of 1/10BHF etching oxidation silicon, thus the mask 35 (Fig. 7 B) of formation silica.
After this, with the aqueous solution etch silicon film of hydrazine, adhere to the mask 34 of photoresist simultaneously thereon.Hydrazine is set at 36: 74 to the ratio (mol ratio) of water.Existence is not etched by the zone of the mask 34 that photoresist is made, and other zone is by etching gradually.As a result, formed island silicon area 36 with approximate tapered edge.Because this etching action, photoresist mask 34 is peeled off and is dissolved (Fig. 7 C).
Then, photoresist mask 34 is from diaphragm 35 decortication, and the mask of being made by silica with the 1/10BHF etching 35.In aforementioned etch processes, photoetching Guang mask 34 is peeled according to the kind of used Treatment Solution or is dissolved.In the present embodiment, form bed course silicon oxide film 402 and mask 407 by identical sputtering technology.Because the etch-rate of BHF (23 ℃) is 900 to 1000 /min, when etching, even considered etching, the etch depth of bed course oxide-film and mask 407 also identical is 250 to 350 ,
Then, form the silicon oxide film 37 that thickness is 1200 thereon by the plasma CVD technology.With single silane and nitrous oxide (N 2O), and the film formation temperature is made as 350 to 500 ℃, for example 430 ℃ as unstrpped gas.The silicon oxide film 37 of Xing Chenging is as gate insulating film (Fig. 7 D) like this.(the tenth embodiment)
The tenth embodiment relates to the method that a kind of gas etch technology of passing through the gas of use nonionic state forms the island silicon area.Fig. 7 represents this embodiment.At first, deposition thickness is that the silicon oxide pad film 31 of 2000 and the thickness that is noncrystalline state are the silicon fiml 32 of 1000 on the glass substrate (not shown).
After this, in nitrogen, under 600 to 750 ℃ temperature, make silicon fiml 32 thermal annealings, so that make its crystalization.After the crystal processing, deposit one thickness is that the silicon oxide film 33 of 200 is as protective layer.Then, form the mask (Fig. 7 A) that photoresist is made by known photoetching technique.
Then, make the mask made from photoresist 34, the diaphragm of making by silica with the 1/10BHF etching 33, thus form silicon oxide masking film 35 (Fig. 7 B).
After this, substrate place pressure be reduced to 1 to 100 holder for example 3.5 holder temperature be in the silicon dioxide tube of room temperature, and make chlorine trifluoride (ClF 3) and the mist of nitrogen flow to silicon dioxide tube.In the present embodiment, the flow set of chlorine trifluoride is 300sccm, and the flow set of nitrogen is 900sccm.Substrate was kept 2 to 5 minutes in this state, stop the supply of chlorine trifluoride.As a result, formed island silicon area 36 (Fig. 7 C) with approximate tapered edge.
Then, photoresist mask 34 is peeled off.Should illustrate, according to the kind of the processing gas that in aforementioned gas etch, uses, under the effect of handling gas, the 34 oxidized or disappearances of photoresist mask.The mask made from 1/10BHF etching oxidation silicon 35.In this embodiment, form bed course silicon oxide film 402 and mask 407 by identical sputtering technology.Because the etch-rate of 1/10BHF (23 ℃) is 900 to 1000 /min,, be 250 to 350 so even considered etching, when etching, the etch depth of the bed course oxidation film also etch depth with mask 407 is identical.
Then, forming thickness thereon by the plasma CVD technology is for example silicon oxide films 37 of 1200 of 1000 to 1500 .With single silane (SiH 4) and oxygen as unstrpped gas, and the film formation temperature is set at 350 to 500 ℃, for example 400 ℃.The silicon oxide film 37 of Xing Chenging is as gate insulating film (Fig. 7 D) like this.(the 11 embodiment)
The 11 embodiment relates to the method that the gas etch technology that is the gas of nonionic state by use forms the island silicon area.Fig. 7 represents this embodiment.At first, deposition thickness is that the bed course silicon oxide film 31 of 2000 and the thickness that is noncrystalline state are the silicon fiml 32 of 500 on the glass substrate (not shown).Then, in oxygen, carried out thermal annealing 1 hour at the silica diaphragm as thin as a wafer 33 that forms on to the silicon fiml surface under 550 ℃.Then, coating concentration by the rotation paint-on technique on diaphragm 33 is 1 to 100ppm nickel acetate aqueous solution.
Then, under 550 ℃, make silicon fiml 32 annealing 0.5 to 8 hour, so that make its crystalization.After the crystal processing, form Etching mask 34 (figure (7A) by known photoetching technique.
Then, make mask 34 with photoresist,, thereby form silicon oxide masking film 35 (Fig. 7 B) with 1/10BHF etching oxidation silicon diaphragm 33.
After this, it is for example inside that is in the silicon dioxide tube under the room temperature of 5 holders of 1 to 100 holder that substrate is placed step-down, and photoresist mask 34 is attached thereon simultaneously, and makes chlorine trifluoride (ClF 3) and the mist of nitrogen flow to silicon dioxide tube.In this embodiment, the flow set of chlorine trifluoride is 100sccm, and the flow set of nitrogen is 900sccm.Make in this state after substrate kept 2 to 5 minutes, stop the supply of chlorine trifluoride.As a result, form island silicon area 36 (Fig. 7 C) with approximate tapered edge.
Then, photoresist mask 34 is peeled off, and the mask of being made by silica with the 1/10BHF etching 35.The kind of the processing gas that photoresist mask 34 bases are used in the above-mentioned gas etching, the oxidized or disappearance by means of the effect of handling gas should be described.Then, form the silicon oxide film 37 that thickness is 1000 to 1500 thereon by the plasma CVD technology.With single alkane (SiH 4) and nitrous oxide as unstrpped gas, and the film formation temperature is set at 350 to 500 ℃ for example 430 ℃.The silicon oxide film of making like this 37 is used as gate insulating film (Fig. 7 D).(the 12 embodiment)
Fig. 8 A to 8E is the sectional view that the process of TFT is made in expression, and it has the island areas that forms according to the present invention and is used as the switching transistor of the active matrix circuit that uses this island areas.At first, on glass substrate 401, form the silica bed course 402 that thickness is 2000 by sputtering technology.Then by the plasma CVD technology on pad film 402 in the deposit thickness be 300 to 1500 , for example 1000 's and be in the silicon fiml 403 of noncrystalline state.Then, be that the silicon oxide film 404 of 200 is as diaphragm by the sputtering technology deposition thickness.
Then, under the air pressure that lowers, silicon fiml 403 is made its crystalization by annealing at 600 ℃.Can use adopt high light for example the system of laser beam carry out the crystal process.After this, on the whole surface of silicon oxide film 404, coat photoresist, and be shaped by known photoetching technique, thus the mask 405 (Fig. 8 A) of formation photoresist.
Then, make the mask made from photoresist 405, the diaphragm made from 1/10BHF etching oxidation silicon 404.Used 1/10BHF is that containing proportional is 1: 10 the hydrogen fluoride and the solution of ammonium fluoride.
Then, silicon fiml 403 is etched, thereby forms the island silicon area 406 with tapered edge.Use dry ecthing method to carry out etching.This etching condition is as follows:
RF power: 500W
Pressure: 100m holder
Gas flow:
CF 4： 50sccm
O 2： 45sccm
As a result, shown in Fig. 8 B, obtained island silicon area 406.But, its marginal portion is taper as shown in the figure.Cone angle is 20 ℃ to 60 °.As throughput ratio CF during etching 4/ O 2When (being 50/45) increases, can not obtain to have the edge of aforementioned tapering part in last example.Should illustrate that the end face of photoresist is etched into taper.The edge surface that has been processed to tapering part has been destroyed widely by plasma.
Then, in order to remove the oxide-film as thin as a wafer that forms on by the surface of the tapering part of plasma collapse, with 1/10BHF to 5 to 30 seconds of oxide-film etching.At this moment, because there is photoresist mask 405, the silicon oxide film 407 that exists on island silicon area 406 does not have etched (Fig. 8 (B)).
Then, use the hydrate (N of hydrazine 2H 4H 2O) etch silicon film, the while is adhered to the mask 405 of photoresist thereon.At this moment, because there is the diaphragm 47 of silica on the island silicon area, etching is only carried out from its edge.In the present embodiment, etching degree X=1000 (Fig. 8 C).
Then, after photoresist mask 405 is peeled off, the diaphragm of making by silica with the 1/10BHF etching 407.In this embodiment, form bed course silicon oxide film 402 and keep film 407 by identical sputtering technology.Because the etch-rate of 1/10BHF (23 ℃) is 900 to 1000 /min, thus even considered etching, when etching the etch depth of bed course oxide-film also with keep the identical of film 407, be 250 to 350 .
Then, by the plasma CVD technology, forming thickness thereon is for example silicon oxide films 408 of 1200 of 1000 to 1500 .With single silane (SiH 4) and nitrous oxide be unstrpped gas, and the film formation temperature is set at 380 to 500 ℃ for example 430 ℃.The silicon oxide film 408 of Xing Chenging is as gate insulating film like this.
In addition,, form and increase the polysilicon film of conductivity owing to mixing up phosphorus by means of the low pressure chemical vapor deposition technology, and etched, so that form grid 409.Then, use grid,, in the island silicon area, introduce n type impurity (phosphorus), thereby form n type extrinsic region 410 in the self-adjusting mode by the technology of mixing up as mask.After this, under 500 to 550 ℃, anneal, thus laser n type impurity (Fig. 8 D).
Then, by plasma CVD deposition techniques thickness be the intermediate insulating layer (silica) of 4000 ; And optionally forming nesa coating thereon, its thickness is 500 , thereby forms pixel capacitors 413.
Like this, in interlayer insulating film 412, formed contact hole, and be the titanium film of 500 and the aluminium film that thickness is 4000 , carried out etching then, made the source electrode of TFT and drain electrode go up and form electrode 414 and 415 by the sputtering technology deposition thickness.In this way, the active matrix circuit that can make (Fig. 8 E).(the 13 embodiment)
Fig. 9 is the sectional view that the process of TFT is made in expression, has wherein formed the silicon area of island according to this embodiment of the present invention.As first embodiment, on glass substrate 501 deposition thickness be the bed course silicon oxide film 502 of 2000 and thickness be 300 to 1000 for example 500 's and be the silicon fiml 503 of noncrystalline state.They are stood 500 to 600 ℃ of for example heat treatments of 550 ℃ of one hour in oxygen then, thereby form silica diaphragm 504 as thin as a wafer in its surface.The thickness of silicon oxide film is 100 or still less according to estimates, but draws thicklyer for simplicity in the drawings.
Then, silicon fiml is optionally mixed up phosphorus, thereby forms n type impurity range 505.Then, the zone 506 of the intrinsic basically between n type impurity range 505 is made the channel formation region territory of TFT.
Then, being coated with concentration on lining plating surface by the rotation paint-on technique is 1 to 100ppm nickel aldehydic acid saline solution, makes to form as thin as a wafer nickel acetate film thereon.Then, under 500 to 580 ℃, carry out thermal annealing 2 to 12 hours for example 550 ℃ following 4 hours, make nickel diffuse in the amorphous silicon, thereby make the silicon fiml crystalization.
Known that nickel (Ni) has catalysis, can promote the crystalization of amorphous silicon in the process that it is diffused into amorphous silicon film.Know that also platinum, palladium, iron and cobalt also have identical effect.The result compares with first embodiment, and present embodiment can be realized the crystalization of amorphous silicon in lower temperature and short time.And, in the crystal process, mix up n type impurity in advance and can be activated simultaneously.
Through after the above-mentioned processing, form photoresist mask 507 (Fig. 9 A) by means of the photoresist shaping by known photoetching technique.
Then, make mask 507 with photoresist, with 1/10BHF etching oxidation film.In addition, as second embodiment,, thereby form island silicon area 508 with tapered edge by dry etching technology etch silicon film 503.The edge surface that has been processed to taper has been destroyed (Fig. 9 B) widely by plasma.
Then, mask 507 attached to silicon fiml in, use the catechol aqueous solution etch silicon film of ethylenediamine.In this etching process, because on the island silicon area, there is the diaphragm 509 of silica, so etching is only carried out from its edge.In the present embodiment, etching degree X=1000 (Fig. 9 C).
After this, the mask 507 of photoresist is peeled off, and with the diaphragm 509 of 1/10BHF etching oxidation silicon.In the present embodiment, because silicon oxide film 509 is extremely thin, about 100 are so that bed course silicon oxide film 502 does not almost have is etched.
Then, forming thickness thereon by the CVD technology of using ecr plasma is for example silicon oxide films 510 of 1200 of 1000 to 1500 .With single silane (SiH 4) and oxygen (O 2) as unstrpped gas, thereby substrate needn't be through the heating of having a mind to.The silicon oxide film of Xing Chenging is as gate insulating film like this.
Then, by sputtering technology thereon deposition thickness be for example aluminium films of 500 and etched of 3000 to 6000 , thereby form grid 511.When in the aluminium film, containing a spot of silicon or scandium (Sc), can improve thermal resistance.In addition, grid is formed like this, makes the separately distance of Z of itself and drain electrode, thereby grid and source are overlapped, as shown in the figure.Do like this is in order to reduce leakage current (Fig. 9 D).
Then, forming thickness by the plasma CVD technology is the silicon oxide film of 4000 , as first interlayer insulating film 511.In first interlayer insulating film 511, form contact hole then.At this moment, contact hole 512 not only forms in the source but also forms in leakage.Then, by sputtering technology, deposition thickness is that the aluminium film of 4500 is also etched so that form source electrode 513.At this moment, there is not electrode leaking side formation.
In addition, forming thickness by the plasma CVD technology is the silicon oxide film of 2000 , as second layer insulation 514.Then, the contact hole 512 inner contact holes that form that formerly form.Then, be the nesa coating of 500 by the sputtering technology deposition thickness, and etched formation pixel capacitors 515.By aforementioned processing, can make the switching transistor and the pixel capacitors (Fig. 9 E) that is attached on the transistor of active matrix circuit.
As mentioned above, the present invention can improve the output of thin-film semiconductor device, increases its reliability, farthest shows its characteristic.According to thin-film semiconductor device of the present invention preferably as the pixel oxide-semiconductor control transistors in the active matrix circuit of liquid crystal display because the source and leak between leakage current little.
The present invention is that example is illustrated with n type channel TFT, obviously, under the situation of P type channel TFT, or under the situation of the complementary circuit that mixes ground deposit n type channel TFT and P type channel TFT on the same substrate, can similarly realize the present invention, in addition, the present invention not only can be applicable to the simple structure in the previous embodiment, and for example can be applied to examine disclose among the Japanese patent application Hei 6-124962 have silicide structural and TFT in source and leakage.Above-mentioned explanation of the present invention is primarily aimed at TFT.Yet obviously the present invention also can be applicable to other circuit devcie, for example has the thin film integrated circuit of several grids in an island semiconductor zone, multi-layer gate polar form TFT, diode, resistance and electric capacity.Thereby the present invention can be widely used in industrial circle.
The above-mentioned explanation of most preferred embodiment of the present invention is for explaining and illustration purpose.Be not for invention being limited to the disclosed form of determining, can make various changes or by obtaining various remodeling in the embodiments of the invention according to above-mentioned instruction.The selection of embodiment and explanation are in order to explain principle of the present invention and application thereof, make those skilled in the art can be according to specifically being used for embodiment and utilize the present invention.Scope of the present invention is limited by appended claim and equivalent thereof.

Claims (50)

1. method of making thin-film semiconductor device comprises:
Form island Si semiconductor zone by the non-plasma treatment that silicon is had etching action with tapered edge.
2. the method for claim 1 wherein contains the wet etching of solution of hydrazine to employing as non-plasma treatment.
3. method as claimed in claim 1, wherein the wet etching of the solution that adopts hydrofluoric acid containing as non-plasma treatment.
4. method as claimed in claim 1 wherein contains the wet etching of solution of ethylenediamine to employing as non-plasma treatment.
5. method as claimed in claim 1 wherein is the gas etch of chemical compound gas of the fluorine of nonionic state and chlorine to employing as non-plasma treatment.
6. a method of making thin-film semiconductor device comprises the following steps:
(a) by using the plasma etching silicon film to form the Si semiconductor zone of island; And
(b) by non-plasma treatment by means of etching remove in described Si semiconductor zone by the zone of described plasma collapse.
7. method as claimed in claim 6 wherein contains the wet etching of solution of hydrazine to employing as non-plasma treatment.
8. method as claimed in claim 7, wherein the wet etching of the solution that adopts hydrofluoric acid containing as non-plasma treatment.
9. method as claimed in claim 6 wherein contains the wet etching of solution of ethylenediamine to employing as non-plasma treatment.
10. method as claimed in claim 6 wherein is the gas etch of chemical compound gas of the fluorine of nonionic state and chlorine to employing as non-plasma treatment.
11. a method of making thin-film semiconductor device comprises the following steps:
(a) form mask being formed on the silicon fiml that thickness on the insulating coating is 100 to 1000 ; And
(b) use described mask, with what be the nonionic state silicon is had the liquid or the described silicon fiml of gas etch of etching action, thereby form island thin film silicon semiconductor regions with tapered edge.
12. as the method for claim 11, wherein the described mask in described step (a) mainly contains silica or silicon nitride.
13. as the method for claim 11, wherein the liquid with etch silicon film effect in described step (b) is the solution that contains hydrazine.
14. as the method for claim 11, wherein the liquid with etch silicon film effect in described step (b) is the mixed solution of hydrofluoric acid and nitric acid.
15. as the method for claim 11, wherein the insulating coating that is formed with silicon fiml thereon in described step (a) mainly contains silica or silicon nitride.
16. as the method for claim 11, wherein the gas with etch silicon film effect that is the nonionic state in described step (b) is the compound of fluorine and chlorine.
17. a method of making thin-film semiconductor device comprises the following steps:
(a) be etched in the silicon fiml that forms on the insulating coating by dry etch technique, thereby form island thin film silicon semiconductor regions with tapered edge.Be formed with mask thereon;
(b) with the marginal portion that is the liquid nonionic state and that have the etch silicon film effect or the described thin film semiconductor of gas treatment zone; And
(c) grid in formation one transversal described thin film semiconductor zone.
18. as the method for claim 17, wherein the described mask in described step (a) mainly contains silica or nitrogen silicon.
19. as the method for claim 17, wherein the liquid with etch silicon film effect in described step (b) is the solution that contains hydrazine.
20. as the method for claim 17, wherein the liquid with etch silicon film work in described step (b) is the mixed solution of hydrofluoric acid and nitronic acid.
21. as the method for claim 17, wherein the insulating coating that is formed with silicon fiml thereon in described step (a) mainly contains silica or silicon nitride.
22. as the method for claim 17, wherein in described step (b) to be the gas nonionic state and that have the etch silicon film effect be the compound of fluorine and chlorine.
23. as the method for claim 17, wherein the silicon fiml of the acquisition in described step (a) contains 1 * 10 17Atom/cm 3Or more promote the catalyst element of amorphous silicon crystalization.
24., between described step (a) and step (b), also be included in 400 to 550 ℃ of following thermal anneal step as the method for claim 17.
25. a method of making thin-film semiconductor device comprises the following steps:
(a) on the silicon fiml that to be formed on the thickness on the insulating coating be 100 to 1000 , form mask; And
(b) with containing NH 2The liquid of class uses described mask etch silicon film, forms the island thin film silicon semiconductor regions with tapered edge.
26. as the method for claim 25, wherein the described mask in described step (a) is photoresist basically.
27., wherein in described step (b), have a NH as the method for claim 25 2The liquid of class is the solution that contains hydrazine.
28., wherein in described step (b), contain NH as the method for claim 25 2The liquid of class is ethylenediamine.
29. as the method for claim 25, the insulating coating that wherein is formed on below the silicon fiml mainly contains silica or silicon nitride.
30. a method of making thin-film semiconductor device comprises the following steps:
(a) be formed on silicon fiml on the insulating coating by the dry etch technique etching, thereby form island film Si semiconductor zone, be formed with mask thereon with tapered edge;
(b) by containing NH 2The marginal portion of the described thin film silicon semiconductor regions of the liquid handling of class; And
(c) grid in the transversal described thin film semiconductor of formation zone.
31. as the method for claim 30, wherein the described mask in described step (a) is photoresist basically.
32., wherein in described step (b), contain NH as the method for claim 30 2The liquid of class is the solution that contains hydrazine.
33., wherein in described step (b), contain NH as the method for claim 30 2The liquid of class is ethylenediamine.
34. as the method for claim 30, wherein the insulating coating that forms under silicon fiml mainly contains silica or silicon nitride.
35. a method of making thin-film semiconductor device comprises the following steps:
(a) be on the silicon fiml of 100 to 1000 at the thickness that is formed on the insulating coating, optionally form by the layer of main silicon oxide-containing or silicon nitride respectively and mainly contain the mask that organic layer constitutes; And
(b) use described mask by being in liquid or gas etch silicon fiml the nonionic state under and that have the etching silicon effect, thereby formation have the thin film silicon semiconductor regions of the island of tapered edge.
36. as the method for claim 35, wherein described in step (a) mainly to contain organic layer be photoresist basically.
37. as the method for claim 35, wherein the liquid of the effect with the described silicon of etching in described step (b) is to contain NH 2The solution of class.
38. as the method for claim 35, wherein the liquid of the effect with the described silicon of etching in described step (b) is the mixed solution of hydrofluoric acid and nitronic acid.
39. as the method for claim 35, the liquid that wherein has the described silicon effect of etching in described step (b) is to contain hydrazine solution.
40. as the method for claim 35, wherein the liquid with the described silicon effect of etching in described step (b) is the solution that contains ethylenediamine.
41. as the method for claim 35, the gas that wherein has the described silicon effect of etching in described step (b) contains chlorofluoride.
42. as the method for claim 35, wherein the insulating coating that forms below described silicon fiml mainly contains silica or silicon nitride.
43. a method of making thin-film semiconductor device comprises the following steps:
(a) be formed on silicon fiml on the insulating coating by the dry etch technique etching, thereby form island thin film silicon semiconductor regions, form respectively thereon by layer mask that constitutes that mainly contains silica or silicon nitride with by mainly containing the mask that organic layer constitutes with tapered edge;
(b) usefulness is in the marginal portion of the liquid with etch silicon film effect or the described thin film silicon semiconductor regions of gas treatment of nonionic state; And
(c) grid in the transversal described thin film semiconductor of formation zone.
44. as the method for claim 43, wherein the organic layer of mainly containing in described step (a) is photoresist basically.
45. as the method for claim 43, wherein the liquid with the described silicon effect of etching in described step (b) is to contain NH 2The solution of class.
46. as the method for claim 43, the liquid that wherein has the described silicon effect of etching in described step (b) is the mixed solution of hydrofluoric acid and nitronic acid.
47. as the method for claim 43, wherein the liquid with the described silicon effect of etching in described step (b) is the solution that contains hydrazine.
48. as the method for claim 43, wherein the liquid with the described silicon effect of etching in described step (b) is the solution that contains ethylenediamine.
49. as the method for claim 43, the gas that wherein has the described silicon effect of etching in described step (b) contains chlorofluoride.
50. as the method for claim 43, wherein the insulating coating that forms below described silicon fiml mainly contains silica.
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CN100416771C (en) * 2002-11-15 2008-09-03 Nec液晶技术株式会社 Combined wet etching method for stacked films and wet etching system used for same
CN100437353C (en) * 2004-12-29 2008-11-26 南京大学 Preparation method of nano mould in nano-seal technology
CN1947248B (en) * 2004-03-10 2010-07-21 S.O.I.Tec绝缘体上硅技术公司 Treatment of service layer of a multi-layer structure and its device

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JP2841381B2 (en) * 1988-09-19 1998-12-24 セイコーエプソン株式会社 Method for manufacturing thin film transistor
US5132745A (en) * 1990-10-05 1992-07-21 General Electric Company Thin film transistor having an improved gate structure and gate coverage by the gate dielectric
US5174857A (en) * 1990-10-29 1992-12-29 Gold Star Co., Ltd. Slope etching process
US5393682A (en) * 1993-12-13 1995-02-28 Taiwan Semiconductor Manufacturing Company Method of making tapered poly profile for TFT device manufacturing

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CN100339995C (en) * 1998-11-17 2007-09-26 株式会社半导体能源研究所 Method of fabricating a semiconductor device
CN100416771C (en) * 2002-11-15 2008-09-03 Nec液晶技术株式会社 Combined wet etching method for stacked films and wet etching system used for same
CN1947248B (en) * 2004-03-10 2010-07-21 S.O.I.Tec绝缘体上硅技术公司 Treatment of service layer of a multi-layer structure and its device
CN100437353C (en) * 2004-12-29 2008-11-26 南京大学 Preparation method of nano mould in nano-seal technology

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