CN112911176A - Advanced digital-analog-domain TDI circuit for inhibiting parasitic effect and implementation method - Google Patents
Advanced digital-analog-domain TDI circuit for inhibiting parasitic effect and implementation method Download PDFInfo
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- CN112911176A CN112911176A CN202110069520.8A CN202110069520A CN112911176A CN 112911176 A CN112911176 A CN 112911176A CN 202110069520 A CN202110069520 A CN 202110069520A CN 112911176 A CN112911176 A CN 112911176A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/768—Addressed sensors, e.g. MOS or CMOS sensors for time delay and integration [TDI]
Abstract
The invention discloses a high-level digital-analog domain TDI circuit for inhibiting parasitic effect, which comprises a fully differential operational amplifier, wherein the fully differential operational amplifier is connected with a sampling capacitor, reversing switches L1 are arranged between the fully differential operational amplifier and the sampling capacitor, and two reversing switches L1 are connected through two reversing switches L2; the sampling capacitor is connected with VREF and the pixel unit, and the fully differential operational amplifier is also connected with a plurality of capacitor CH upper and lower pole plate switching circuits which are connected in parallel. The invention also discloses a realization method of the high-grade digital-analog domain TDI circuit. The output voltage of the pixel unit is alternately charged to the upper and lower polar plates by introducing the switches L1 and L2, and meanwhile, in order to ensure that the charge in the CH cannot be offset by the input after the polarity is switched, the CH upper and lower polar plate switch is added, the output of the operational amplifier is switched between high voltage and low voltage through the control of the switches, and the optimization effect on the charge error of an input/output bus coupled into the CH through parasitic capacitance is very obvious.
Description
Technical Field
The invention belongs to the technical field of analog domain CMOS-TDI circuits, and particularly relates to an advanced digital-analog domain TDI circuit for inhibiting parasitic effect and an implementation method of the advanced digital-analog domain TDI circuit for inhibiting the parasitic effect.
Background
Much attention has been paid to CMOS image sensors because of their advantages, such as low power consumption and ease of integration into systems on chip. With the wide development of image sensors, in partial low-light shooting, new requirements are made on the precision and the signal-to-noise ratio of images, and the stage number of a traditional analog domain TDI circuit is limited by parasitic influence caused by high-level numbers. Based on the addition of decoupling capacitors to eliminate parasitic effect, the capacitance network between the original storage capacitor CH and the parasitic capacitor is reformed to reduce the parasitic capacitance formed by the capacitance network, and the capacitance network comprises a fully differential operational amplifier, a storage capacitor network, sampling capacitors and parasitic bus parasitic capacitances Cpt and Cpb, a decoupling capacitor Cb, and a single-stage total parasitic capacitance Cp of the parasitic capacitor and the storage capacitor CH.
In an accumulation period of the TDI circuit, a charge sampling phase and a charge holding phase are arranged, the charge sampling phase is that CLK is conducted, the operational amplifier is in a unit gain state, VIN is pixel unit reset voltage Vrst, CS samples the voltage, switches at two ends of CH are turned off, and Cp is reduced by several orders of magnitude due to the addition of decoupling capacitance, so that the influence of voltage change of an input/output bus on CH at the moment can be ignored. When entering a charge holding phase, CLK is turned off, the voltage of VIN is a reading voltage Vsig of a pixel unit, the switches at two ends of CH are turned on at the moment, charge transfer is carried out, the output voltage rises to Vo1, the beginning of the next accumulation period is known after the phase is ended, the voltage at two ends of an input/output bus is Vo1, when entering a charge sampling phase of the next period, the voltage of the output/input bus is reduced to 0 from Vo1, the core of the influence of the voltage change of the bus on CH is reduced when the voltage changes, and because a decoupling capacitor Cd exists, Cp is reduced, and the influence of the voltage change of the bus on CH is reduced.
It can be seen from the above solutions that the parasitic influence is well suppressed by adding a decoupling capacitor, but each stage of integrator needs a decoupling capacitor Cd, and the size of the capacitor is in the order of 100fF, and the size of the single-stage storage capacitor CH is also in the order of magnitude, when the TDI stage is higher, the sacrificial layout area is too large, so that the circuit structure can be further optimized by using the mechanism of the parasitic influence without introducing additional capacitors and devices.
Disclosure of Invention
The invention aims to provide a high-grade digital-analog domain TDI circuit for inhibiting parasitic effect, which solves the problem that the area of the circuit is increased by adding decoupling capacitance in the prior art.
Another object of the present invention is to provide a method for implementing the above advanced digital-analog domain TDI circuit with parasitic effect suppression.
The technical scheme adopted by the invention is that the advanced digital-analog domain TDI circuit for inhibiting the parasitic effect comprises a fully differential operational amplifier (OPA), positive and negative electrode VIN interfaces of the fully differential operational amplifier (OPA) are respectively connected with a sampling Capacitor (CS), reversing switches L1 are arranged between the fully differential operational amplifier (OPA) and the sampling Capacitor (CS), and the two reversing switches L1 are connected through two reversing switches L2; one of the sampling capacitors CS is connected with a reference voltage VREF, the other sampling capacitor CS is connected with a pixel unit, and an anode VIN interface and a cathode VIN interface of the full-differential operational amplifier OPA are respectively connected with a plurality of capacitor CH upper and lower pole plate switching circuits which are connected in parallel.
The present invention is also characterized in that,
the upper and lower polar plate switching circuit of each capacitor CH comprises a capacitor CH connected with a fully differential operational amplifier (OPA), one end of the capacitor CH is respectively connected with a switch I11 and a switch K1, the other end of the capacitor CH is respectively connected with a switch I1 and a switch K11, the switch I11 and the switch K11 are respectively connected with a negative electrode VIN interface or a positive electrode VIN interface of the fully differential operational amplifier (OPA), and the switch K1 and the switch I1 are respectively connected with a positive electrode VOUT interface or a negative electrode VOUT interface of the fully differential operational amplifier (OPA).
The second technical scheme adopted by the invention is that the implementation method of the high-grade digital-analog domain TDI circuit for inhibiting the parasitic effect specifically comprises the following steps:
step 3, taking two accumulation periods as a large accumulation period, accumulating enough corresponding stages and outputting;
and 4, refreshing the output holding capacitor CH in the next large accumulation period and repeating the accumulation process.
The present invention is also characterized in that,
in the step 1, the method specifically comprises the following steps: in the conducting period of the reversing switch L1, when the charge is sampled at the phase, the pixel unit outputs Vrst, at the moment, the circuit is in a unit gain state, the common-mode voltage VCM is input and output, and switches at two ends of the capacitor CH are in a turn-off state; in the charge holding phase, the switch I11 and the switch I1 are simultaneously turned on, the input voltage is Vsig output by the pixel unit, then the switch I11 is turned off first, and the switch I1 is turned off later, so that the influence of charge injection of the switch is reduced, until the sampling phase of the next period, the differential output value of the output bus is reduced from Vo1 to the voltage change of 0 VCM-VCM, and the differential output value is coupled into the holding capacitor CH;
in the step 2, the method specifically comprises the following steps: in the period that the commutation switch L2 is turned on, the output of the pixel unit is connected with the positive terminal of the OPA, the switches K1 and K11 are turned on simultaneously, the switch K11 is turned off first, the switch K1 is turned off, and the differential output value of the output bus line rises from Vo2 to 0 in the period.
The invention has the beneficial effects that: after the reversing switch is added, the circuit is still compatible with the related double sampling and offset storage characteristics of the original circuit. The control mode is compatible with the clock of the original circuit, the influence on the precision of the original circuit is very little, the accumulated output values of two adjacent times of the advanced digital-analog domain accumulator are extremely close, and then the advanced digital-analog domain accumulator is subjected to polarity switching operation, so that the bus voltage change caused by the two times is reversed, the effect of dynamic offset is achieved, and the circuit area is not increased.
Drawings
FIG. 1 is a schematic diagram of a high level analog-to-digital domain TDI circuit with parasitic effect suppression according to the present invention;
FIG. 2 is a variation curve of the output bus of the circuit according to the present invention after the circuit is implemented.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
The invention relates to an advanced digital-analog domain TDI circuit for inhibiting parasitic effect, which comprises a fully differential operational amplifier (OPA) as shown in figure 1, wherein positive and negative electrode VIN interfaces of the fully differential operational amplifier (OPA) are respectively connected with a sampling capacitor CS, reversing switches L1 are arranged between the fully differential operational amplifier (OPA) and the sampling capacitor CS, and two reversing switches L1 are connected through two reversing switches L2; one sampling capacitor CS is connected with a reference voltage VREF, the other sampling capacitor CS is connected with a pixel unit, and an anode VIN interface and a cathode VIN interface of the fully differential operational amplifier OPA are respectively connected with a plurality of capacitor CH upper and lower pole plate switching circuits which are connected in parallel;
the upper and lower pole plate switching circuit of each capacitor CH comprises a capacitor CH connected with a fully differential operational amplifier OPA, one end of the capacitor CH is respectively connected with a switch I11 and a switch K1, the other end of the capacitor CH is respectively connected with a switch I1 and a switch K11, the switch I11 and the switch K11 are respectively connected with a negative electrode VIN interface or a positive electrode VIN interface of the fully differential operational amplifier OPA, and the switch K1 and the switch I1 are respectively connected with a positive electrode VOUT interface or a negative electrode VOUT interface of the fully differential operational amplifier OPA;
the invention relates to a method for realizing an advanced digital-analog domain TDI circuit for inhibiting parasitic effect, which comprises the following steps:
the method specifically comprises the following steps: in the conducting period of the reversing switch L1, when the charge is sampled at the phase, the pixel unit outputs Vrst, at the moment, the circuit is in a unit gain state, the common-mode voltage VCM is input and output, and switches at two ends of the capacitor CH are in a turn-off state; in the charge holding phase, the switch I11 and the switch I1 are simultaneously turned on, the input voltage is Vsig output by the pixel unit, then the switch I11 is turned off first, and the switch I1 is turned off later, so that the influence of charge injection of the switch is reduced, until the sampling phase of the next period, the differential output value of the output bus is reduced from Vo1 to the voltage change of 0 VCM-VCM, and the differential output value is coupled into the holding capacitor CH;
the method specifically comprises the following steps: in the period that the reversing switch L2 is turned on, the output of the pixel unit is connected with the positive terminal of the OPA, the states in the sampling stage are the same, because the upper and lower polar plates of the holding capacitor CH in the previous period retain the previous voltage, VOUT + is originally high voltage, the upper and lower polar plates of the capacitor are required to be turned over and charged to achieve the effects that VOUT + outputs low voltage and VOUT-outputs high voltage at the moment, the switches K1 and K11 are turned on simultaneously, the rear switch K11 is turned off firstly, the switch K1 is turned off, and the differential output value of the output bus in the period is increased to 0 from Vo 2;
step 3, taking two accumulation periods as a large accumulation period, accumulating enough corresponding stages and outputting;
and 4, refreshing the output holding capacitor CH in the next large accumulation period and repeating the accumulation process.
Fig. 2 shows the comparison of the output bus change after adding the polarity switching circuit with the original circuit, because Vo1 and Vo2 are close in size and opposite in polarity, the parasitic capacitance coupling influences caused by the Vo1 and the Vo2 are opposite in polarity and mutually offset, and the theoretical analysis shows that when the accumulated number reaches 64 levels, the optimization effect can reach 2 to 3 orders of magnitude compared with the original circuit.
According to the high-grade digital-analog domain TDI circuit for inhibiting the parasitic effect, the added circuit after the reversing switch is still compatible with the related double sampling and offset storage characteristics of the original circuit. The control mode is compatible with the clock of the original circuit, the influence on the precision of the original circuit is very little, the accumulated output values of two adjacent times of the advanced digital-analog domain accumulator are extremely close, and then the polarity switching operation is carried out on the accumulated output values so as to reverse the change of the bus voltage caused by the two times, thus the effect of dynamic offset is achieved.
The method of the invention divides the accumulation period into a first accumulation period and a second accumulation period. The output polarities of the two accumulation periods are opposite and the values are close to cancel each other out.
Claims (5)
1. A high-level digital-analog domain TDI circuit for restraining parasitic effect is characterized by comprising a fully differential operational amplifier (OPA), wherein positive and negative electrode VIN interfaces of the fully differential operational amplifier (OPA) are respectively connected with a sampling capacitor CS, reversing switches L1 are arranged between the fully differential operational amplifier (OPA) and the sampling capacitor CS, and the two reversing switches L1 are connected through two reversing switches L2; one of the sampling capacitors CS is connected with a reference voltage VREF, the other sampling capacitor CS is connected with a pixel unit, and an anode VIN interface and a cathode VIN interface of the fully differential operational amplifier OPA are respectively connected with a plurality of capacitor CH upper and lower pole plate switching circuits which are connected in parallel.
2. The advanced digital-analog domain TDI circuit capable of suppressing the parasitic effect as recited in claim 1, wherein each of said capacitor CH upper and lower plate switching circuits comprises a capacitor CH connected with a fully differential operational amplifier OPA, one end of said capacitor CH is connected with a switch I11 and a switch K1, the other end of said capacitor CH is connected with a switch I1 and a switch K11, said switch I11 and said switch K11 are connected with a negative VIN interface or a positive VIN interface of the fully differential operational amplifier OPA, and said switch K1 and said switch I1 are connected with a positive VOUT interface or a negative VOUT interface of the fully differential operational amplifier OPA.
3. A method for realizing a high-grade digital-analog domain TDI circuit for inhibiting parasitic effect is characterized by comprising the following steps:
step 1, the analog domain accumulator carries out accumulation operation of one normal polarity, and a first accumulation period is controlled through a reversing switch L1;
step 2, the analog domain accumulator carries out accumulation operation with opposite polarity for one time, the parasitic effect influence of the previous accumulation operation is counteracted, and a second accumulation period is controlled through a reversing switch L2;
step 3, taking two accumulation periods as a large accumulation period, accumulating enough corresponding stages and outputting;
and 4, refreshing the output holding capacitor CH in the next large accumulation period and repeating the accumulation process.
4. The method for implementing the advanced digital-analog-domain TDI circuit capable of suppressing the parasitic effect as claimed in claim 3, wherein in the step 1, specifically: in the conducting period of the reversing switch L1, when the charge is sampled at the phase, the pixel unit outputs Vrst, at the moment, the circuit is in a unit gain state, the common-mode voltage VCM is input and output, and switches at two ends of the capacitor CH are in a turn-off state; in the charge holding phase, the switch I11 and the switch I1 are simultaneously turned on, the input voltage is Vsig output by the pixel unit, then the switch I11 is turned off first, and the switch I1 is turned off later, so that the influence of the switch charge injection is reduced, until the sampling phase of the next period, the differential output value of the output bus is reduced from Vo1 to the voltage change of VCM-VCM ═ 0, and the differential output value is coupled into the holding capacitor CH.
5. The method for implementing the advanced digital-analog-domain TDI circuit capable of suppressing the parasitic effect as claimed in claim 4, wherein in the step 2, specifically: in the period that the commutation switch L2 is turned on, the output of the pixel unit is connected with the positive terminal of the OPA, the switches K1 and K11 are turned on simultaneously, the switch K11 is turned off first, the switch K1 is turned off, and the differential output value of the output bus line rises from Vo2 to 0 in the period.
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| CN113824910A (en) * | 2021-08-10 | 2021-12-21 | 西安理工大学 | Analog domain high-level TDI accelerating circuit and accelerating implementation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113824909A (en) * | 2021-08-10 | 2021-12-21 | 西安理工大学 | High-level digital Time Delay Integration (TDI) analog domain circuit capable of eliminating parasitic effect and implementation method thereof |
| CN113824910A (en) * | 2021-08-10 | 2021-12-21 | 西安理工大学 | Analog domain high-level TDI accelerating circuit and accelerating implementation method thereof |
| CN113824910B (en) * | 2021-08-10 | 2023-07-21 | 西安理工大学 | Analog domain advanced TDI (time delay integration) acceleration circuit and acceleration implementation method thereof |
| CN113824909B (en) * | 2021-08-10 | 2024-04-16 | 西安理工大学 | Advanced TDI analog domain circuit capable of eliminating parasitic effect and implementation method thereof |
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