CN113824909B - Advanced TDI analog domain circuit capable of eliminating parasitic effect and implementation method thereof - Google Patents
Advanced TDI analog domain circuit capable of eliminating parasitic effect and implementation method thereof Download PDFInfo
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- CN113824909B CN113824909B CN202110914112.8A CN202110914112A CN113824909B CN 113824909 B CN113824909 B CN 113824909B CN 202110914112 A CN202110914112 A CN 202110914112A CN 113824909 B CN113824909 B CN 113824909B
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- 230000003071 parasitic effect Effects 0.000 title claims abstract description 47
- 238000000034 method Methods 0.000 title claims abstract description 15
- 238000005070 sampling Methods 0.000 claims abstract description 26
- 239000003990 capacitor Substances 0.000 claims description 73
- 238000009825 accumulation Methods 0.000 claims description 37
- 230000002829 reductive effect Effects 0.000 claims description 7
- 230000000875 corresponding effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
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- 230000000295 complement effect Effects 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/768—Addressed sensors, e.g. MOS or CMOS sensors for time delay and integration [TDI]
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Abstract
The invention discloses a high-level TDI analog domain circuit capable of eliminating parasitic effect, which alternately charges an upper polar plate and a lower polar plate by introducing polarity change-over switches L1 and L2, and simultaneously adds a CH upper polar plate change-over switch and a CH lower polar plate change-over switch to ensure that charges in CH cannot be counteracted by input after polarity change, and the output of an operational amplifier is switched between high voltage and low voltage by the control of the switches; introducing a positive feedback capacitance Cb in the holding stage to counteract the loss of parasitic capacitance to the transferred charge; the invention also discloses a realization method of the advanced TDI analog domain circuit capable of eliminating the parasitic effect, which eliminates the parasitic effect in the sampling stage and the holding stage in the analog domain accumulating process and greatly improves the accumulating precision of the analog domain TDI circuit.
Description
Technical Field
The invention belongs to the technical field of analog domain CMOS-TDI circuits, relates to a high-level digital-to-analog (TDI) analog domain circuit capable of eliminating parasitic effects, and also relates to an implementation method of the circuit.
Background
A great deal of attention has been paid to CMOS (complementary metal-oxide-silicon) image sensors, which have advantages of low power consumption, easy integration in a system-on-chip, and the like. With the wide development of image sensors, in partial low-light imaging, new requirements are placed on the accuracy and the signal-to-noise ratio of images, and the level of a traditional analog domain TDI (Time-Delay-Integration) circuit is limited by parasitic influence caused by high level. The parasitic effect is eliminated based on adding decoupling capacitance, and the capacitance network between the original storage capacitance CH and the parasitic capacitance is reorganized to reduce the parasitic capacitance formed by the parasitic capacitance, wherein the parasitic capacitance comprises a full differential operational amplifier, a storage capacitance network, sampling capacitance and parasitic bus parasitic capacitances Cpt and Cpb, decoupling capacitance Cb, and single-stage total parasitic capacitance Cp of the parasitic capacitance and the storage capacitance CH, and when the accumulation level is higher, the total parasitic capacitance is Cptotal and is connected between the input bus and the output bus.
In one accumulation period of the TDI circuit, two stages of charge sampling phase and charge holding phase are provided, the charge sampling phase is conducted by CLK, the operational amplifier is in a unit gain state, VIN is pixel unit reset voltage Vrst, CS samples the voltage, and switches at two ends of CH are turned off, and Cp is reduced by several orders of magnitude due to the addition of decoupling capacitance, so that the influence of voltage change of an input/output bus on CH at the moment is negligible. When the charge holding phase is entered, CLK is turned off, VIN is the readout voltage Vsig of the pixel unit, at this time, the switches at two ends of CH are turned on to perform charge transfer, in this process, some of the stored charge and transferred charge in CH are absorbed by the parasitic capacitance Cptotal, while the output voltage rises to Vo1, after the phase is ended until the next accumulation period starts, the voltage at two ends of the input/output bus is Vo1, when the charge sampling phase of the next period is entered, the voltage of the output/input bus falls from Vo1 to 0, and when this voltage changes, the bus voltage change affects the CH at the core, because of the decoupling capacitance Cd, cp is reduced, so the influence of the bus voltage change on CH and the influence of the parasitic capacitance on the stored charge and transferred charge are reduced.
For the scheme, the decoupling capacitance is added to well inhibit parasitic influence, but the integrator of each stage needs a decoupling capacitance Cd, when the TDI level is higher, the sacrificial layout area is too large, so that the parasitic influence mechanism can be further utilized to optimize the circuit structure without introducing additional capacitance and devices.
Disclosure of Invention
The invention aims to provide a high-level TDI analog domain circuit capable of eliminating parasitic effect, which can dynamically adjust the size of a positive feedback capacitor Cb by pre-sampling an accumulation value once before formal accumulation, so that the positive feedback capacitor Cb counteracts the influence of the extremely parasitic capacitance on stored charge and transferred charge.
The invention also provides an implementation method of the advanced TDI analog domain circuit capable of eliminating parasitic effect.
The first technical scheme adopted by the invention is that the high-level TDI analog domain circuit capable of eliminating parasitic effect comprises a full differential operational amplifier OPA, positive and negative electrode VIN interfaces of the full differential operational amplifier OPA are respectively connected with a sampling capacitor CS, reversing switches L1 are arranged between the full differential operational amplifier OPA and the sampling capacitor CS, the two reversing switches L1 are also connected through two reversing switches L2, a switch I is arranged between a positive feedback capacitor Cb and an input bus, and a switch I' and a switch I are respectively arranged between the positive feedback capacitor Cb and positive and negative output ends; one sampling capacitor CS is connected with a reference voltage VREF, the other sampling capacitor CS is connected with a pixel unit, and an anode VIN interface and a cathode VIN interface of the full differential operational amplifier OPA are also respectively connected with a plurality of capacitors CH upper and lower polar plate switching circuits which are mutually connected in parallel.
The first technical scheme of the invention is characterized in that:
the upper polar plate and lower polar plate switching circuit of each capacitor CH comprises a capacitor CHi connected with a fully differential operational amplifier OPA, one end of the capacitor CHi is respectively connected with a switch Iii and a switch Ki, the other end of the capacitor CHi is respectively connected with a switch Ii and a switch Kii, the switch Iii and the switch Kii are both connected with a negative pole VIN interface or a positive pole VIN interface of the fully differential operational amplifier OPA, the switch Ki and the switch Ii are both connected with a positive pole VOUT interface or a negative pole VOUT interface of the fully differential operational amplifier OPA, and i=1, 2.
One end of the positive feedback capacitor Cb is connected with the switch I, the other end of the positive feedback capacitor Cb is connected with I ', one end of the switch I is connected with the input bus, the other end of the switch I is connected with the positive feedback capacitor Cb, one end of the switch I is connected with the output bus of the other side, one end of the switch I ' is connected with the positive feedback capacitor Cb, and one end of the switch I ' is connected with the output bus of the side.
The second technical scheme adopted by the invention is that the implementation method of the advanced TDI analog domain circuit capable of eliminating parasitic effect comprises the following steps:
step 1, an analog domain accumulator performs an accumulation operation of normal polarity;
step 2, the analog domain accumulator performs one accumulation operation with opposite polarity, and counteracts the parasitic effect influence of the last accumulation operation;
step 3, taking the two accumulation periods as a large accumulation period, accumulating the accumulation periods to be corresponding to the series, and outputting the accumulated accumulation periods;
and 4, refreshing the holding capacitor CHi after output in the next accumulation period and repeating the accumulation process of the steps 1-3.
The second technical scheme adopted by the invention is characterized in that:
the specific process of the step 1 is as follows:
in the conduction period of the reversing switch L1, when the charge is sampled in phase, the pixel unit outputs Vrst, the circuit is in a unit gain state, the input and output common-mode voltage VCM is input, and the switches at the two ends of the capacitor CHi are in an off state; the switch I is communicated with the switch I', and the charge inside the positive feedback capacitor Cb is refreshed; in the charge holding phase, the switch Iii is simultaneously turned on with the switch Ii, the input voltage is the pixel cell output Vsig, the switches I and I are turned on, and the positive and negative output voltages of the full differential are symmetrical about VCM, so that when the positive feedback capacitance Cb and the parasitic total capacitance Cptotal are equal, the effects on the stored charge and the transferred charge are offset from each other, the switch Iii is turned off first, the switch Ii is turned off later, and the differential output value of the output bus is reduced from Vo1 to VCM-vcm=0 until the sampling phase of the next cycle, and the voltage change is coupled into the holding capacitance CHi.
The specific process of the step 2 is as follows: in the period of turning on the reversing switch L2, the output of the pixel unit is connected to the positive end of the fully differential operational amplifier OPA, the switch Ki and the switch Kii are turned on simultaneously, the switch Kii is turned off first, the switch Ki is turned off later, and the differential output value of the output bus rises from Vo2 to 0 in this period.
The beneficial effects of the invention are as follows: the high-level TDI analog domain circuit capable of eliminating parasitic effect provided by the invention is compatible with the related double sampling and offset storage characteristics of the original circuit after the circuit is added with the reversing switch. The control mode is compatible with the clock of the original circuit, has very little influence on the precision of the original circuit, utilizes the extremely close adjacent two accumulated output values of the advanced analog domain accumulator, and then carries out polarity switching operation to reverse the bus voltage change caused by the two times before and after, so as to achieve the effect of dynamic offset, does not increase the circuit area, and pre-samples the accumulated value for one time before formal accumulation to dynamically adjust the size of the positive feedback capacitor Cb, so that the influence of the extremely parasitic capacitor on the stored charge and the transferred charge is offset.
Drawings
FIG. 1 is a schematic diagram of an advanced TDI analog domain circuit capable of eliminating parasitic effects according to the present invention;
fig. 2 is a graph showing the variation between the implemented advanced TDI analog domain circuit and the output bus of the original circuit, which can eliminate the parasitic effect.
Detailed Description
The invention will be described in detail below with reference to the drawings and the detailed description.
The invention can eliminate the high-level TDI (Time-Delay-Integration) image sensor analog domain circuit of the parasitic effect, as shown in figure 1, include the full differential operational amplifier OPA, positive and negative electrode VIN interface of the full differential operational amplifier OPA connects the sampling capacitor CS separately, there are commutating switches L1 between OPA and connecting the sampling capacitor CS of the full differential operational amplifier, connect through two commutating switches L2 between two commutating switches L1 too, there are switches I between positive feedback capacitor Cb and input bus, positive feedback capacitor Cb and output positive and negative output end have switches I' and I respectively; one sampling capacitor CS is connected with a reference voltage VREF, the other sampling capacitor CS is connected with a pixel unit, and an anode VIN interface and a cathode VIN interface of the full differential operational amplifier OPA are also respectively connected with N capacitors CH upper and lower polar plate switching circuits which are mutually connected in parallel;
the upper polar plate and lower polar plate switching circuit of each capacitor CH comprises a capacitor CHi connected with the fully differential operational amplifier OPA, one end of the capacitor CHi is respectively connected with a switch Iii and a switch Ki, the other end of the capacitor CHi is respectively connected with a switch Ii and a switch Kii, the switch Iii and the switch Kii are both connected with the negative pole VIN interface or the positive pole VIN interface of the fully differential operational amplifier OPA, and the switch Ki and the switch Ii are both connected with the positive pole VOUT interface or the negative pole VOUT interface of the fully differential operational amplifier OPA; where i=1, 2, &..;
when I is 1, the corresponding switches are I1, I11, K1 and K11 respectively;
when I is 2, the corresponding switches are I2, I22, K2 and K22 respectively;
......
when i is N, the corresponding switches are IN, INN, KN, KNN respectively;
the number of pixel units is N, respectively pixel 1, pixel 2, pixel 3, and.
One end of the positive feedback capacitor Cb is connected with the switch I, the other end of the positive feedback capacitor Cb is connected with I', one end of the switch I is connected with the input bus, the other end of the switch I is connected with the positive feedback capacitor Cb, one end of the switch I is connected with the output bus of the other side, one end of the switch I is connected with the positive feedback capacitor Cb, and the other end of the switch I is connected with the output bus of the side.
The invention discloses a high-level TD analog domain implementation method for eliminating parasitic effect, which specifically comprises the following steps:
step 1, the analog domain accumulator performs an accumulation operation of normal polarity, specifically,
in the conduction period of the reversing switch L1, when the charge is sampled in phase, the pixel unit outputs Vrst, at the moment, the circuit is in a unit gain state, the input and output common-mode voltage VCM is input, and the switches at the two ends of the capacitor CH are in an off state; the switch I is conducted with the switch I', and Cb internal charge is refreshed; when the charge keeps the phase, the switch Iii is conducted with the switch Ii at the same time, the input voltage is the pixel unit output Vsig, the switch I is conducted with the switch I, and the positive and negative output terminal voltages of the full differential are symmetrical by taking VCM as the center, so when the positive feedback capacitor Cb and the parasitic total capacitor Cptotal are equal, the switch Iii is disconnected firstly, the switch Ii is disconnected afterwards, the influence of the switch charge injection is reduced, the differential output value of the output bus is reduced from Vo1 to VCM-vcm=0 until the sampling phase of the next period, and the voltage change is coupled into the holding capacitor CH;
step 2, the analog domain accumulator performs one accumulation operation with opposite polarity, and counteracts the parasitic effect influence of the last accumulation operation;
in the period that the reversing switch L2 is turned on, the output of the pixel unit is connected to the positive end of the OPA, the state of the sampling stage is the same, because the upper polar plate and the lower polar plate of the holding capacitor CH in the previous period keep the previous voltage, VOUT+ is high voltage, the upper polar plate and the lower polar plate of the capacitor need to be turned over and charged to achieve the effect that VOUT+ outputs low voltage at the moment, VOUT-outputs high voltage, the switches Ki and Kii are simultaneously turned on, the switch Kii is firstly turned off, the switch Ki is turned off, and the differential output value of the output bus in the period rises from Vo2 to 0.
And step 3, taking two accumulation periods as a large accumulation period, accumulating the accumulation periods to obtain corresponding series, and outputting the accumulated accumulation periods.
And 4, refreshing the holding capacitor CHi after output in the next accumulation period and repeating the accumulation process.
Fig. 2 shows a graph of the differential output effect between the introduction of positive feedback and the non-introduction of positive feedback, vn is the result before the introduction of positive feedback, and the output accuracy is further improved after the introduction of the adjustable positive feedback capacitor. In fig. 2, i has a value of 3.
The invention adopts the output polarity switching technology and the positive feedback capacitance technology to be suitable for the high-level CMOS-TDI analog domain realization circuit, so that the change of the original circuit structure is small, the effect of inhibiting parasitic effect is achieved by controlling a switch and an adjustable positive feedback capacitance by logic, wherein the switch L1 controls a first accumulation period, the switch L2 controls a second accumulation period, the switches IN and INN matched with the switch L1 and the switch L2 are used for charging with normal polarity, the KN and KNN control the switches L1 and the switch L2 are used for charging reversely, the positive feedback capacitance Cb is used for brushing internal charge IN a sampling stage, and the positive feedback is provided by connecting the I IN a stage I with an output bus at the other end.
The improved circuit of the advanced TDI analog domain circuit capable of eliminating parasitic effect is compatible with the correlated double sampling and offset storage characteristics of the original circuit. The control mode is compatible with the clock of the original circuit, has very little influence on the precision of the original circuit, and utilizes the extremely close accumulated output values of the adjacent two times of the advanced analog domain accumulator, and then carries out polarity switching operation to enable the bus voltage change caused by the previous and subsequent two times to be reverse, so that the positive feedback capacitor counteracts the influence of the parasitic capacitance on the stored charge and the transferred charge in the holding stage.
The invention can eliminate parasitic effect, and the high-level TDI analog domain circuit alternately uses the upper and lower polar plates of the storage capacitor CH to charge and introduces the positive feedback capacitor Cb, thus being applicable to the analog domain implementation circuit of the high-level CMOS-TDI image sensor. The output voltage of the pixel unit is alternately charged into the upper polar plate and the lower polar plate by introducing the polarity change-over switches L1 and L2, and meanwhile, in order to ensure that the charge in the capacitor CH is not counteracted by the input after the polarity is changed, the upper polar plate change-over switches and the lower polar plate change-over switches of the capacitor CH are added, and the output of the operational amplifier is switched between high voltage and low voltage by the control of the switches; the positive feedback capacitor Cb is introduced in the holding stage to offset the loss of the parasitic capacitor on the transferred charge, and the parasitic influence in the sampling stage and the holding stage in the analog domain accumulation process is eliminated by the method, so that the accumulation precision of the analog domain TDI circuit is greatly improved.
Claims (1)
1. The high-level TDI analog domain circuit capable of eliminating parasitic effect is characterized in that: the positive-negative voltage source circuit comprises a full-differential operational amplifier OPA, wherein positive-negative voltage source interfaces VIN of the full-differential operational amplifier OPA are respectively connected with a sampling capacitor CS, reversing switches L1 are arranged between the full-differential operational amplifier OPA and the sampling capacitor CS, the two reversing switches L1 are also connected through two reversing switches L2, a switch I is arranged between a positive feedback capacitor Cb and an input bus, and switches I' and I are respectively arranged at positive feedback capacitor Cb and positive and negative output ends; one sampling capacitor CS is connected with a reference voltage VREF, the other sampling capacitor CS is connected with a pixel unit, and an anode VIN interface and a cathode VIN interface of the full differential operational amplifier OPA are also respectively connected with a plurality of capacitors CH upper and lower polar plate switching circuits which are mutually connected in parallel;
each capacitor CH upper and lower polar plate switching circuit comprises a capacitor CHi connected with a fully differential operational amplifier OPA, one end of the capacitor CHi is respectively connected with a switch Iii and a switch Ki, the other end of the capacitor CHi is respectively connected with a switch Ii and a switch Kii, the switch Iii and the switch Kii are both connected with a negative electrode VIN interface or a positive electrode VIN interface of the fully differential operational amplifier OPA, the switch Ki and the switch Ii are both connected with a positive electrode VOUT interface or a negative electrode VOUT interface of the fully differential operational amplifier OPA, and i=1, 2.
One end of the positive feedback capacitor Cb is connected with the switch I, the other end of the positive feedback capacitor Cb is connected with I, one end of the switch I is connected with the input bus, the other end of the switch I is connected with the positive feedback capacitor Cb, one end of the switch I is connected with the output bus of the other side, one end of the switch I 'is connected with the positive feedback capacitor Cb, and one end of the switch I' is connected with the output bus of the side;
the implementation method of the advanced TDI analog domain circuit capable of eliminating parasitic effect comprises the following steps:
step 1, an analog domain accumulator performs an accumulation operation of normal polarity;
the specific process of the step 1 is as follows:
in the conduction period of the reversing switch L1, when the charge is sampled in phase, the pixel unit outputs Vrst, the circuit is in a unit gain state, the input and output common-mode voltage VCM is input, and the switches at the two ends of the capacitor CHi are in an off state; the switch I is communicated with the switch I', and the charge inside the positive feedback capacitor Cb is refreshed; when the charge keeps the phase, the switch Iii is conducted with the switch Ii at the same time, the input voltage is the pixel unit output Vsig, the switches I and I are conducted, because the positive and negative output voltages of the full differential are symmetrical with VCM as the center, when the positive feedback capacitor Cb and the parasitic total capacitor Cptotal are equal, the switch Iii is disconnected firstly, the switch Ii is disconnected afterwards, and the differential output value of the output bus is reduced from Vo1 to VCM-vcm=0 until the sampling phase of the next period, and the voltage change is coupled into the holding capacitor CH;
step 2, the analog domain accumulator performs one accumulation operation with opposite polarity, and counteracts the parasitic effect influence of the last accumulation operation;
the specific process of the step 2 is as follows: in the period that the reversing switch L2 is turned on, the output of the pixel unit is connected with the positive end of the full-differential operational amplifier OPA, the switch Ki and the switch Kii are simultaneously turned on, the switch Kii is turned off firstly, the switch Ki is turned off later, and the differential output value of the output bus in the period rises from Vo2 to 0;
step 3, taking the two accumulation periods as a large accumulation period, accumulating the accumulation periods to be corresponding to the series, and outputting the accumulated accumulation periods;
and 4, refreshing the holding capacitor CHi after output in the next accumulation period and repeating the accumulation processes of the steps 1-3.
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