CN113824909A - High-level digital Time Delay Integration (TDI) analog domain circuit capable of eliminating parasitic effect and implementation method thereof - Google Patents
High-level digital Time Delay Integration (TDI) analog domain circuit capable of eliminating parasitic effect and implementation method thereof Download PDFInfo
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- CN113824909A CN113824909A CN202110914112.8A CN202110914112A CN113824909A CN 113824909 A CN113824909 A CN 113824909A CN 202110914112 A CN202110914112 A CN 202110914112A CN 113824909 A CN113824909 A CN 113824909A
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- 230000003071 parasitic effect Effects 0.000 title claims abstract description 46
- 238000000034 method Methods 0.000 title claims abstract description 21
- 230000010354 integration Effects 0.000 title description 3
- 239000003990 capacitor Substances 0.000 claims abstract description 84
- 238000009825 accumulation Methods 0.000 claims abstract description 30
- 238000005070 sampling Methods 0.000 claims abstract description 27
- 230000000694 effects Effects 0.000 claims description 8
- 241000606706 Chione <angiosperm> Species 0.000 claims 1
- 230000002829 reductive effect Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/768—Addressed sensors, e.g. MOS or CMOS sensors for time delay and integration [TDI]
Abstract
The invention discloses a high-level digital TDI analog domain circuit capable of eliminating parasitic effect, which alternately charges upper and lower polar plates with output voltage of a pixel unit by introducing polarity change-over switches L1 and L2, and simultaneously adds the upper and lower polar plate change-over switches of CH in order to ensure that the charge in CH is not offset by the input after polarity change-over, and the output of an operational amplifier is switched between high voltage and low voltage by the control of the switches; introducing a positive feedback capacitor Cb in the holding stage to offset the loss of the parasitic capacitance to the transferred charge; the invention also discloses a realization method of the high-grade digital TDI analog domain circuit capable of eliminating parasitic effect, which eliminates parasitic influence in a sampling stage and a holding stage in the analog domain accumulation process by the method and greatly improves the accumulation precision of the TDI circuit in the analog domain.
Description
Technical Field
The invention belongs to the technical field of analog domain CMOS-TDI circuits, relates to a high-level digital TDI analog domain circuit capable of eliminating parasitic effects, and further relates to an implementation method of the circuit.
Background
Much attention has been paid to CMOS (complementary-oxide-semiconductor) image sensors because of their advantages, such as low power consumption and ease of integration into systems on chip. With the wide development of image sensors, in partial low-light shooting, new requirements are made on the accuracy and the signal-to-noise ratio of images, and the stage number of a conventional analog domain TDI (Time-Delay-Integration) circuit is limited by the parasitic influence caused by high-level numbers. Based on the addition of decoupling capacitors to eliminate parasitic effect, the capacitance network between the original storage capacitor CH and the parasitic capacitor is reformed to reduce the parasitic capacitance formed by the capacitance network, and the capacitance network comprises a fully differential operational amplifier, a storage capacitor network, sampling capacitors and parasitic bus parasitic capacitors Cpt and Cpb, a decoupling capacitor Cb, and a single-stage total parasitic capacitor Cp of the parasitic capacitor and the storage capacitor CH, wherein the total parasitic capacitor Cptotal is connected between the input bus and the output bus when the accumulated stage number is higher.
In an accumulation period of the TDI circuit, a charge sampling phase and a charge holding phase are arranged, the charge sampling phase is that CLK is conducted, the operational amplifier is in a unit gain state, VIN is pixel unit reset voltage Vrst, CS samples the voltage, switches at two ends of CH are turned off, and Cp is reduced by several orders of magnitude due to the addition of decoupling capacitance, so that the influence of voltage change of an input/output bus on CH at the moment can be ignored. When a charge holding phase is entered, CLK is turned off, the voltage of VIN is a reading voltage Vsig of a pixel unit, switches at two ends of CH are turned on for charge transfer, in the process, a part of charges stored in CH and transferred charges is absorbed by a parasitic capacitor Cptotal, meanwhile, the output voltage rises to Vo1, after the phase is finished, the voltage at two ends of an input/output bus is known to be Vo1, when a charge sampling phase of the next period is entered, the voltage of the output/input bus is reduced from Vo1 to 0, and the voltage change of the bus affects the core of CH because a decoupling capacitor Cd exists and reduces Cp, so the influence of the change of the bus voltage on CH and the influence of the parasitic capacitor on stored charges and transferred charges are reduced.
It can be seen from the above solutions that the parasitic influence is well suppressed by adding the decoupling capacitor, but each stage of integrator needs a decoupling capacitor Cd, and when the TDI stage is higher, the sacrificial layout area is too large, so that the circuit structure can be further optimized by using the mechanism of the parasitic influence without introducing additional capacitors and devices.
Disclosure of Invention
The invention aims to provide a high-level digital TDI analog domain circuit capable of eliminating parasitic effect, which can dynamically adjust the size of a positive feedback capacitor Cb by pre-sampling once accumulated numerical value before formal accumulation, so that the positive feedback capacitor Cb can counteract the influence of extreme parasitic capacitance on stored charge and transferred charge.
The invention also provides a realization method of the high-level digital TDI analog domain circuit capable of eliminating parasitic effect.
The invention adopts a first technical scheme that an advanced digital TDI analog domain circuit capable of eliminating parasitic effect comprises a fully differential operational amplifier (OPA), positive and negative electrode VIN interfaces of the fully differential operational amplifier (OPA) are respectively connected with a sampling Capacitor (CS), reversing switches L1 are arranged between the fully differential operational amplifier (OPA) and the sampling Capacitor (CS), two reversing switches L1 are also connected through two reversing switches L2, a switch I is arranged between a positive feedback capacitor Cb and an input bus, and the positive feedback capacitor Cb and positive and negative output ends are respectively provided with switches I' and I; one of the sampling capacitors CS is connected with a reference voltage VREF, the other sampling capacitor CS is connected with a pixel unit, and a positive electrode VIN interface and a negative electrode VIN interface of the full-differential operational amplifier OPA are respectively connected with a plurality of capacitor CH upper and lower pole plate switching circuits which are connected in parallel.
The first technical scheme of the invention is also characterized in that:
the upper and lower polar plate switching circuit of each capacitor CH comprises a capacitor CHi connected with a fully differential operational amplifier OPA, one end of the capacitor CHi is respectively connected with a switch Iii and a switch Ki, the other end of the capacitor CHi is respectively connected with a switch Ii and a switch Kii, the switch Iii and the switch Kii are both connected with a negative electrode VIN interface or a positive electrode VIN interface of the fully differential operational amplifier OPA, the switch Ki and the switch Ii are both connected with a positive electrode VOUT interface or a negative electrode VOUT interface of the fully differential operational amplifier OPA, and i is 1, 2.
One end of the positive feedback capacitor Cb is connected with the switch I, the other end of the positive feedback capacitor Cb is connected with the I ' and the I, one end of the switch I is connected with the input bus, the other end of the switch I is connected with the positive feedback capacitor Cb, one end of the I is connected with the Cb, the other end of the I is connected with the output bus on the other side, one end of the switch I ' is connected with the positive feedback capacitor Cb, and one end of the switch I ' is connected with the output bus on the side.
The second technical scheme adopted by the invention is that the implementation method of the high-level digital TDI analog domain circuit capable of eliminating parasitic effect specifically comprises the following steps:
step 3, taking the two accumulation periods as a large accumulation period, accumulating enough corresponding stages and outputting;
and 4, refreshing the output hold capacitor CHi in the next accumulation period and repeating the accumulation processes in the steps 1 to 3.
The second technical scheme adopted by the invention is also characterized in that:
the specific process of the step 1 is as follows:
in the conducting period of the reversing switch L1, when the charge is sampled at the phase, the pixel unit outputs Vrst, at the moment, the circuit is in a unit gain state, the common-mode voltage VCM is input and output, and switches at two ends of the capacitor CHi are in a turn-off state; the switch I is conducted with the switch I', and the internal charge of the positive feedback capacitor Cb is refreshed; in the charge holding phase, the switch Iii is turned on simultaneously with the switch Ii, the input voltage is the pixel cell output Vsig, the switches I and I are turned on, and since the fully differential positive and negative output voltages are symmetric about VCM, when the positive feedback capacitance Cb and the parasitic total capacitance Cptotal are equal, the effect on the stored charge and the transferred charge is cancelled, the switch Iii is turned off first, the switch Ii is turned off later, and until the sampling phase of the next cycle, the differential output value of the output bus is lowered from Vo1 to VCM-VCM equal to 0, and the voltage change is coupled into the holding capacitance CHi.
The specific process of the step 2 is as follows: in the period that the reversing switch L2 is turned on, the output of the pixel unit is connected with the positive terminal of the fully differential operational amplifier OPA, the switch Ki and the switch Kii are turned on simultaneously, the switch Kii is turned off firstly, the switch Ki is turned off later, and the differential output value of the output bus in the period rises from Vo2 to 0.
The invention has the beneficial effects that: the high-level digital TDI analog domain circuit capable of eliminating parasitic effect provided by the invention is still compatible with the related double sampling and offset storage characteristics of the original circuit after the reversing switch is added. The control mode is compatible with the clock of the original circuit and has little influence on the precision of the original circuit, the adjacent two accumulated output values of the advanced digital-analog domain accumulator are extremely close, then the advanced digital-analog domain accumulator is subjected to polarity switching operation to reverse the change of the bus voltage caused by the previous and subsequent two times, so that the effect of dynamic cancellation is achieved, the area of the circuit is not increased, and the value of the positive feedback capacitor Cb is dynamically adjusted by pre-sampling the accumulated value once before formal accumulation so as to cancel the influence of the extreme parasitic capacitor on stored charge and transferred charge.
Drawings
FIG. 1 is a schematic diagram of an advanced digital TDI analog domain circuit with parasitic effect elimination according to the present invention;
FIG. 2 is a variation curve of the output bus of the original circuit after the realization of the high-level digital TDI analog domain circuit capable of eliminating parasitic effect.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
The invention can eliminate the high-grade number TDI (Time-Delay-Integration) image sensor analog domain circuit of the parasitic effect, as shown in figure 1, including fully differential operational amplifier OPA, positive negative pole VIN interface of fully differential operational amplifier OPA connects sampling capacitor CS separately, all there are commutate switches L1 between fully differential operational amplifier OPA and connecting sampling capacitor CS, still connect through two commutate switches L2 between two commutate switches L1, there are switches I between positive feedback capacitor Cb and input bus, positive feedback capacitor Cb and output positive and negative output terminal have switches I' and I separately; one sampling capacitor CS is connected with a reference voltage VREF, the other sampling capacitor CS is connected with a pixel unit, and an anode VIN interface and a cathode VIN interface of the fully differential operational amplifier OPA are respectively connected with N capacitor CH upper and lower pole plate switching circuits which are connected in parallel;
the upper and lower pole plate switching circuit of each capacitor CH comprises a capacitor CHi connected with a fully differential operational amplifier OPA, one end of the capacitor CHi is respectively connected with a switch Iii and a switch Ki, the other end of the capacitor CHi is respectively connected with a switch Ii and a switch Kii, the switch Iii and the switch Kii are both connected with a negative electrode VIN interface or a positive electrode VIN interface of the fully differential operational amplifier OPA, and the switch Ki and the switch Ii are both connected with a positive electrode VOUT interface or a negative electrode VOUT interface of the fully differential operational amplifier OPA; wherein i1, 2.... N;
when I takes 1, the corresponding switches are I1, I11, K1 and K11 respectively;
when I takes 2, the corresponding switches are I2, I22, K2 and K22 respectively;
......
when N is taken as i, the corresponding switches are IN, INN, KN and KNN respectively;
n pixel units are respectively a pixel 1, a pixel 2, and a pixel 3.
One end of the positive feedback capacitor Cb is connected with the switch I, the other end of the positive feedback capacitor Cb is connected with the I ' and the I, one end of the switch I is connected with the input bus, the other end of the switch I is connected with the positive feedback capacitor Cb, one end of the I is connected with the positive feedback capacitor Cb, the other end of the I is connected with the output bus on the other side, one end of the switch I ' is connected with the positive feedback capacitor Cb, and the other end of the switch I ' is connected with the output bus on the other side.
The invention discloses a high-level digital TD analog domain implementation method for eliminating parasitic effect, which specifically comprises the following steps:
in the conducting period of the reversing switch L1, when the charge is sampled at the phase, the pixel unit outputs Vrst, at the moment, the circuit is in a unit gain state, the common-mode voltage VCM is input and output, and switches at two ends of the capacitor CH are in a turn-off state; the switches I and I' are conducted, and the internal charge of Cb is refreshed; in the charge holding phase, the switch Iii is turned on simultaneously with the switch Ii, the input voltage is the pixel unit output Vsig, the switches I and I are turned on, and since the fully differential positive and negative output terminal voltages are symmetric around VCM, when the positive feedback capacitance Cb and the parasitic total capacitance Cptotal are equal, the effect on the stored charge and the transferred charge is cancelled, the switch Iii is turned off first, the switch Ii is turned off later, the effect of the switch charge injection is reduced, until the sampling phase of the next cycle, the differential output value of the output bus is reduced from Vo1 to VCM-VCM 0, and the voltage change is coupled into the holding capacitance CH;
in the period that the reversing switch L2 is turned on, the output of the pixel unit is connected with the positive terminal of the OPA, the states in the sampling stage are the same, because the upper and lower polar plates of the holding capacitor CH in the previous period retain the previous voltage, VOUT + is originally high voltage, the upper and lower polar plates of the capacitor are required to be turned over and charged to achieve the effects that VOUT + outputs low voltage and VOUT-outputs high voltage at the moment, the switches Ki and Kii are turned on simultaneously, the switch Kii is turned off first, the switch Ki is turned off, and the differential output value of the output bus in the period is increased from Vo2 to 0.
And step 3, taking two accumulation periods as a large accumulation period, accumulating enough stages and outputting.
And 4, refreshing the hold capacitor CHi after output in the next accumulation period and repeating the accumulation process.
Fig. 2 shows a graph of the effect of differential output with and without positive feedback introduced, Vn is the result before positive feedback is introduced, and the output accuracy is further improved after the adjustable positive feedback capacitor is introduced. The value of i in fig. 2 is 3.
The invention adopts output polarity switching technology and positive feedback capacitance technology, is suitable for a high-grade CMOS-TDI analog domain realization circuit, ensures that the change of the original circuit structure is small, and achieves the effect of inhibiting parasitic effect by a logic control switch and an adjustable positive feedback capacitance, wherein a switch L1 controls a first accumulation period, a switch L2 controls a second accumulation period, a switch IN and an INN which are matched with the switch L1 and the switch L2 control the normal polarity charging, a switch L1 and a switch L2 control the reverse charging, the positive feedback capacitance Cb empties the internal charge IN the sampling stage, and an output bus connected at the other end IN the holding stage I provides positive feedback.
The improved circuit of the high-level digital TDI analog domain circuit capable of eliminating parasitic effect is still compatible with the related double sampling and offset storage characteristics of the original circuit. The control mode is compatible with the clock of the original circuit and has little influence on the precision of the original circuit, the accumulated output values of two adjacent times of the advanced digital-analog domain accumulator are extremely close, then the accumulated output values are subjected to polarity switching operation, so that the bus voltage change caused by the two times is reversed, and the positive feedback capacitor offsets the influence of parasitic capacitor on the stored charge and the transferred charge in the holding stage.
The high-level digital TDI analog domain circuit capable of eliminating parasitic effects alternately uses upper and lower electrode plates of a storage capacitor CH for charging and introduces a positive feedback capacitor Cb, and is suitable for the analog domain realization circuit of a high-level CMOS-TDI image sensor. The output voltage of the pixel unit is alternately charged to an upper polar plate and a lower polar plate by introducing polarity switching switches L1 and L2, and meanwhile, in order to ensure that the charge in the capacitor CH cannot be offset by the input after the polarity is switched, the upper polar plate and the lower polar plate switching switches of the capacitor CH are added, and the output of the operational amplifier is switched between high voltage and low voltage through the control of the switches; the positive feedback capacitor Cb is introduced in the holding stage to offset the loss of the parasitic capacitor to the transferred charge, and the parasitic influence of the sampling stage and the holding stage in the analog domain accumulation process is eliminated by the method, so that the accumulation precision of the TDI circuit in the analog domain is greatly improved.
Claims (6)
1. The high-level digital TDI analog domain circuit capable of eliminating parasitic effect is characterized in that: the full-differential operational amplifier circuit comprises a full-differential operational amplifier OPA, wherein positive and negative electrode VIN interfaces of the full-differential operational amplifier OPA are respectively connected with a sampling capacitor CS, reversing switches L1 are arranged between the full-differential operational amplifier OPA and the sampling capacitor CS, the two reversing switches L1 are also connected through two reversing switches L2, a switch I is arranged between a positive feedback capacitor Cb and an input bus, and switches I' and I are respectively arranged at the positive and negative output ends of the positive feedback capacitor Cb; one of the sampling capacitors CS is connected with a reference voltage VREF, the other sampling capacitor CS is connected with a pixel unit, and a positive electrode VIN interface and a negative electrode VIN interface of the full-differential operational amplifier OPA are respectively connected with a plurality of capacitor CH upper and lower pole plate switching circuits which are connected in parallel.
2. The high-level digital TDI analog domain circuit for eliminating parasitic effects of claim 1, wherein: every polar plate switching circuit includes the electric capacity CHi that is connected with the full differential op a on capacitor CH, and electric capacity CHi one end is connected switch Iii and switch Ki respectively, and the electric capacity CHi other end is connected switch Ii and switch Kii respectively, and switch Iii and switch Kii all with the negative pole VIN interface or the anodal VIN interface connection of full differential op a, switch Ki and switch Ii all with the anodal VOUT interface or the negative pole VOUT interface connection of full differential op a, i1, 2.
3. The high-level digital TDI analog domain circuit for eliminating parasitic effects of claim 2, wherein: one end of the positive feedback capacitor Cb is connected with the switch I, the other end of the positive feedback capacitor Cb is connected with the I ' and the I, one end of the switch I is connected with the input bus, the other end of the switch I is connected with the positive feedback capacitor Cb, one end of the I is connected with the Cb, the other end of the I is connected with the output bus on the other side, one end of the switch I ' is connected with the positive feedback capacitor Cb, and one end of the switch I ' is connected with the output bus on the side.
4. The method of claim 3, wherein the method comprises: the method specifically comprises the following steps:
step 1, performing accumulation operation of normal polarity once by an analog domain accumulator;
step 2, the analog domain accumulator carries out an accumulation operation with opposite polarity, and the parasitic effect influence of the previous accumulation operation is counteracted;
step 3, taking the two accumulation periods as a large accumulation period, accumulating enough corresponding stages and outputting;
and 4, refreshing the output hold capacitor CHi in the next accumulation period and repeating the accumulation processes of the steps 1 to 3.
5. The method of claim 4, wherein the method comprises: the specific process of the step 1 is as follows:
in the conducting period of the reversing switch L1, when the charge is sampled at the phase, the pixel unit outputs Vrst, at the moment, the circuit is in a unit gain state, the common-mode voltage VCM is input and output, and switches at two ends of the capacitor CHi are in a turn-off state; the switch I is conducted with the switch I', and the internal charge of the positive feedback capacitor Cb is refreshed; in the charge holding phase, the switch Iii is turned on simultaneously with the switch Ii, the input voltage is the pixel cell output Vsig, the switches I and I are turned on, and since the fully differential positive and negative output voltages are symmetric about VCM, when the positive feedback capacitance Cb and the parasitic total capacitance Cptotal are equal, the effect on the stored charge and the transferred charge is cancelled, the switch Iii is turned off first, the switch Ii is turned off later, and until the sampling phase of the next cycle, the differential output value of the output bus is lowered from Vo1 to VCM-VCM equal to 0, and the voltage change is coupled into the holding capacitance CH.
6. The method of claim 5, wherein the method comprises: the specific process of the step 2 is as follows: in the period that the reversing switch L2 is turned on, the output of the pixel unit is connected with the positive terminal of the fully differential operational amplifier OPA, the switch Ki and the switch Kii are turned on simultaneously, the switch Kii is turned off firstly, the switch Ki is turned off later, and the differential output value of the output bus in the period rises from Vo2 to 0.
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