CN105763198A - Integrator gain multiplying circuit in modulator - Google Patents
Integrator gain multiplying circuit in modulator Download PDFInfo
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- CN105763198A CN105763198A CN201610101666.5A CN201610101666A CN105763198A CN 105763198 A CN105763198 A CN 105763198A CN 201610101666 A CN201610101666 A CN 201610101666A CN 105763198 A CN105763198 A CN 105763198A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
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Abstract
The invention discloses an integrator gain multiplying circuit in a modulator. The circuit comprises two sampling capacitors, two integrating capacitors, an operational amplifier circuit, and a plurality of sampling and integrating switches. The sampling resistors are respectively a positive end signal sampling capacitor and a negative end signal sampling capacitor. The integrating capacitors are respectively a positive end integrating capacitor and a negative end integrating capacitor. According to the integrator gain multiplying circuit in a modulator, gain is achieved for the input signal and reference voltage through the same group of sampling resistors, so that the area of a switched capacitor circuit is reduced, and the manufacture cost of the switched capacitor circuit is reduced.
Description
Technical field
The present invention relates to electronic circuit, particularly to the integrator circuit that switched-capacitor circuit realizes.
Background technology
Switched-capacitor circuit is widely used in sigma delta analog-digital converter (sigma-deltaADC), as its integrator.Sigma delta analog-digital converter is proportion measurement, and the input signal being about to simulation is multiplied by gain A, is converted to the analog-digital conversion process of the digital signal of n-bit with the ratio of the reference voltage of simulation.In the past, it is used in switched-capacitor circuit and realizes gain and have employed the input signal of simulation and reference voltage and adopt electric capacity respectively through one group, which increase the area of switched-capacitor circuit.
The switched-capacitor integrator based on levitation current supplies gain bootstrap phase inverter as described by patent application 201410847785.6, this invention integrator is divided into sample phase and integration phase, sample phase circuit is by ten metal-oxide-semiconductors of M1-M10 and sampling capacitance Cs, integrating capacitor CI, upper and lower two holding capacitor Cc, S1 composition is switched with one, wherein M1 to M1, M3, M5, M7, M9 are PMOS, M2, M4, M6, M8, M10 are PMOS, sampling capacitance CS, integrating capacitor CI and upper and lower two holding capacitor Cc are divided into the two poles of the earth A, B.But, in this patent application, constituted phase inverter with metal-oxide-semiconductor and capacitor combination, thus replacing operational amplifier, the problem that still can not solve to add the area of switched-capacitor circuit.
Summary of the invention
For solving the problems referred to above, it is an object of the invention to provide the integrator gain multiple circuit in a kind of manipulator, input signal and reference voltage that the present invention can simulate share one group of sampling capacitance and realize gain.
Further object is that the integrator gain multiple circuit provided in a kind of manipulator, this circuit can reduce the area of switched-capacitor circuit, reduces the cost of manufacture of switched-capacitor circuit.
For achieving the above object, technical scheme is as follows.
Integrator gain multiple circuit in a kind of manipulator, this circuit includes 2 sampling capacitances, 2 integrating capacitors, 1 discharge circuit, and some (a plurality of) sample and integral restrictor；Sampling capacitance has anode signal sampling electric capacity and each one of negative terminal signal sampling electric capacity, and wherein the top crown of anode signal sampling electric capacity connects 21,23 switches, and the bottom crown of anode signal sampling electric capacity connects 11,13,15,17 switches；The top crown of negative terminal signal sampling electric capacity connects 22,24 switches, and the bottom crown of negative terminal signal sampling electric capacity connects 12,14,16,18 switches；The other end of 11 switches connects the anode Vip of input signal, 13, the other end of 14 switches connects integrator common-mode voltage VCM, the other end of 12 switches connects the negative terminal Vin of input signal, 15, the other end of 18 switches connects the anode REFP of reference voltage, 16, the other end of 17 switches connects the negative terminal REFN of reference voltage, and the other end of 21,22 switches connects integrator common-mode voltage VCM；
Integrating capacitor has anode integrating capacitor and each one of negative terminal integrating capacitor, and wherein the top crown of anode integrating capacitor connects the positive input terminal of the other end of 23 switches, amplifier, and the bottom crown of anode integrating capacitor connects the negative output terminal of integrator positive output end Vop, amplifier；The top crown of negative terminal integrating capacitor connects the negative input end of the other end of 24 switches, amplifier, and the bottom crown of negative terminal integrating capacitor connects the positive output end of integrator negative output terminal Von, 30 amplifiers.
Additionally, switch is by 5 non-overlapping clocks, control including Ф 1, Ф 2, Ф 2p, Ф 2n, Ф 2c, within an integrator cycle, the sample integration of m analog input signal is completed by Ф 1, Ф 2, tri-clocks of Ф 2c, the sample integration of n analog input signal and reference voltage is simultaneously completed by Ф 1, Ф 2, Ф 2p or tri-clocks of Ф 2n, the feedback signal that wherein Ф 2p represents in sigma delta modulator is timing, when Ф 2n representative feedback signal in sigma delta modulator is negative.
Described non-overlapping clock, wherein, Ф 1 controls switch 11,12,21,22, Ф 2 and controls switch 23,24, Ф 2p control switch 17,18, Ф 2n control switch 15,16, Ф 2c control switch 13,14.
Described switch can be switched by single PMOS or NMOS tube, CMOS tube etc. and realize.
Integrator gain multiple circuit in the manipulator that the present invention realizes, shares one group of sampling capacitance by input signal and reference voltage and realizes gain, it is possible to reduce the area of switched-capacitor circuit, reduce the cost of manufacture of switched-capacitor circuit.
Accompanying drawing explanation
Fig. 1 is the integrator circuit realizing gain doubling technology of the present invention.
Fig. 2 is each phase place explanation controlling switch clock used in the integrator circuit realizing gain doubling technology of the present invention.
Fig. 3 is Fig. 3 of the present invention is the structural representation of application example using cmos switch.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein is only in order to explain the present invention, is not intended to limit the present invention.
Refer to shown in Fig. 1, be the circuit of the fully differential signal input and output realizing gain doubling technology of the present invention.In Fig. 1, this circuit includes: sampling capacitance 31,32, operational amplifier 30, integrating capacitor 33,34, switchs 11,12,13,14,15,16,17,18,21,22,23,24.
According to the present invention, this switched-capacitor circuit includes 2 sampling capacitances, 2 integrating capacitors, 1 discharge circuit, some samplings and integral restrictor.Sampling capacitance is divided into 31 anode signal sampling electric capacity and each one of 32 negative terminal signal sampling electric capacity.Wherein the top crown of 31 anode signal sampling electric capacity connects 21,23 switches, and the bottom crown of 31 anode signal sampling electric capacity connects 11,13,15,17 switches；The top crown of 32 negative terminal signal sampling electric capacity connects 22,24 switches, and the bottom crown of 32 negative terminal signal sampling electric capacity connects 12,14,16,18 switches.The other end of 11 switches connects the anode Vip of input signal, 13, the other end of 14 switches connects integrator common-mode voltage VCM, the other end of 12 switches connects the negative terminal Vin of input signal, 15, the other end of 18 switches connects the anode REFP of reference voltage, 16, the other end of 17 switches connects the negative terminal REFN of reference voltage, and the other end of 21,22 switches connects integrator common-mode voltage VCM.
Integrating capacitor is divided into 33 anode integrating capacitors and each one of 34 negative terminal integrating capacitors.Wherein the top crown of 33 anode integrating capacitors connects the positive input terminal of the other end of 23 switches, 30 amplifiers, and the bottom crown of 33 anode integrating capacitors connects the negative output terminal of integrator positive output end Vop, 30 amplifiers；The top crown of 34 negative terminal integrating capacitors connects the negative input end of the other end of 24 switches, 30 amplifiers, and the bottom crown of 34 negative terminal integrating capacitors connects the positive output end of integrator negative output terminal Von, 30 amplifiers.
It addition, switch is controlled by 5 non-overlapping clocks, including Ф 1, Ф 2, Ф 2p, Ф 2n, Ф 2c, such as Fig. 2.Within an integrator cycle, completed the sample integration of m analog input signal by Ф 1, Ф 2, tri-clocks of Ф 2c, simultaneously completed the sample integration of n analog input signal and reference voltage by Ф 1, Ф 2, Ф 2p or tri-clocks of Ф 2n.[1] feedback signal that Ф 2p represents in sigma delta modulator is timing, when [2] Ф 2n representative feedback signal in sigma delta modulator is negative.
The gain that integrator finally realizes is (m+n)/n.
Each phase clock of integrator circuit breaker in middle illustrates, as follows:
Clock ф 1 phaseswitch 11,12,21,22 is opened.
Clock ф 2 phaseswitch 23,24 is opened.
Clock ф 2c phaseswitch 13,14 is opened.
Clock ф 2p phaseswitch 15,16 is opened.
Clock ф 2n phaseswitch 17,18 is opened.
Within an integrator cycle, completed the sample integration of m analog input signal by Ф 1, Ф 2, tri-clocks of Ф 2c, simultaneously completed the sample integration of n analog input signal and reference voltage by Ф 1, Ф 2, Ф 2p or tri-clocks of Ф 2n.[1] feedback signal that Ф 2p represents in sigma delta modulator is timing, when [2] Ф 2n representative feedback signal in sigma delta modulator is negative.
Integrator to realize process as follows:
Within an integrator cycle:
Analog input signal is sampled: ф 1 phase place: sampling switch 11,12,21,22 is opened, and analog input signal is sampled by sampling capacitance.
The analog input signal of sampling is integrated by analog input signal integration: ф 2, ф 2c phase place: integral restrictor 13,14,23,24 is opened, sampling capacitance and integrating capacitor.
Operation more than repeating (Repeated m is secondary altogether within an integrator cycle for analog input signal sampling and this process of analog input signal integration).
Analog input signal is sampled: ф 1 phase place: sampling switch 11,12,21,22 is opened, and analog input signal is sampled by sampling capacitance.
Being simulated input signal and reference voltage integration: ф 2, ф 2p or ф 2n phase place: integral restrictor 15 or 17,16 or 18,23,24 open, the reference voltage of sampling is integrated by sampling capacitance and integrating capacitor simultaneously.
Repeat above content (be simulated input signal and reference voltage sampling simultaneously and this process of integration repeats n time altogether within an integrator cycle).
Shown in Fig. 3, being be circuit diagram during CMOS tube by the switch application in Fig. 1, wherein, CMOS tube can also sample PMOS or NMOS tube substitutes.
In a word, the present invention utilizes the integrator gain multiple circuit in the manipulator that combinations thereof completes, utilization in conjunction with switch, input signal and reference voltage are shared one group of sampling capacitance and realizes gain, sampling capacitance can be made full use of, reduce the area of switched-capacitor circuit, reduce the cost of manufacture of switched-capacitor circuit.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all any amendment, equivalent replacement and improvement etc. made within the spirit and principles in the present invention, should be included within protection scope of the present invention.
Claims (4)
1. the integrator gain multiple circuit in a manipulator, it is characterised in that this circuit includes 2 sampling capacitances, 2 integrating capacitors, 1 discharge circuit, some samplings and integral restrictor；
Sampling capacitance has anode signal sampling electric capacity and each one of negative terminal signal sampling electric capacity, and wherein the top crown of anode signal sampling electric capacity connects 21,23 switches, and the bottom crown of anode signal sampling electric capacity connects 11,13,15,17 switches；The top crown of negative terminal signal sampling electric capacity connects 22,24 switches, and the bottom crown of negative terminal signal sampling electric capacity connects 12,14,16,18 switches；The other end of 11 switches connects the anode Vip of input signal, 13, the other end of 14 switches connects integrator common-mode voltage VCM, the other end of 12 switches connects the negative terminal Vin of input signal, 15, the other end of 18 switches connects the anode REFP of reference voltage, 16, the other end of 17 switches connects the negative terminal REFN of reference voltage, and the other end of 21,22 switches connects integrator common-mode voltage VCM；
Integrating capacitor has anode integrating capacitor and each one of negative terminal integrating capacitor, and wherein the top crown of anode integrating capacitor connects the positive input terminal of the other end of 23 switches, amplifier, and the bottom crown of anode integrating capacitor connects the negative output terminal of integrator positive output end Vop, amplifier；The top crown of negative terminal integrating capacitor connects the negative input end of the other end of 24 switches, amplifier, and the bottom crown of negative terminal integrating capacitor connects the positive output end of integrator negative output terminal Von, 30 amplifiers.
2. the integrator gain multiple circuit in manipulator as claimed in claim 1, it is characterized in that described switch is by 5 non-overlapping clock Ф 1, Ф 2, Ф 2p, Ф 2n, Ф 2c controls, within an integrator cycle, by Ф 1, Ф 2, tri-clocks of Ф 2c complete the sample integration of m analog input signal, by Ф 1, Ф 2, Ф 2p or tri-clocks of Ф 2n simultaneously complete the sample integration of n analog input signal and reference voltage, the feedback signal that wherein Ф 2p represents in sigma delta modulator is timing, when Ф 2n representative feedback signal in sigma delta modulator is negative.
3. the integrator gain multiple circuit in manipulator as claimed in claim 1, it is characterised in that described switch can be realized by single PMOS or NMOS tube, CMOS tube switch.
4. the integrator gain multiple circuit in manipulator as claimed in claim 2, it is characterised in that described non-overlapping clock, wherein, Ф 1 controls switch 11,12,21,22, Ф 2 and controls switch 23,24, Ф 2p control switch 17,18, Ф 2n controls switch 15,16, Ф 2c and controls switch 13,14.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610101666.5A CN105763198A (en) | 2016-02-24 | 2016-02-24 | Integrator gain multiplying circuit in modulator |
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| CN201610101666.5A CN105763198A (en) | 2016-02-24 | 2016-02-24 | Integrator gain multiplying circuit in modulator |
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| CN105763198A true CN105763198A (en) | 2016-07-13 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112911176A (en) * | 2021-01-19 | 2021-06-04 | 西安理工大学 | Advanced digital-analog-domain TDI circuit for inhibiting parasitic effect and implementation method |
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| US5220286A (en) * | 1991-06-28 | 1993-06-15 | International Business Machines Corporation | Single ended to fully differential converters |
| US6204787B1 (en) * | 1999-03-31 | 2001-03-20 | Cirrus Logic, Inc. | Circuits and methods for gain ranging in an analog modulator and systems using the same |
| CN101625718A (en) * | 2009-06-19 | 2010-01-13 | 复旦大学 | Double sampling integrator |
| CN101834606A (en) * | 2009-03-09 | 2010-09-15 | 复旦大学 | Front-end sampling hold and margin amplification circuit of analog-to-digital converter |
| CN102916703A (en) * | 2012-11-06 | 2013-02-06 | 长沙景嘉微电子股份有限公司 | 1-bit digital-to-analogue conversion and switch capacitor filtering circuit |
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2016
- 2016-02-24 CN CN201610101666.5A patent/CN105763198A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5220286A (en) * | 1991-06-28 | 1993-06-15 | International Business Machines Corporation | Single ended to fully differential converters |
| US6204787B1 (en) * | 1999-03-31 | 2001-03-20 | Cirrus Logic, Inc. | Circuits and methods for gain ranging in an analog modulator and systems using the same |
| CN101834606A (en) * | 2009-03-09 | 2010-09-15 | 复旦大学 | Front-end sampling hold and margin amplification circuit of analog-to-digital converter |
| CN101625718A (en) * | 2009-06-19 | 2010-01-13 | 复旦大学 | Double sampling integrator |
| CN102916703A (en) * | 2012-11-06 | 2013-02-06 | 长沙景嘉微电子股份有限公司 | 1-bit digital-to-analogue conversion and switch capacitor filtering circuit |
Non-Patent Citations (1)
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| 郭小梅: "18位级联Delta_Sigma_ADC的设计", 《中国优秀硕士学位论文全文数据库信息科技辑》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112911176A (en) * | 2021-01-19 | 2021-06-04 | 西安理工大学 | Advanced digital-analog-domain TDI circuit for inhibiting parasitic effect and implementation method |
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Application publication date: 20160713 |
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