CN105811989A - Integrator gain multiplication circuit applied to sigma-delta modulator - Google Patents
Integrator gain multiplication circuit applied to sigma-delta modulator Download PDFInfo
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- CN105811989A CN105811989A CN201610102356.5A CN201610102356A CN105811989A CN 105811989 A CN105811989 A CN 105811989A CN 201610102356 A CN201610102356 A CN 201610102356A CN 105811989 A CN105811989 A CN 105811989A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
- H03M3/478—Means for controlling the correspondence between the range of the input signal and the range of signals the converter can handle; Means for out-of-range indication
- H03M3/48—Means for controlling the correspondence between the range of the input signal and the range of signals the converter can handle; Means for out-of-range indication characterised by the type of range control, e.g. limiting
- H03M3/482—Means for controlling the correspondence between the range of the input signal and the range of signals the converter can handle; Means for out-of-range indication characterised by the type of range control, e.g. limiting by adapting the quantisation step size
- H03M3/484—Means for controlling the correspondence between the range of the input signal and the range of signals the converter can handle; Means for out-of-range indication characterised by the type of range control, e.g. limiting by adapting the quantisation step size by adapting the gain of the feedback signal, e.g. by adapting the reference values of the digital/analogue converter in the feedback path
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- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Filters That Use Time-Delay Elements (AREA)
Abstract
The invention discloses an integrator gain multiplication circuit applied to a sigma-delta modulator. The circuit comprises two sampling capacitors, two integrating capacitors, one operational amplifier circuit and a plurality of sampling and integration switches, wherein the sampling capacitors include one positive-end signal sampling capacitor and one negative-end signal sampling capacitor and the integrating capacitors include one positive-end integrating capacitor and one negative-end integrating capacitor. According to the realized integrator circuit, input signals and reference voltages realize gain by sharing one sampling capacitor, the area of a switch capacitor circuit is can be reduced, and the manufacturing cost of the switch capacitor circuit is decreased.
Description
Technical field
The present invention relates to electronic circuit, particularly to the integrator circuit that switched-capacitor circuit realizes.
Background technology
Switched-capacitor circuit is widely used in sigma delta analog-digital converter (sigma-deltaADC), as its integrator.Sigma delta analog-digital converter is proportion measurement, and the input signal being about to simulation is multiplied by gain A, is converted to the analog-digital conversion process of the digital signal of n-bit with the ratio of the reference voltage of simulation.In the past, it is used in switched-capacitor circuit and realizes gain and have employed the input signal of simulation and reference voltage and adopt electric capacity respectively through one group, which increase the area of switched-capacitor circuit.
The switched-capacitor integrator based on levitation current supplies gain bootstrap phase inverter as described by patent application 201410847785.6, this invention integrator is divided into sample phase and integration phase, sample phase circuit is by ten metal-oxide-semiconductors of M1-M10 and sampling capacitance Cs, integrating capacitor CI, upper and lower two holding capacitor Cc, S1 composition is switched with one, wherein M1 to M1, M3, M5, M7, M9 are PMOS, M2, M4, M6, M8, M10 are PMOS, sampling capacitance CS, integrating capacitor CI and upper and lower two holding capacitor Cc are divided into the two poles of the earth A, B.But, in this patent application, constituted phase inverter with metal-oxide-semiconductor and capacitor combination, thus replacing operational amplifier, the problem that still can not solve to add the area of switched-capacitor circuit.
Summary of the invention
For solving the problems referred to above, it is an object of the invention to provide a kind of integrator gain multiple circuit being applied in sigma delta modulator, input signal and reference voltage that the present invention can simulate share one group of sampling capacitance and realize storage gain.
Further object is that a kind of integrator gain multiple circuit being applied in sigma delta modulator of offer, this circuit can reduce the area of switched-capacitor circuit, reduces the cost of manufacture of switched-capacitor circuit.
For achieving the above object, technical scheme is as follows.
A kind of integrator gain multiple circuit being applied in sigma delta modulator, this circuit includes 2 sampling capacitances, 2 integrating capacitors, 1 discharge circuit, and some (a plurality of) sample and integral restrictor；
Sampling capacitance has anode signal sampling electric capacity and each one of negative terminal signal sampling electric capacity, and wherein the top crown of anode signal sampling electric capacity connects 21,23 switches, and the bottom crown of anode signal sampling electric capacity connects 11,13,15,17 switches；The top crown of negative terminal signal sampling electric capacity connects 22,24 switches, and the bottom crown of negative terminal signal sampling electric capacity connects 12,14,16,18 switches；11, the other end of 14 switches connects the anode Vip of input signal, 12, the other end of 13 switches connects the negative terminal Vin of input signal, 15, the other end of 18 switches connects the anode REFP of reference voltage, 16, the other end of 17 switches connects the negative terminal REFN of reference voltage, and the other end of 21,22 switches connects integrator common-mode voltage VCM；
Integrating capacitor has anode integrating capacitor and each one of negative terminal integrating capacitor, and wherein the top crown of anode integrating capacitor connects the positive input terminal of the other end of 23 switches, amplifier, and the bottom crown of anode integrating capacitor connects the negative output terminal of integrator positive output end Vop, amplifier；The top crown of negative terminal integrating capacitor connects the negative input end of the other end of 24 switches, amplifier, and the bottom crown of negative terminal integrating capacitor connects the positive output end of integrator negative output terminal Von, 30 amplifiers.
Additionally, switch is controlled by 3 groups of non-overlapping clocks, three groups of non-overlapping clocks are Ф 1 and Ф 2, Ф 1s and Ф 2s, Ф 1f and Ф 2f respectively, the clock cycle of Ф 1 and Ф 2 is T, the integrator cycle relative to sigma delta modulator, namely the cycle completing a gain integration is (m+n) * T, and the gain that integrator finally realizes is m/n.Specifically, each integrator cycle has needed the sample integration of m analog input signal and the sample integration of n reference voltage.
Described non-overlapping clock, wherein, Ф 1 controls switch 21,22, Ф 2 and controls switch 23,24, Ф 1s control switch 11,12, Ф 2s control switch 13,14, Ф 1f control switch 15,16, Ф 2f control switch 17,18.
Described switch can be switched by single PMOS or NMOS tube, CMOS tube etc. and realize.
The integrator circuit (being namely applied in the integrator gain multiple circuit in sigma delta modulator) that the present invention realizes, input signal and reference voltage are shared one group of sampling capacitance and realizes gain, the area of switched-capacitor circuit can be reduced, reduce the cost of manufacture of switched-capacitor circuit.
Accompanying drawing explanation
Fig. 1 is the integrator circuit realizing gain doubling technology of the present invention.
Fig. 2 is each phase place explanation controlling switch clock used in the integrator circuit realizing gain doubling technology of the present invention.
Fig. 3 is Fig. 3 of the present invention is the structural representation of application example using cmos switch.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein is only in order to explain the present invention, is not intended to limit the present invention.
Refer to shown in Fig. 1, Fig. 1 represents according to the integrator circuit realizing gain doubling technology stated.In Fig. 1, the integrator circuit realizing gain doubling technology is used to include: sampling capacitance 31,32, operational amplifier 30, integrating capacitor 33,34, switch 11,12,13,14,15,16,17,18,21,22,23,24.
Wherein, this circuit includes 2 sampling capacitances, 2 integrating capacitors, 1 discharge circuit, some samplings and integral restrictor.Sampling capacitance is divided into 31 anode signal sampling electric capacity and each one of 32 negative terminal signal sampling electric capacity.Wherein the top crown of 31 anode signal sampling electric capacity connects 21,23 switches, and the bottom crown of 31 anode signal sampling electric capacity connects 11,13,15,17 switches；The top crown of 32 negative terminal signal sampling electric capacity connects 22,24 switches, and the bottom crown of 32 negative terminal signal sampling electric capacity connects 12,14,16,18 switches.11, the other end of 14 switches connects the anode Vip of input signal, 12, the other end of 13 switches connects the negative terminal Vin of input signal, 15, the other end of 18 switches connects the anode REFP of reference voltage, 16, the other end of 17 switches connects the negative terminal REFN of reference voltage, and the other end of 21,22 switches connects integrator common-mode voltage VCM.Integrating capacitor is divided into 33 anode integrating capacitors and each one of 34 negative terminal integrating capacitors.Wherein the top crown of 33 anode integrating capacitors connects the positive input terminal of the other end of 23 switches, 30 amplifiers, and the bottom crown of 33 anode integrating capacitors connects the negative output terminal of integrator positive output end Vop, 30 amplifiers；The top crown of 34 negative terminal integrating capacitors connects the negative input end of the other end of 24 switches, 30 amplifiers, and the bottom crown of 34 negative terminal integrating capacitors connects the positive output end of integrator negative output terminal Von, 30 amplifiers.
It addition, switch is controlled by 3 groups of non-overlapping clocks, including Ф 1 and Ф 2, Ф 1s and Ф 2s, Ф 1f and Ф 2f, as shown in Figure 2.The clock cycle of Ф 1 and Ф 2 is T, and relative to the integrator cycle of sigma delta modulator, the cycle namely completing a gain integration is (m+n) * T.Specifically, each integrator cycle has needed the sample integration of m analog input signal and the sample integration of n reference voltage.[1] feedback signal that Ф 1f, Ф 2f represent in sigma delta modulator is timing, when [2] Ф 1f, Ф 2f representative feedback signal in sigma delta modulator is negative.
The gain that integrator finally realizes is m/n.
Fig. 2 represents that each phase clock of integrator circuit breaker in middle illustrates, as follows:
Clock ф 1 phaseswitch 21,22 is opened.
Clock ф 2 phaseswitch 23,24 is opened.
Clock ф 1s phaseswitch 11,12 is opened.
Clock ф 2s phaseswitch 13,14 is opened.
Clock ф 1f phaseswitch 15,16 is opened.
Clock ф 2f phaseswitch 17,18 is opened.
The connection of switched-capacitor circuit is as follows:
Integrator to realize process as follows:
Within an integrator cycle:
Analog input signal is sampled: ф 1& ф 1s phase place: sampling switch 11,12,21,22 is opened, and analog input signal is sampled by sampling capacitance.
Analog input signal integration: the analog input signal of sampling is integrated by ф 2& ф 2s phase place: integral restrictor 13,14,23,24 is opened, sampling capacitance and integrating capacitor.
Repeat foregoing (Repeated m is secondary altogether within an integrator cycle for analog input signal sampling and this process of analog input signal integration).
Reference voltage is sampled: ф 1& ф 1f phase place: sampling switch 15,16,21,22 is opened, and reference voltage is sampled by sampling capacitance.
Reference voltage integration: the reference voltage of sampling is integrated by ф 2& ф 2f phase place: integral restrictor 17,18,23,24 is opened, sampling capacitance and integrating capacitor.
Repeat foregoing (reference voltage sampling and this process of reference voltage integration repeat n time altogether within an integrator cycle).
Shown in Fig. 3, being be circuit diagram during CMOS tube by the switch application in Fig. 1, wherein, CMOS tube can also sample PMOS or NMOS tube substitutes.
In a word, the present invention utilizes what combinations thereof completed integrator circuit, in conjunction with the utilization of switch, input signal and reference voltage are shared one group of sampling capacitance and realizes gain, sampling capacitance can be made full use of, reduce the area of switched-capacitor circuit, reduce the cost of manufacture of switched-capacitor circuit.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all any amendment, equivalent replacement and improvement etc. made within the spirit and principles in the present invention, should be included within protection scope of the present invention.
Claims (4)
1. the integrator gain multiple circuit that a kind is applied in sigma delta modulator, it is characterised in that this circuit includes 2 sampling capacitances, 2 integrating capacitors, 1 discharge circuit, some samplings and integral restrictor；
Sampling capacitance has anode signal sampling electric capacity and each one of negative terminal signal sampling electric capacity, and wherein the top crown of anode signal sampling electric capacity connects 21,23 switches, and the bottom crown of anode signal sampling electric capacity connects 11,13,15,17 switches；The top crown of negative terminal signal sampling electric capacity connects 22,24 switches, and the bottom crown of negative terminal signal sampling electric capacity connects 12,14,16,18 switches；11, the other end of 14 switches connects the anode Vip of input signal, 12, the other end of 13 switches connects the negative terminal Vin of input signal, 15, the other end of 18 switches connects the anode REFP of reference voltage, 16, the other end of 17 switches connects the negative terminal REFN of reference voltage, and the other end of 21,22 switches connects integrator common-mode voltage VCM；
Integrating capacitor has anode integrating capacitor and each one of negative terminal integrating capacitor, and wherein the top crown of anode integrating capacitor connects the positive input terminal of the other end of 23 switches, amplifier, and the bottom crown of anode integrating capacitor connects the negative output terminal of integrator positive output end Vop, amplifier；The top crown of negative terminal integrating capacitor connects the negative input end of the other end of 24 switches, amplifier, and the bottom crown of negative terminal integrating capacitor connects the positive output end of integrator negative output terminal Von, 30 amplifiers.
2. it is applied in the integrator gain multiple circuit in sigma delta modulator as claimed in claim 1, it is characterized in that described switch is controlled by 3 groups of non-overlapping clocks, three groups of non-overlapping clocks are Ф 1 and Ф 2, Ф 1s and Ф 2s, Ф 1f and Ф 2f respectively.
3. it is applied in the integrator gain multiple circuit in sigma delta modulator as claimed in claim 2, it is characterized in that described non-overlapping clock, wherein, Ф 1 controls switch 21,22, Ф 2 controls switch 23,24, Ф 1s and controls switch 11,12, Ф 2s control switch 13,14, Ф 1f controls switch 15,16, Ф 2f and controls switch 17,18.
4. it is applied in the integrator gain multiple circuit in sigma delta modulator as claimed in claim 1, it is characterised in that described switch can be switched by single PMOS or NMOS tube, CMOS tube etc. and realize.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610102356.5A CN105811989A (en) | 2016-02-24 | 2016-02-24 | Integrator gain multiplication circuit applied to sigma-delta modulator |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610102356.5A CN105811989A (en) | 2016-02-24 | 2016-02-24 | Integrator gain multiplication circuit applied to sigma-delta modulator |
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| CN105811989A true CN105811989A (en) | 2016-07-27 |
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| CN201610102356.5A Pending CN105811989A (en) | 2016-02-24 | 2016-02-24 | Integrator gain multiplication circuit applied to sigma-delta modulator |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111462664A (en) * | 2019-01-21 | 2020-07-28 | 联咏科技股份有限公司 | Sensing circuit and sampling hold circuit of organic light emitting diode driving device |
Citations (4)
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|---|---|---|---|---|
| US6147522A (en) * | 1998-12-31 | 2000-11-14 | Cirrus Logic, Inc. | Reference voltage circuitry for use in switched-capacitor applications |
| US6204787B1 (en) * | 1999-03-31 | 2001-03-20 | Cirrus Logic, Inc. | Circuits and methods for gain ranging in an analog modulator and systems using the same |
| CN104253614A (en) * | 2014-09-19 | 2014-12-31 | 陕西高新实业有限公司 | Switched capacitor integrator with sampling holding function |
| CN104272590A (en) * | 2012-05-03 | 2015-01-07 | 美国亚德诺半导体公司 | Programmable gain amplifier with common mode sampling |
-
2016
- 2016-02-24 CN CN201610102356.5A patent/CN105811989A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6147522A (en) * | 1998-12-31 | 2000-11-14 | Cirrus Logic, Inc. | Reference voltage circuitry for use in switched-capacitor applications |
| US6204787B1 (en) * | 1999-03-31 | 2001-03-20 | Cirrus Logic, Inc. | Circuits and methods for gain ranging in an analog modulator and systems using the same |
| CN104272590A (en) * | 2012-05-03 | 2015-01-07 | 美国亚德诺半导体公司 | Programmable gain amplifier with common mode sampling |
| CN104253614A (en) * | 2014-09-19 | 2014-12-31 | 陕西高新实业有限公司 | Switched capacitor integrator with sampling holding function |
Non-Patent Citations (1)
| Title |
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| 郭小梅: "18位级联Delta_Sigma_ADC的设计", 《中国优秀硕士学位论文全文数据库信息科技辑》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111462664A (en) * | 2019-01-21 | 2020-07-28 | 联咏科技股份有限公司 | Sensing circuit and sampling hold circuit of organic light emitting diode driving device |
| CN111462664B (en) * | 2019-01-21 | 2024-03-08 | 联咏科技股份有限公司 | Sensing circuit and sample hold circuit of organic light emitting diode driving device |
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