CA2364309A1 - A system for improved digital-to-analog data conversion - Google Patents
A system for improved digital-to-analog data conversion Download PDFInfo
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- CA2364309A1 CA2364309A1 CA 2364309 CA2364309A CA2364309A1 CA 2364309 A1 CA2364309 A1 CA 2364309A1 CA 2364309 CA2364309 CA 2364309 CA 2364309 A CA2364309 A CA 2364309A CA 2364309 A1 CA2364309 A1 CA 2364309A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/72—Sequential conversion in series-connected stages
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Abstract
A pipelined digital-to-analog converter (DAC) converts a digital input to an analog output. The pipelined DAC has a plurality of stages. A first of the plurality of stages is coupled to an initialization capacitor and ground. A remainder of the plurality of stages is coupled to a previous stage. Each of said plurality of stages comprises the following.
A capacitor having a first and second plate, the capacitor for receiving a charge at the first plate in accordance with an associated bit of the digital input. A
switch for coupling the first plate of said capacitor to ground when the capacitor is not receiving the charge.
A switch for coupling the second plate of the capacitor to ground when the capacitor is receiving the charge. Coupling the capacitor to ground reduces the effect of stray capacitance in the pipelined DAC.
A capacitor having a first and second plate, the capacitor for receiving a charge at the first plate in accordance with an associated bit of the digital input. A
switch for coupling the first plate of said capacitor to ground when the capacitor is not receiving the charge.
A switch for coupling the second plate of the capacitor to ground when the capacitor is receiving the charge. Coupling the capacitor to ground reduces the effect of stray capacitance in the pipelined DAC.
Description
A SYSTEM FOR IMPROVED DIGITAL-TO-ANALOG DATA CONVERSION
Priority is claimed from Canadian Patent Application No. 2,327,644. The present invention relates to an improved system for converting data from a digital form to an analog form.
BACKGROUND OF THE INVENTION
A digital to analog converter (DAC) is a device for generating an analog output, usually a voltage~or current, that is a representation of a sequence of bits at its input. For example, an 8-bit DAC outputs a voltage or current that can have one of 256 different values. So if 1o the output ranges from 0 to IOV, the DAC outputs a voltage corresponding to one of 256 voltage levels between 0 and 10. A number of techniques are used to implement this conversion.
One such technique is known as an algorithmic DAC, which is based on a step-by-step method. Generally, a multi-bit word, or digital input, is processed one portion at a time.
In each step, a partial result from the previous step is combined with a portion of the mufti-bit input word and then passed on to the next step. Figure 1 is a flow chart illustrating this basic algorithm, wherein the input word is processed one bit at a time, starting from the least significant bit. An interim value R is initialized to zero. A counter 2o n, used to count the number of bits processed, is also initialized to zero.
A loop commences wherein if a bit b" is 0, the interim value R is divided in half. If the bit bn is 1, the sum of the interim value R and a reference voltage V,efis divided in half. The value of the counter n is increased by one. The loop is repeated for the next more significant bit until n = N, where N is the total number of bits in the word input. At that 2s point, the interim value R represents an analog form of the word input.
Dividing R in half weights the digital bits according to their significance. That is, the least significant bit has the smallest impact on the outcome of the DAC since it will be divided more times than any of the other bits.
3o Although there are other algorithms available in the art, this technique is attractive because of the savings it offers in terms of circuit size and power. Two architectures that have been developed to implement this technique are the pipelined DAC and the cyclic DAC. The pipelined DAC provides operating speed at the expense of size and therefore, power. The cyclic DAC is more economical than the pipelined DAC since it reuses the same hardware for each iteration of the algorithm. However, the reduction in size of the cyclic DAC comes at the expense of a lower output rate. It is most suitable to implement algorithmic DACs using a switched-capacitor (SC) technique, however other techniques, such as switched-current (SI), can also be used.
Original SC pipelined DACs used an operational amplifier (op amp) in each stage for 1o performing the required operations, however this makes the DAC very expensive. Figure 2a illustrates a SC quasi-passive pipelined DAC (QPPDAC), represented generally by the numeral 10 that is described below. The DAC is referred to as quasi-passive because no op amps are used for performing the required operations. Rather, the DAC
essentially comprises capacitors and switches.
The QPPDAC circuit 10 includes a series of stages 12. Each stage 12 comprises a capacitor 14 and several switches. A first plate (herein referred to as the bottom plate for illustrative purposes only) of the capacitor 14 is coupled to ground. A second plate (herein referred to as the top plate for illustrative purposes only) of the capacitor 14 is 2o coupled to a reference voltage V,.efma a first switch 16 and to ground via a second switch 18. The top plate of the capacitor 14 is also coupled to the top plate of the capacitor in a previous stage via a third switch 20. For the first stage 12a, there is no previous stage for the top plate of the capacitor 14 to be coupled. Instead, the top plate of the capacitor 14 is coupled via the third switch 20 to the top plate of an initialization capacitor 22, and an initialization switch 24. The initialization capacitor 22 has the same capacitance as the remaining capacitors 14. Both the bottom plate of the initialization capacitor 22 and the other end of the initialization switch 24 are coupled to ground. For the final stage 12f, the capacitor 14f is further coupled to an output stage such as sample and hold (not shown).
The QPPDAC uses a three-phase clock for timing. A timing diagram for the clock is shown in figure 2b. The clock phases run continuously, that is, no reset cycle or the like ;
is necessary, and a portion of a new digital input word is taken in every clock cycle.
Also, the phases are staggered in time and do not overlap. Therefore, the DAC
can operate on N div 3 words at the same time, where N is the number of resolution bits of the DAC and the portion of the word taken in is three (3) bits in size.
Figure 3 provides an illustrative example as to how the bits are input into the QPPDAC, represented generally by the numeral 30. In this example, N = 9, so three numbers can be 1o converted at a time. In a first clock cycle, three bits from each of three words are input to the DAC 32. These bits are the least significant bits (LSB) of word 3, the middle 3 bits of word 2, and the most significant bits (MSB) of word 1. The less significant bits of word l and word 2 have already been converted in previous clock cycles. In the next clock cycle, the middle three bits of word 3, the MSB of word 2, and the LSB
of a new ~ 5 word, word 4, are converted. Lastly, in the next clock cycle, the MSB of word 3, the middle three bits of word four, and the LSB of a new word, word 5, are converted.
Therefore, after 3 clock cycles an entire 9-bit word is converted.
Referring once again to figure 2, b~~kJ represents the jth bit of the kth digital input word.
2o The conversion process for each word begins with the LSB. Depending on the bit value, either the first switch 16a So, I or the second switch 18a So,2 is closed during the first phase of the clock cycle, ~l. If the first switch 16a is closed, Co is charged to V,ef If the second switch 18a is closed, Co is grounded. Therefore, the voltage at Co can be represented as bo~mJ V,ef, where bo is 1 or 0. At the same time, the initiation switch 24 is closed and the 25 initiation capacitor 22 is discharged to ground. The third switch 20a remains open and closes only in the following clock phase.
In the second phase,, of the same clock cycle, the first 16a and second 18a switches in the first stage 12a are opened and the third switch 20a closes. CD shares its charge with 3o the initiation capacitor 22 through the third switch 20a. Since all the capacitors are matched, the voltage at Co is equal to:
VCp -~bO~m~Vref~~2.
During the same phase of the same clock cycle ~, CI is charged to bl~mJ Vr~
where b, is 1 or 0.
In the third phase,~3, of the same clock cycle, the third switch 20a in the first stage 12a opens. Also, the first 16b and second 18b switches in the second stage 12b are opened and the third switch 20b closes. Therefore, the voltage across CI and Co is shared.
Again, since the capacitors are matched, the voltage will divide equally across C, and Co.
Therefore, at the end of the third phase of the clock cycle, ~3, the voltage across C, is:
1~, 1 to vC, = 2 "lLmwrej + 4 bO~m~Vref At the same time, that is during ~3 of the same clock cycle, C2 is charged to b2~mJ Vref where b2 is 0 or 1.
The next phase is the first phase, ~1, of the next clock cycle. The first three stages behave as described above. The fourth stage 12d continues to convert the same word.
The third switch 20b in the second stage 12b opens. Also, the first 16c and second 18c switches in the third stage 12c are opened and the third switch 20c closes. Therefore, the voltage across C2 and CI is shared. Again, since the capacitors are matched, the voltage will divide equally across C2 and C,. Therefore, at the end of the first phase, ~l, of the next 2o clock cycle the voltage across C2 is:
VCz = 2 bz~m~Vref + 4 bl~mlVref + g bo~m~Vref .
At the same time, that is during ~I of the same clock cycle, C3 is charged to b3~mJ Vref where b3 is 0 or 1.
The digital input bits are properly delayed for ensuring that they are processed at the correct time. The DAC continues in a similar fashion until a charge is accumulated on the capacitor 14 in the last stage. At this point the accumulated charge is an analog representation of the digital word input. Due to the pipelined architecture of the system, the throughput of the DAC is one word per clock cycle.
However, this architecture for a QPPDAC suffers from parasitic capacitance.
The parasitic capacitance is due to several factors, including the reverse biased junction capacitance of the switches and any stray metal-to-metal, or metal-to-substrate capacitance that could have been introduced in the manufacturing process. This parasitic, or stray, capacitance brings stray charge into the conversion operation.
The stray charge in the system is undesirable for two reasons. The first reason is that the stray charge can lead to a gain error. Since the voltage on a capacitor is proportional to 1o the charge on the capacitor, any stray charge will affect voltage, and lead to inaccurate results. The second undesirable affect of the stray capacitance is that it is typically non-linear. Non-linearity of the capacitors makes the output voltage a non-linear function of the input, again distorting the results. The problem of non-linearity is more serious for high-speed DACs, where large switches (with large junction capacitance) are used for 15 shorter charge and discharge times.
Another shortcoming of the QPPDAC is that its largest differential non-linearity (DNL) is at the midrange. Figure 4 illustrates this problem. This large DNL is caused by capacitor mismatch, which is inevitable in the manufacturing process. In general, a 2o mismatch between any of the equivalent capacitors creates conversion non-linearity.
It is an object of the present invention to obviate or mitigate at least some of the disadvantages mentioned above.
In accordance with an aspect of the present invention there is provided a pipelined digital-to-analog converter (DAC) for converting a digital input to an analog output. The pipelined DAC has a plurality of stages. A first of the plurality of stages is coupled to an initialization capacitor and ground. A remainder of the plurality of stages is coupled to a 3o previous stage. Each of said plurality of stages comprises the following. A
capacitor having a first and second plate, the capacitor for receiving a charge at the first plate in accordance with an associated bit of the digital input. A switch for coupling the first plate of said capacitor to ground when the capacitor is not receiving the charge. A switch for coupling the second plate of the capacitor to ground when the capacitor is receiving the charge. Coupling the capacitor to ground reduces the effect of stray capacitance in the pipelined DAC.
In accordance with a further aspect of the invention there is provided a DAC
for converting a digital input to an analog output. The DAC comprises the following components. A first DAC circuit coupled to the digital input and a sign of the digital 1o input. A reference voltage to the first DAC circuit is positive if the digital input is positive and negative if the digital input is negative. A second DAC circuit coupled to the digital input and an inverse of the sign of the digital input. A reference voltage to the , second DAC circuit is positive if the digital input is negative and negative if the digital input is positive. A combiner for subtracting the output of said second DAC
from the 15 output of the first DAC.
In accordance with yet a further aspect of the invention there is provided a DAC for converting a digital input to an analog output. The DAC is coupled to a positive reference voltage if the digital input is positive and a negative reference voltage if the 2o digital input is negative, thereby doubling the DAC's output range and moving a large differential non-linearity from a midpoint of said output range.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will now be described by way of example only with reference to 25 the following drawings in which:
Figure 1 is a flow diagram describing an algorithm for a digital to analog converter (prior art);
Figure 2a is a schematic diagram of a quasi-passive pipelined digital to analog converter (DAC) (prior art);
3o Figure 2b is a timing diagram for a clock to be used in the DAC shown in Figure 2a (prior art);
Figure 3 is a block diagram illustrating the flow of input into the DAC shown in Figure 2a (prior art);
Figure 4 is a graph illustrating the position of the largest differential non-linearity of the DAC shown in figure 2a (prior art);
Figure 5 is a schematic diagram of a quasi-passive pipelined DAC in accordance with an embodiment of the invention;
Figure 6 is a schematic diagram of a first stage of a sample and hold circuit;
Figure 7 is a schematic diagram of a bipolar quasi-passive pipelined DAC;
Figure 8 is a graph illustrating the position of the largest differential non-linearity of the DAC shown in figure 7;
Figure 9 is a schematic diagram of a differential bipolar quasi-passive pipelined DAC;
Figure 10 is a schematic diagram of a second stage of a sample and hold circuit;
Figure lOb is a timing diagram for a clock to be used in the SH circuit shown in Figure 10a;
Figure 11 is a schematic diagram of a pipelined DAC with a pair of parallel final stages;
Figure 12 is a schematic diagram of a cyclic DAC with a positive and a negative reference voltage;
2o Figure 13 is a schematic diagram of a differential bipolar cyclic DAC;
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
For convenience, like numerals in the description refer to like structures in the drawings.
Referring to Figure 5 a QPPDAC circuit is represented generally by the numeral 50. The circuit 50 behaves in a similar fashion to the circuit 20 illustrated in figure 2a, however it is arranged for minimizing the effect of stray capacitance. The circuit 50 includes several stages 52. Each stage comprises a capacitor 54 and several switches. A top plate of the capacitor 54 is couple to ground via a first switch 56. The top plate of the capacitor is further coupled to a previous stage via a second switch 58. A bottom plate of the 3o capacitor 54 is coupled to the reference voltage V,efvia a third switch 60 and coupled to ground via a fourth switch 62. The bottom plate is further coupled to ground via a fifth switch 64.
For the first stage 52a, there is no previous stage for the top plate of the capacitor 54a to be coupled. Rather, the top plate of the capacitor 54a is coupled via the second switch 58a to the top plate of an initialization capacitor 66, and an initialization switch 68. The initialization capacitor 66 has the same capacitance as the other capacitors 54. Both the bottom plate of the initialization capacitor 66 and the other end of the initialization switch 68 are coupled to ground. For the final stage 52f, the capacitor 54f is further coupled to 1o an output stage such as sample and hold (not shown). Refernng to figure Sb, a three phase clock is implemented for the timing of the circuit 50, as in the prior art.
Implementing the QPPDAC in this manner provides the removal of a majority of the effect of stray capacitance. For example, charging the capacitor 54a in the first stage 52a to V,.ef(assuming bit bo(mJ is a 1) is described as follows. Figure Sc shows an exploded view of the first stage 52a of the circuit 50. The figure includes schematic representations of the parasitic (stray) capacitance. The capacitor 54a is charged during the first phase, ~1, of each clock cycle. Therefore, the first switch 56a is closed and the top plate of the capacitor 54a is grounded. The stray capacitance 70 associated with the 2o top plate of the capacitor 54a is effectively removed since both "plates"
of the parasitic capacitance 70 are coupled to ground.
While the top plate is grounded, the bottom plate is charged with a charge equal to Q = CoVref When the clock enters the second phase ~, the first switch 56a is opened, as is the switch 60a providing the reference voltage. During ~, the bottom plate is grounded via switch 64a. The parasitic capacitance 72 associated with the bottom plate of the capacitor 54a is, therefore, effectively removed since both "plates" of the parasitic capacitance are coupled to ground. Since the charge on the capacitor 54a remains the same, so must the 3o voltage across it. Therefore, when the bottom plate is grounded the voltage is transferred to the top plate. The switch 58a connecting the first stage 52a to the initialization capacitor 66 is closed and the voltage across the capacitor 54a is shared. The circuit continues to work in the same manner as described in the prior art using the architecture described in the present embodiment of the invention until the charge on the final capacitor represents an analog conversion of a digital input.
There is still however an issue with non-linearity. Although the gain error is improved by grounding the top plate while the capacitors are charging, there is still a non-linearity introduced by the switches that cannot be avoided. The non-linearity, however, can be removed after the last stage 54f of the DAC. Referring to figure 6, a first stage of a 1o sample and hold (SH) circuit is illustrated generally by numeral 80.
The first stage of the SH circuit 80 comprises an inverting amplifier 82, a linear SH
capacitor 84 and a first 86 and a second 88 SH switch. The SH capacitor 84 is coupled to the amplifier in a negative feedback configuration. The first SH switch 86 couples the 15 input of the amplifier 82 to the top plate of the capacitor 54f in the last stage 52f of the DAC. The second SH switch 88 couples the output of the amplifier 82 to the bottom plate of the capacitor 54f in the last stage 52f of the DAC. Non-linear capacitance associated with the system is represented graphically as a capacitor 90.
2o In the example illustrated in figure 6, the resolution of the DAC modulus the number of bits input at a time is equal to one. Therefore, the capacitor 54f in last stage 52f of the DAC is charged during the first phase ~l of the clock cycle. Similarly, if the resolution of the DAC modulus the number of bits input at a time was equal to two, the capacitor in the last stage of the DAC would be charged during the second phase ~ of the clock cycle.
25 Since the number of bits input at a time is equal to three for the present embodiment, the last alternative occurs when the resolution of the DAC modulus the number of bits input at a time is equal to 0. In this case, the capacitor in the last stage of the DAC would be charged during the third phase ~3 of the clock cycle.
3o For any of the above described cases, the SH switches 86 and 88 both close two phases after the capacitor is charged. In the example illustrated in figure 6, the SH
switches 86 and 88 close during the third phase, ~. This allows the capacitor to charge to the value of the nth bit during the first phase, and the previous n -1 bits to be added to the nth bit in the second phase. During the third phase, the SH switches 86 and 88 are closed. The input to the amplifier 82 is at analog ground and therefore forces the top plate of the capacitor 54f in the last stage 52f to ground. Therefore, the non-linear capacitance 90 is effectively removed, since both the top "plate" and the bottom "plate" are grounded.
Since all of the other switches are open, the charge associated with the capacitor 54f on the final stage is shared with the SH capacitor 84. If the capacitors 54f and 84 are matched and there is no charge already on the SH capacitor 84, then they will share the 1o charge equally. Since both capacitors are linear, the output of the DAC
will be linear.
Referring to figure 1 Oa, a second stage of the sample and hold (SH) circuit is illustrated generally by numeral 200. The second stage of the SH circuit 200 comprises an amplifier 82, a sample capacitor Cs, a hold capacitor CH, and four SH switches S1, S2, S3, and S4.
One end of sample capacitor Cs is coupled the output of the first stage SH
circuit 80 via the first switch S 1 and to the output of the amplifier via the third switch S3. The other end of the sample capacitor Cs is coupled to the input of the amplifier 82 via the fourth switch S4 and to ground via the second switch S2. The hold capacitor CH is coupled to ' the amplifier 82 in a negative feedback configuration.
Referring to figure l Ob, the timing for the switches in figure 10a is illustrated. The first and second switches S 1 and S2 are closed first, simultaneously. This charges the sample capacitor Cs to the input voltage. The first and second switches S 1 and S2 are then opened and the third and fourth switches S3 and S4 are closed. This transfers the input voltage to the hold capacitor CH. The second stage of the SH circuit 200 provides continuous time linearity, that is, linearity during transients. While a specific SH circuit is described above, the DAC may be implemented using other SH circuits that are either proprietary or known in the art.
3o The DAC, however, still has its largest differential non-linearity (DNL) at the middle of its range. The DNL can be reduced and moved away from that point by a technique referred to as bipolar conversion. Figure 7 illustrates the DAC previously described, fi~rther amended for allowing bipolar conversion, represented generally by the numeral 90. This DAC circuit 90 behaves in a similar fashion as the previously described circuit illustrated in figure 5. However, the reference voltage V~efthat is applied depends on the sign of the input word that is being converted. If the input word is negative, then a negative voltage is applied. If the input word is positive, then a positive voltage is applied. In figure 7, the sign of the input is represented as s[m], where s[m]
_ ~1. The sign of the input may be represented with a sign bit or in twos complement notation.
There are several effective methods of converting between the two formats that are 1o known to a person skilled in the art. The magnitude of the digital input determines the magnitude of the analog output. For unipolar conversion, the DAC ranges from 0 to a maximum in a positive direction on both axes. For bipolar conversion the DAC
ranges from a maximum in a negative direction to a maximum in the positive direction on both axes.
There are two advantages in using this architecture. First, the major DNL
error is moved away from the midpoint to the 1/4 and 3/4 range points. Secondly, since the output range is effectively doubled, the non-linearity loses its significance by one bit.
These facts are better illustrated in the linearity plots shown in figure 8. While the discontinuities have 2o maintained their sizes, one extra bit of resolution is obtained due to the doubled output range. The fact that the converter is most linear at the midpoint makes the dynamic range of the DAC virtually independent of its linearity. This is a significant advantage for this DAC in many practical applications such as audio and voice.
However, there is a difficulty with the implementation of a bipolar DAC. A
mismatch between the positive and negative voltages can cause significant non-linearity. Figure 9 illustrates a differential architecture, represented generally by the numeral 90, that is used for avoiding this issue as well as improving the noise immunity of a DAC in a system.
The differential architecture 90 includes a positive bipolar pipelined DAC 92 circuit, a 3o negative bipolar pipelined DAC 94 circuit, a combiner 96, and a sample and hold circuit 98. Each DAC circuit 92 and 94 has a first input, a second input, and an output. The output of each DAC circuit 92 and 94 is connected to the combiner 96. The combiner 96 is connected to the sample and hold circuit 98.
The first input for each DAC is used for receiving the digital input and the second input for each DAC is used for the sign of the digital input. The negative DAC
circuit 94 is virtually a mirror image of the positive DAC circuit 92. While they share the same digital input, they use opposite reference voltages. A signal to be input to the sample and hold circuit 98 is obtained by subtracting the output of the negative DAC
circuit 94 from the output of the positive DAC circuit 92 in the combiner 96. The sample and hold to circuit is preferably a differential circuit itself.
The differential DAC can therefore virtually cancel the reference voltage mismatch by averaging them out. Although this is clear intuitively, a mathematical derivation helps to quantify it. Let the inherent gain of the plus 92 and minus 94 sides be Gp and Gm respectively. Ideally, Gp = Gm = I, but due to capacitor mismatches these gains may have slight errors. The actual gain (slope) of the plus 92 and minus 94 sides for a digital input with a positive sign is then GpVref+ and GmVref respectively. The overall slope of the converter, after sample and hold 98, for positive digital inputs can be written as Sp = GpVref+ - GmVref.
2o Similarly, the negative slope is Sn = Gp vref - Gm yref+.
Ideally, Sp = -Sn, and no distortion is caused by slope mismatch. The exact slope mismatch is dS = Sp + Sn = (Gp - Gm)(Vref+ + Vref).
This mismatch is less than the single-ended mismatch of Vref+ + Vref by a factor of Gp -Gm.
Another advantage of the differential architecture for the DAC is the reduction of capacitor non-linearity error. Capacitor non-linearity can arise from penetrations of an 3o electric field of the capacitor into the plates. This non-linearity affects the integral linearity of the converter.
Generally, the pipeline stages settle faster than the SH circuit. Therefore, to avoid the speed of the SH circuit becoming a bottleneck, an additional stage is added in parallel with the last stage. Referring to figure 11, this embodiment of the invention is illustrated generally by numeral 250. The stages 252 and 254 are multiplexed between the DAC
and the SH circuit. While one of the stages is participating in the digital to analog conversion, the other is transferring charge to the SH. This allows the SH
circuit to operate as slow as half the speed of the DAC circuit without constraining the overall conversion speed.
While the embodiments described above refer to the pipeline implementation of the DAC, the ideas can just as effectively be implemented for a cyclic DAC.
Refernng to figure 12, a cyclic DAC is provided with a positive and negative voltage, which has the same effects as described for the pipelined DAC. Further, referring to figure 13, a cyclic ~ 5 DAC with a positive reference voltage and a cyclic DAC with a negative reference voltage are coupled in parallel. Again, this has the same effects as described for the pipelined DAC
While the pipelined DAC produces a new output on every clock cycle, the cyclic DAC
2o requires a number of clock cycles for a conversion. The SH stage circuit of the cyclic DAC is approximately 3 times slower than the switch and capacitors in the transfer of change. Since the number of conversion bits is typically much larger than 3, the same SH
stage circuit can be shared by multiple cyclic DAC circuits. Therefore, a bank of cyclic DACs may be implemented that delivers conversion rates between those of a single 25 cyclic DAC and a pipelined DAC.
While the invention has been described in connection with a specific embodiment thereof and in a specific use, various modifications thereof will occur to those skilled in the art without departing from the spirit of the invention.
The terms and expressions which have been employed in the specification are used as terms of description and not of limitations, there is no intention in the use of such terms and expressions to exclude any equivalents of the features shown and described or portions thereof, but it is recognized that various modifications are possible within the scope of the invention.
Priority is claimed from Canadian Patent Application No. 2,327,644. The present invention relates to an improved system for converting data from a digital form to an analog form.
BACKGROUND OF THE INVENTION
A digital to analog converter (DAC) is a device for generating an analog output, usually a voltage~or current, that is a representation of a sequence of bits at its input. For example, an 8-bit DAC outputs a voltage or current that can have one of 256 different values. So if 1o the output ranges from 0 to IOV, the DAC outputs a voltage corresponding to one of 256 voltage levels between 0 and 10. A number of techniques are used to implement this conversion.
One such technique is known as an algorithmic DAC, which is based on a step-by-step method. Generally, a multi-bit word, or digital input, is processed one portion at a time.
In each step, a partial result from the previous step is combined with a portion of the mufti-bit input word and then passed on to the next step. Figure 1 is a flow chart illustrating this basic algorithm, wherein the input word is processed one bit at a time, starting from the least significant bit. An interim value R is initialized to zero. A counter 2o n, used to count the number of bits processed, is also initialized to zero.
A loop commences wherein if a bit b" is 0, the interim value R is divided in half. If the bit bn is 1, the sum of the interim value R and a reference voltage V,efis divided in half. The value of the counter n is increased by one. The loop is repeated for the next more significant bit until n = N, where N is the total number of bits in the word input. At that 2s point, the interim value R represents an analog form of the word input.
Dividing R in half weights the digital bits according to their significance. That is, the least significant bit has the smallest impact on the outcome of the DAC since it will be divided more times than any of the other bits.
3o Although there are other algorithms available in the art, this technique is attractive because of the savings it offers in terms of circuit size and power. Two architectures that have been developed to implement this technique are the pipelined DAC and the cyclic DAC. The pipelined DAC provides operating speed at the expense of size and therefore, power. The cyclic DAC is more economical than the pipelined DAC since it reuses the same hardware for each iteration of the algorithm. However, the reduction in size of the cyclic DAC comes at the expense of a lower output rate. It is most suitable to implement algorithmic DACs using a switched-capacitor (SC) technique, however other techniques, such as switched-current (SI), can also be used.
Original SC pipelined DACs used an operational amplifier (op amp) in each stage for 1o performing the required operations, however this makes the DAC very expensive. Figure 2a illustrates a SC quasi-passive pipelined DAC (QPPDAC), represented generally by the numeral 10 that is described below. The DAC is referred to as quasi-passive because no op amps are used for performing the required operations. Rather, the DAC
essentially comprises capacitors and switches.
The QPPDAC circuit 10 includes a series of stages 12. Each stage 12 comprises a capacitor 14 and several switches. A first plate (herein referred to as the bottom plate for illustrative purposes only) of the capacitor 14 is coupled to ground. A second plate (herein referred to as the top plate for illustrative purposes only) of the capacitor 14 is 2o coupled to a reference voltage V,.efma a first switch 16 and to ground via a second switch 18. The top plate of the capacitor 14 is also coupled to the top plate of the capacitor in a previous stage via a third switch 20. For the first stage 12a, there is no previous stage for the top plate of the capacitor 14 to be coupled. Instead, the top plate of the capacitor 14 is coupled via the third switch 20 to the top plate of an initialization capacitor 22, and an initialization switch 24. The initialization capacitor 22 has the same capacitance as the remaining capacitors 14. Both the bottom plate of the initialization capacitor 22 and the other end of the initialization switch 24 are coupled to ground. For the final stage 12f, the capacitor 14f is further coupled to an output stage such as sample and hold (not shown).
The QPPDAC uses a three-phase clock for timing. A timing diagram for the clock is shown in figure 2b. The clock phases run continuously, that is, no reset cycle or the like ;
is necessary, and a portion of a new digital input word is taken in every clock cycle.
Also, the phases are staggered in time and do not overlap. Therefore, the DAC
can operate on N div 3 words at the same time, where N is the number of resolution bits of the DAC and the portion of the word taken in is three (3) bits in size.
Figure 3 provides an illustrative example as to how the bits are input into the QPPDAC, represented generally by the numeral 30. In this example, N = 9, so three numbers can be 1o converted at a time. In a first clock cycle, three bits from each of three words are input to the DAC 32. These bits are the least significant bits (LSB) of word 3, the middle 3 bits of word 2, and the most significant bits (MSB) of word 1. The less significant bits of word l and word 2 have already been converted in previous clock cycles. In the next clock cycle, the middle three bits of word 3, the MSB of word 2, and the LSB
of a new ~ 5 word, word 4, are converted. Lastly, in the next clock cycle, the MSB of word 3, the middle three bits of word four, and the LSB of a new word, word 5, are converted.
Therefore, after 3 clock cycles an entire 9-bit word is converted.
Referring once again to figure 2, b~~kJ represents the jth bit of the kth digital input word.
2o The conversion process for each word begins with the LSB. Depending on the bit value, either the first switch 16a So, I or the second switch 18a So,2 is closed during the first phase of the clock cycle, ~l. If the first switch 16a is closed, Co is charged to V,ef If the second switch 18a is closed, Co is grounded. Therefore, the voltage at Co can be represented as bo~mJ V,ef, where bo is 1 or 0. At the same time, the initiation switch 24 is closed and the 25 initiation capacitor 22 is discharged to ground. The third switch 20a remains open and closes only in the following clock phase.
In the second phase,, of the same clock cycle, the first 16a and second 18a switches in the first stage 12a are opened and the third switch 20a closes. CD shares its charge with 3o the initiation capacitor 22 through the third switch 20a. Since all the capacitors are matched, the voltage at Co is equal to:
VCp -~bO~m~Vref~~2.
During the same phase of the same clock cycle ~, CI is charged to bl~mJ Vr~
where b, is 1 or 0.
In the third phase,~3, of the same clock cycle, the third switch 20a in the first stage 12a opens. Also, the first 16b and second 18b switches in the second stage 12b are opened and the third switch 20b closes. Therefore, the voltage across CI and Co is shared.
Again, since the capacitors are matched, the voltage will divide equally across C, and Co.
Therefore, at the end of the third phase of the clock cycle, ~3, the voltage across C, is:
1~, 1 to vC, = 2 "lLmwrej + 4 bO~m~Vref At the same time, that is during ~3 of the same clock cycle, C2 is charged to b2~mJ Vref where b2 is 0 or 1.
The next phase is the first phase, ~1, of the next clock cycle. The first three stages behave as described above. The fourth stage 12d continues to convert the same word.
The third switch 20b in the second stage 12b opens. Also, the first 16c and second 18c switches in the third stage 12c are opened and the third switch 20c closes. Therefore, the voltage across C2 and CI is shared. Again, since the capacitors are matched, the voltage will divide equally across C2 and C,. Therefore, at the end of the first phase, ~l, of the next 2o clock cycle the voltage across C2 is:
VCz = 2 bz~m~Vref + 4 bl~mlVref + g bo~m~Vref .
At the same time, that is during ~I of the same clock cycle, C3 is charged to b3~mJ Vref where b3 is 0 or 1.
The digital input bits are properly delayed for ensuring that they are processed at the correct time. The DAC continues in a similar fashion until a charge is accumulated on the capacitor 14 in the last stage. At this point the accumulated charge is an analog representation of the digital word input. Due to the pipelined architecture of the system, the throughput of the DAC is one word per clock cycle.
However, this architecture for a QPPDAC suffers from parasitic capacitance.
The parasitic capacitance is due to several factors, including the reverse biased junction capacitance of the switches and any stray metal-to-metal, or metal-to-substrate capacitance that could have been introduced in the manufacturing process. This parasitic, or stray, capacitance brings stray charge into the conversion operation.
The stray charge in the system is undesirable for two reasons. The first reason is that the stray charge can lead to a gain error. Since the voltage on a capacitor is proportional to 1o the charge on the capacitor, any stray charge will affect voltage, and lead to inaccurate results. The second undesirable affect of the stray capacitance is that it is typically non-linear. Non-linearity of the capacitors makes the output voltage a non-linear function of the input, again distorting the results. The problem of non-linearity is more serious for high-speed DACs, where large switches (with large junction capacitance) are used for 15 shorter charge and discharge times.
Another shortcoming of the QPPDAC is that its largest differential non-linearity (DNL) is at the midrange. Figure 4 illustrates this problem. This large DNL is caused by capacitor mismatch, which is inevitable in the manufacturing process. In general, a 2o mismatch between any of the equivalent capacitors creates conversion non-linearity.
It is an object of the present invention to obviate or mitigate at least some of the disadvantages mentioned above.
In accordance with an aspect of the present invention there is provided a pipelined digital-to-analog converter (DAC) for converting a digital input to an analog output. The pipelined DAC has a plurality of stages. A first of the plurality of stages is coupled to an initialization capacitor and ground. A remainder of the plurality of stages is coupled to a 3o previous stage. Each of said plurality of stages comprises the following. A
capacitor having a first and second plate, the capacitor for receiving a charge at the first plate in accordance with an associated bit of the digital input. A switch for coupling the first plate of said capacitor to ground when the capacitor is not receiving the charge. A switch for coupling the second plate of the capacitor to ground when the capacitor is receiving the charge. Coupling the capacitor to ground reduces the effect of stray capacitance in the pipelined DAC.
In accordance with a further aspect of the invention there is provided a DAC
for converting a digital input to an analog output. The DAC comprises the following components. A first DAC circuit coupled to the digital input and a sign of the digital 1o input. A reference voltage to the first DAC circuit is positive if the digital input is positive and negative if the digital input is negative. A second DAC circuit coupled to the digital input and an inverse of the sign of the digital input. A reference voltage to the , second DAC circuit is positive if the digital input is negative and negative if the digital input is positive. A combiner for subtracting the output of said second DAC
from the 15 output of the first DAC.
In accordance with yet a further aspect of the invention there is provided a DAC for converting a digital input to an analog output. The DAC is coupled to a positive reference voltage if the digital input is positive and a negative reference voltage if the 2o digital input is negative, thereby doubling the DAC's output range and moving a large differential non-linearity from a midpoint of said output range.
BRIEF DESCRIPTION OF THE DRAWINGS
The present invention will now be described by way of example only with reference to 25 the following drawings in which:
Figure 1 is a flow diagram describing an algorithm for a digital to analog converter (prior art);
Figure 2a is a schematic diagram of a quasi-passive pipelined digital to analog converter (DAC) (prior art);
3o Figure 2b is a timing diagram for a clock to be used in the DAC shown in Figure 2a (prior art);
Figure 3 is a block diagram illustrating the flow of input into the DAC shown in Figure 2a (prior art);
Figure 4 is a graph illustrating the position of the largest differential non-linearity of the DAC shown in figure 2a (prior art);
Figure 5 is a schematic diagram of a quasi-passive pipelined DAC in accordance with an embodiment of the invention;
Figure 6 is a schematic diagram of a first stage of a sample and hold circuit;
Figure 7 is a schematic diagram of a bipolar quasi-passive pipelined DAC;
Figure 8 is a graph illustrating the position of the largest differential non-linearity of the DAC shown in figure 7;
Figure 9 is a schematic diagram of a differential bipolar quasi-passive pipelined DAC;
Figure 10 is a schematic diagram of a second stage of a sample and hold circuit;
Figure lOb is a timing diagram for a clock to be used in the SH circuit shown in Figure 10a;
Figure 11 is a schematic diagram of a pipelined DAC with a pair of parallel final stages;
Figure 12 is a schematic diagram of a cyclic DAC with a positive and a negative reference voltage;
2o Figure 13 is a schematic diagram of a differential bipolar cyclic DAC;
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
For convenience, like numerals in the description refer to like structures in the drawings.
Referring to Figure 5 a QPPDAC circuit is represented generally by the numeral 50. The circuit 50 behaves in a similar fashion to the circuit 20 illustrated in figure 2a, however it is arranged for minimizing the effect of stray capacitance. The circuit 50 includes several stages 52. Each stage comprises a capacitor 54 and several switches. A top plate of the capacitor 54 is couple to ground via a first switch 56. The top plate of the capacitor is further coupled to a previous stage via a second switch 58. A bottom plate of the 3o capacitor 54 is coupled to the reference voltage V,efvia a third switch 60 and coupled to ground via a fourth switch 62. The bottom plate is further coupled to ground via a fifth switch 64.
For the first stage 52a, there is no previous stage for the top plate of the capacitor 54a to be coupled. Rather, the top plate of the capacitor 54a is coupled via the second switch 58a to the top plate of an initialization capacitor 66, and an initialization switch 68. The initialization capacitor 66 has the same capacitance as the other capacitors 54. Both the bottom plate of the initialization capacitor 66 and the other end of the initialization switch 68 are coupled to ground. For the final stage 52f, the capacitor 54f is further coupled to 1o an output stage such as sample and hold (not shown). Refernng to figure Sb, a three phase clock is implemented for the timing of the circuit 50, as in the prior art.
Implementing the QPPDAC in this manner provides the removal of a majority of the effect of stray capacitance. For example, charging the capacitor 54a in the first stage 52a to V,.ef(assuming bit bo(mJ is a 1) is described as follows. Figure Sc shows an exploded view of the first stage 52a of the circuit 50. The figure includes schematic representations of the parasitic (stray) capacitance. The capacitor 54a is charged during the first phase, ~1, of each clock cycle. Therefore, the first switch 56a is closed and the top plate of the capacitor 54a is grounded. The stray capacitance 70 associated with the 2o top plate of the capacitor 54a is effectively removed since both "plates"
of the parasitic capacitance 70 are coupled to ground.
While the top plate is grounded, the bottom plate is charged with a charge equal to Q = CoVref When the clock enters the second phase ~, the first switch 56a is opened, as is the switch 60a providing the reference voltage. During ~, the bottom plate is grounded via switch 64a. The parasitic capacitance 72 associated with the bottom plate of the capacitor 54a is, therefore, effectively removed since both "plates" of the parasitic capacitance are coupled to ground. Since the charge on the capacitor 54a remains the same, so must the 3o voltage across it. Therefore, when the bottom plate is grounded the voltage is transferred to the top plate. The switch 58a connecting the first stage 52a to the initialization capacitor 66 is closed and the voltage across the capacitor 54a is shared. The circuit continues to work in the same manner as described in the prior art using the architecture described in the present embodiment of the invention until the charge on the final capacitor represents an analog conversion of a digital input.
There is still however an issue with non-linearity. Although the gain error is improved by grounding the top plate while the capacitors are charging, there is still a non-linearity introduced by the switches that cannot be avoided. The non-linearity, however, can be removed after the last stage 54f of the DAC. Referring to figure 6, a first stage of a 1o sample and hold (SH) circuit is illustrated generally by numeral 80.
The first stage of the SH circuit 80 comprises an inverting amplifier 82, a linear SH
capacitor 84 and a first 86 and a second 88 SH switch. The SH capacitor 84 is coupled to the amplifier in a negative feedback configuration. The first SH switch 86 couples the 15 input of the amplifier 82 to the top plate of the capacitor 54f in the last stage 52f of the DAC. The second SH switch 88 couples the output of the amplifier 82 to the bottom plate of the capacitor 54f in the last stage 52f of the DAC. Non-linear capacitance associated with the system is represented graphically as a capacitor 90.
2o In the example illustrated in figure 6, the resolution of the DAC modulus the number of bits input at a time is equal to one. Therefore, the capacitor 54f in last stage 52f of the DAC is charged during the first phase ~l of the clock cycle. Similarly, if the resolution of the DAC modulus the number of bits input at a time was equal to two, the capacitor in the last stage of the DAC would be charged during the second phase ~ of the clock cycle.
25 Since the number of bits input at a time is equal to three for the present embodiment, the last alternative occurs when the resolution of the DAC modulus the number of bits input at a time is equal to 0. In this case, the capacitor in the last stage of the DAC would be charged during the third phase ~3 of the clock cycle.
3o For any of the above described cases, the SH switches 86 and 88 both close two phases after the capacitor is charged. In the example illustrated in figure 6, the SH
switches 86 and 88 close during the third phase, ~. This allows the capacitor to charge to the value of the nth bit during the first phase, and the previous n -1 bits to be added to the nth bit in the second phase. During the third phase, the SH switches 86 and 88 are closed. The input to the amplifier 82 is at analog ground and therefore forces the top plate of the capacitor 54f in the last stage 52f to ground. Therefore, the non-linear capacitance 90 is effectively removed, since both the top "plate" and the bottom "plate" are grounded.
Since all of the other switches are open, the charge associated with the capacitor 54f on the final stage is shared with the SH capacitor 84. If the capacitors 54f and 84 are matched and there is no charge already on the SH capacitor 84, then they will share the 1o charge equally. Since both capacitors are linear, the output of the DAC
will be linear.
Referring to figure 1 Oa, a second stage of the sample and hold (SH) circuit is illustrated generally by numeral 200. The second stage of the SH circuit 200 comprises an amplifier 82, a sample capacitor Cs, a hold capacitor CH, and four SH switches S1, S2, S3, and S4.
One end of sample capacitor Cs is coupled the output of the first stage SH
circuit 80 via the first switch S 1 and to the output of the amplifier via the third switch S3. The other end of the sample capacitor Cs is coupled to the input of the amplifier 82 via the fourth switch S4 and to ground via the second switch S2. The hold capacitor CH is coupled to ' the amplifier 82 in a negative feedback configuration.
Referring to figure l Ob, the timing for the switches in figure 10a is illustrated. The first and second switches S 1 and S2 are closed first, simultaneously. This charges the sample capacitor Cs to the input voltage. The first and second switches S 1 and S2 are then opened and the third and fourth switches S3 and S4 are closed. This transfers the input voltage to the hold capacitor CH. The second stage of the SH circuit 200 provides continuous time linearity, that is, linearity during transients. While a specific SH circuit is described above, the DAC may be implemented using other SH circuits that are either proprietary or known in the art.
3o The DAC, however, still has its largest differential non-linearity (DNL) at the middle of its range. The DNL can be reduced and moved away from that point by a technique referred to as bipolar conversion. Figure 7 illustrates the DAC previously described, fi~rther amended for allowing bipolar conversion, represented generally by the numeral 90. This DAC circuit 90 behaves in a similar fashion as the previously described circuit illustrated in figure 5. However, the reference voltage V~efthat is applied depends on the sign of the input word that is being converted. If the input word is negative, then a negative voltage is applied. If the input word is positive, then a positive voltage is applied. In figure 7, the sign of the input is represented as s[m], where s[m]
_ ~1. The sign of the input may be represented with a sign bit or in twos complement notation.
There are several effective methods of converting between the two formats that are 1o known to a person skilled in the art. The magnitude of the digital input determines the magnitude of the analog output. For unipolar conversion, the DAC ranges from 0 to a maximum in a positive direction on both axes. For bipolar conversion the DAC
ranges from a maximum in a negative direction to a maximum in the positive direction on both axes.
There are two advantages in using this architecture. First, the major DNL
error is moved away from the midpoint to the 1/4 and 3/4 range points. Secondly, since the output range is effectively doubled, the non-linearity loses its significance by one bit.
These facts are better illustrated in the linearity plots shown in figure 8. While the discontinuities have 2o maintained their sizes, one extra bit of resolution is obtained due to the doubled output range. The fact that the converter is most linear at the midpoint makes the dynamic range of the DAC virtually independent of its linearity. This is a significant advantage for this DAC in many practical applications such as audio and voice.
However, there is a difficulty with the implementation of a bipolar DAC. A
mismatch between the positive and negative voltages can cause significant non-linearity. Figure 9 illustrates a differential architecture, represented generally by the numeral 90, that is used for avoiding this issue as well as improving the noise immunity of a DAC in a system.
The differential architecture 90 includes a positive bipolar pipelined DAC 92 circuit, a 3o negative bipolar pipelined DAC 94 circuit, a combiner 96, and a sample and hold circuit 98. Each DAC circuit 92 and 94 has a first input, a second input, and an output. The output of each DAC circuit 92 and 94 is connected to the combiner 96. The combiner 96 is connected to the sample and hold circuit 98.
The first input for each DAC is used for receiving the digital input and the second input for each DAC is used for the sign of the digital input. The negative DAC
circuit 94 is virtually a mirror image of the positive DAC circuit 92. While they share the same digital input, they use opposite reference voltages. A signal to be input to the sample and hold circuit 98 is obtained by subtracting the output of the negative DAC
circuit 94 from the output of the positive DAC circuit 92 in the combiner 96. The sample and hold to circuit is preferably a differential circuit itself.
The differential DAC can therefore virtually cancel the reference voltage mismatch by averaging them out. Although this is clear intuitively, a mathematical derivation helps to quantify it. Let the inherent gain of the plus 92 and minus 94 sides be Gp and Gm respectively. Ideally, Gp = Gm = I, but due to capacitor mismatches these gains may have slight errors. The actual gain (slope) of the plus 92 and minus 94 sides for a digital input with a positive sign is then GpVref+ and GmVref respectively. The overall slope of the converter, after sample and hold 98, for positive digital inputs can be written as Sp = GpVref+ - GmVref.
2o Similarly, the negative slope is Sn = Gp vref - Gm yref+.
Ideally, Sp = -Sn, and no distortion is caused by slope mismatch. The exact slope mismatch is dS = Sp + Sn = (Gp - Gm)(Vref+ + Vref).
This mismatch is less than the single-ended mismatch of Vref+ + Vref by a factor of Gp -Gm.
Another advantage of the differential architecture for the DAC is the reduction of capacitor non-linearity error. Capacitor non-linearity can arise from penetrations of an 3o electric field of the capacitor into the plates. This non-linearity affects the integral linearity of the converter.
Generally, the pipeline stages settle faster than the SH circuit. Therefore, to avoid the speed of the SH circuit becoming a bottleneck, an additional stage is added in parallel with the last stage. Referring to figure 11, this embodiment of the invention is illustrated generally by numeral 250. The stages 252 and 254 are multiplexed between the DAC
and the SH circuit. While one of the stages is participating in the digital to analog conversion, the other is transferring charge to the SH. This allows the SH
circuit to operate as slow as half the speed of the DAC circuit without constraining the overall conversion speed.
While the embodiments described above refer to the pipeline implementation of the DAC, the ideas can just as effectively be implemented for a cyclic DAC.
Refernng to figure 12, a cyclic DAC is provided with a positive and negative voltage, which has the same effects as described for the pipelined DAC. Further, referring to figure 13, a cyclic ~ 5 DAC with a positive reference voltage and a cyclic DAC with a negative reference voltage are coupled in parallel. Again, this has the same effects as described for the pipelined DAC
While the pipelined DAC produces a new output on every clock cycle, the cyclic DAC
2o requires a number of clock cycles for a conversion. The SH stage circuit of the cyclic DAC is approximately 3 times slower than the switch and capacitors in the transfer of change. Since the number of conversion bits is typically much larger than 3, the same SH
stage circuit can be shared by multiple cyclic DAC circuits. Therefore, a bank of cyclic DACs may be implemented that delivers conversion rates between those of a single 25 cyclic DAC and a pipelined DAC.
While the invention has been described in connection with a specific embodiment thereof and in a specific use, various modifications thereof will occur to those skilled in the art without departing from the spirit of the invention.
The terms and expressions which have been employed in the specification are used as terms of description and not of limitations, there is no intention in the use of such terms and expressions to exclude any equivalents of the features shown and described or portions thereof, but it is recognized that various modifications are possible within the scope of the invention.
Claims (11)
1. A pipelined digital-to-analog converter (DAC) for converting a digital input to an analog output, said pipelined DAC having a plurality of stages, a first of said plurality of stages being coupled to an initialization capacitor and ground, a remainder of said plurality of stages being coupled to a previous stage, each of said plurality of stages comprising:
(a) a capacitor having a first and second plate, said capacitor for receiving a charge at said first plate in accordance with an associated bit of said digital input;
(b) a switch for coupling said first plate of said capacitor to ground when said capacitor is not receiving said charge; and (c) a switch for coupling said second plate of said capacitor to ground when said capacitor is receiving said charge;
wherein coupling said capacitor to ground reduces the effect of stray capacitance in said pipelined DAC.
(a) a capacitor having a first and second plate, said capacitor for receiving a charge at said first plate in accordance with an associated bit of said digital input;
(b) a switch for coupling said first plate of said capacitor to ground when said capacitor is not receiving said charge; and (c) a switch for coupling said second plate of said capacitor to ground when said capacitor is receiving said charge;
wherein coupling said capacitor to ground reduces the effect of stray capacitance in said pipelined DAC.
2. A pipelined DAC as defined in claim 1, wherein said remainder of said plurality of stages are coupled to a previous stage by a switch coupled between said second plate of said capacitor and a second plate of a capacitor in said previous stage.
3. A pipelined DAC as defined in claim 1, wherein said first plate is coupled to a reference voltage if said associated bit of said digital input is equal to one and coupled to ground if said associated bit of said digital input is equal to zero.
4. A pipelined DAC as defined in claim 3, wherein said reference voltage is positive if said digital input is positive and said reference voltage is negative if said digital input is negative.
5. A pipelined DAC as defined in claim 1, further comprising a first sample and hold circuit, said first sample and hold circuit comprising:
(a) an amplifier having its input coupled to said second plate of said capacitor in a last of said plurality of stages via a switch and its output coupled to said first plate of said capacitor in said last of said plurality of stages via a switch;
and (b) a sample and hold capacitor coupled with said amplifier in a negative feedback configuration;
wherein said charge is transferred from said capacitor in said last stage to said sample and hold capacitor in a linear fashion for providing a linear output.
(a) an amplifier having its input coupled to said second plate of said capacitor in a last of said plurality of stages via a switch and its output coupled to said first plate of said capacitor in said last of said plurality of stages via a switch;
and (b) a sample and hold capacitor coupled with said amplifier in a negative feedback configuration;
wherein said charge is transferred from said capacitor in said last stage to said sample and hold capacitor in a linear fashion for providing a linear output.
6. A pipelined DAC as defined in claim 5, further comprising a second sample and hold circuit, said second sample and hold circuit comprising:
(a) a sample capacitor having a first and second plate, said first plate being coupled to said output from said first sample and hold circuit via a switch and said second plate being coupled to ground via a switch;
(b) an amplifier having its input coupled to said second plate of said sample capacitor via a switch and its output coupled to said first plate of said sample capacitor via a switch; and (c) a hold capacitor coupled with said amplifier in a negative feedback configuration.
(a) a sample capacitor having a first and second plate, said first plate being coupled to said output from said first sample and hold circuit via a switch and said second plate being coupled to ground via a switch;
(b) an amplifier having its input coupled to said second plate of said sample capacitor via a switch and its output coupled to said first plate of said sample capacitor via a switch; and (c) a hold capacitor coupled with said amplifier in a negative feedback configuration.
7. A pipelined DAC as defined in claim 4 comprising a first and a second pipelined DAC circuit operating in parallel, said first pipelined DAC circuit coupled to said digital input and a sign of said digital input and said second pipelined DAC
circuit coupled to said digital input and an inverse of said sign of said digital input, wherein said output of said second pipelined DAC is subtracted from said output of said first pipelined DAC.
circuit coupled to said digital input and an inverse of said sign of said digital input, wherein said output of said second pipelined DAC is subtracted from said output of said first pipelined DAC.
8. A pipelined DAC as defined in claim 7, wherein a difference resulting from said subtraction is input to a sample and hold circuit.
9. A pipelined DAC as defined in claim 5, wherein said last of said plurality of stages comprises two stages in parallel for reducing a bottleneck at said sample and hold circuit, said sample and hold circuit multiplexing between each of said two last stages.
10. A digital-to-analog converter (DAC) for converting a digital input to an analog output, said DAC comprising (a) a first DAC circuit coupled to said digital input and a sign of said digital input, wherein a reference voltage to said first DAC circuit is positive if said digital input is positive and negative if said digital input is negative;
(b) a second DAC circuit coupled to said digital input and an inverse of said sign of said digital input, wherein a reference voltage to said second DAC circuit is positive if said digital input is negative and negative if said digital input is positive; and (c) a combiner for subtracting said output of said second DAC from said output of said first DAC.
(b) a second DAC circuit coupled to said digital input and an inverse of said sign of said digital input, wherein a reference voltage to said second DAC circuit is positive if said digital input is negative and negative if said digital input is positive; and (c) a combiner for subtracting said output of said second DAC from said output of said first DAC.
11. A digital-to-analog converter (DAC) for converting a digital input to an analog output, wherein said DAC is coupled to a positive reference voltage if said digital input is positive and to a negative reference voltage if said digital input is negative, thereby doubling said DAC's output range and moving a large differential non-linearity from a midpoint of said output range.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA 2364309 CA2364309A1 (en) | 2000-12-04 | 2001-12-03 | A system for improved digital-to-analog data conversion |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA002327644A CA2327644A1 (en) | 2000-12-04 | 2000-12-04 | A differential bipolar stray-insensitive pipelined digital-to-analog converter |
| CA2,327,644 | 2000-12-04 | ||
| CA 2364309 CA2364309A1 (en) | 2000-12-04 | 2001-12-03 | A system for improved digital-to-analog data conversion |
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| CA2364309A1 true CA2364309A1 (en) | 2002-06-04 |
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| CA 2364309 Abandoned CA2364309A1 (en) | 2000-12-04 | 2001-12-03 | A system for improved digital-to-analog data conversion |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112911176A (en) * | 2021-01-19 | 2021-06-04 | 西安理工大学 | Advanced digital-analog-domain TDI circuit for inhibiting parasitic effect and implementation method |
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2001
- 2001-12-03 CA CA 2364309 patent/CA2364309A1/en not_active Abandoned
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112911176A (en) * | 2021-01-19 | 2021-06-04 | 西安理工大学 | Advanced digital-analog-domain TDI circuit for inhibiting parasitic effect and implementation method |
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