CA1183913A - Capacitive commutating filter - Google Patents

Abstract

CAPACITIVE COMMUTATING FILTER
ABSTRACT OF THE DISCLOSURE
A capacitive commutating filter provides a D. C.
output voltage of amplitude responsive to the amplitude of an input waveform having a frequency substantially equal to the operating frequency of the filter. The filter operating frequency is established by a digital signal. The filter input is selectively and cyclically connected through N input resistances, wherein N is an integer greater than zero, to adjacently progressive N ones of (2N+1) nodes, each having one of (2N+1) capacitive filter elements connected to ground potential. The equilibrium voltages across the capacitive filter elements, established during the N/(2N+1) segments of the input waveform during which each capacitor is connected to the input, are coupled to one set each of maximum-positive-polarity and maximum-negative-polarity diodes, for placing the maximum and minimum filter capacitive element voltages at respective ones of the inverting and non-inverting inputs of a differential amplifier, having the output thereof forming the filter output.

Description

~ RD-7~663 Background of the Invention The present invention relates ~o electronic waveform filterin~ circuitry andv mor~ particularly~ ~o a novel capacitive commutating filter for detecting a particular 05 waveform frequency in an input signal.
Many data processing applicatio~s require a filter for de~ec~ing the presence of a w~Yeform at a particular frequency. Many forms of capacitive co~muta in~ filter are known for providing this fre~uency detection function~
1~ The prior art filters utilized passive or active circui~s in which the filter frequency is fixedly established and is dependent upon the ratio of values o various resistive, capacitive and/or inductive components.
Such component values must be established with relatively narrow tolerance and cause the filter to not only ~e relatively expensive to fabricate, but also restrict operation to only a single frequency. It is highly desirable to have a capacitive commutating filter which has a filter frequency capable of being precisely and repeatedly controlled by an external signal, and particu-larly one of digital nature. It is also advantageous ~o provide a capacitive commutating filter in which the filter frequency is relatively independent of process variation or temperature drift of the electronic componen~s utilized in th,e circuit.

~ RD~12~3 Br ef Summary of the Inve ion In accordance with the inventionO my novel capacitive commutating fil~er, capable of being digitally controlled to a center frequency capable of varia~ion over a three-os order-of-magnitude frequency range, u~ilize-~ switching means for simul~aneously connecting N resistances, where ~ is an in~eg@r greater than zero~ cyclically between a filter input termincll and adjacent one of (2N+13 nodes, each node being connected to one terminal of an individual one of ~2N+l) c~pacitive filter element~, having the remaining terminals connected to ground potential~ The resis~ances are controllably connected to the input terminal by a commutating switch drive circuit receiving a digital signal having a selected edge transition frequency equal to ~2~+1) times the commutating filter selection frequency. The capacitor filter elements are connec~ed through maximum-posi~ive-polarity voltage and maximum-negative-polarity voltage gating means, respectively, to respective maximum and zo minimum signal busses, respectively connected to the differential inputs of a differential amplifier. The greatest positive-polarity voltage magnitude and the greatest negative-polarity voltage magnitude are respect~
fully connected to the operational amplifier and provide a ilter D.C. output voltage which is present substantially only when the filter receives a waveform having the frequency to which the filter has been tuned by the tran~ition requency of the input digital control signal.

~ 3 In one presently preferred embodi.ment, the commutating switch drive circui~ry, utili~es a diYide-~by-(2N+l) counter having its outpu~s conllected to ~he word select inputs o a read only memory having (2N~l) da~a words each of (2N~l) output bits each connected for closing N of the input switchin~ means at any chosen time.
Accordingly, it is an objec~ of the present invention ~o provide a novel capaci~ive co~muta~ing il~er for deteting a periodic waveform of a frequ ncy established responsive to a digital control signal~
This and other ob; cts of the present in~ention will become apparent upon considera~ion of ~he foLlowing detailed description when read in conjunction with the drawings.
Brief Description of the Drawings ~ igure 1 is a schematic dia~ram of a presently preferred embodiment of ~he capacitive commutating filter in accordance with the invention;
Figure la is a schematic block diagram of a general input portion for the capacitive commutating filter of the present invention; and Figure 2 is a graph illustrating an input waveform and useful in understanding operation of the capacitive commutating fi:Lter o~ the inven~ionO
Dekailed Des¢r:iptlon_of the Invention Referriny initially to Figure 1, one presently preferred embodiment of my novel capacitive commutating . RD-12663 filter 10 inc1udes an inpu~ ~erminal lOa, ~o which an input voltage waveform Vin is applied, with respect to a ground poten~ial input terminal lOb~ A co~mutating switch ~ection 71 connects inpu~ terminal lOa via N
05 commutating resisto~s, where N is an in~eger greater than zero, ~e~uentia11y to N simultaneous ones of a se~ of (2~+1~ nodes. A different one of (2M~l) capacitors is connected between each of t:he node~ and ground potential.
In the illu~trakive embodimen~ N~29 whereby commutatin~
switch section 11 ha~ 2N+1=5 nodes Nl-N5, each connected to one terminal o an associated one o~ capacitors Cl-C5, respectively. The remaining terminal of each of the five capacitors is connected to ground potential.
Input termînal 1Oa is individually connectable through ~2N+l) swi~ching devi.ces, e.g. field-effec.t transistor switching devices Sl-S5, each in series with one of (2N~I) total commu~ating resistors, e.g A~ reisistors R1-~5, each connected to an associated one of the nodes, e.y. nodes Nl-N5. ~ (e.g. two) adjacent ones of switches S are c10sed at any particu1ar instant, with a cyclic change occurring at the mid-point of the conduction of any particular switch. That i5, the switches are cycllcally closed, e.g. in order Sl, S2, S3, S4, S5, S1 and so ~orth; at the instant that a particular switch, ~5 e.g. switch S3, is closed, the second-lower switch, e.g. switch Sl, is just opening, and the next-lower switch, e.y. S2 (which was closed halfway through ~ RD-12663 the closed time interval of the second-lower switch Sl) is itsel~ halfway ~hrough its closed time in~erval~
Similarly, ~he swi~ch ~o be next-se~uentially-closed, e.g~ switch S4, wiil close halfway through ~he time 05 interval during which switch ~3 i5 closed, and the second-higher-closing switch~ eOg. switch S5, will ctose when next-higher switch S4 is hatfway through a closure period, and a~ the time when switch 53 itsel open.~. Thus, there are always ~wo switche~ clo~ed and input ~erminal lOa is connected to a pair of adjacen~
commutating resistors, which, in ~urn, apply the ins~an~
taneous input signal amplitude to a pair of adjacent ones of capacitors Cl~CSr The general form of the input circuit (for N-2) is shown in Figure la, wherein switch S' acts, responsive to the signal at ~he input S'i thereof, to connect the pair o~ input.resistors R to N~2 two se~uential ones of nodes Nl-N5. The commutating signal at input S'i is provided by commutating switch drive circuitry 12;

which is itself activated in response to a digital signal having periodic transitions at a rate equal to (2N~l) times the desire~ ioput frequency fO to be ac~uired. In the .illustrati.vé embodiment, with N-2 and ~2N+1)=5 nodes, a train of pulses, or a binary signal having a chosen~pol~rity transition frequency, of 5fO is requi~ed at input 12a.

~ 3 ~ RD-12663 Returni~g to Figure 1~ commutating switch drive circuitry 12 utilizes a divide by-(2N-~l) mea~s 14, e.g. a divide~by-five means whlen ~=2. ~eans 14 may, in the illustra ive e~bodiment~ be formed by .the divide 05 by-five counter in a s~andard 7490 TT~ integrated.circuit.
Thus, responsive to the Sf0 frequency of the positive-qoing tran~itionso~ ~he digital input signal applied to means inpu~ 14a, fiv~ different s~at~s of the divider means logic output~ B0i BI and B2 occur and are coupled ~o the associated ~0, Al and A2 inputs of a read-only -.
memory means 15. Memory means 15 is a (2N+l) word by (2N-~l) bit memory~ e.g. a five-word by five-~it memory means, when N=2. Each of the five memory means r data outputs D~-D4 is individually connected to the control electrode of an associated swi.tch means S, in manner such that a logic-one level at a particu1ar memory means output D controls the associated switch means S to be on, or closed, condition. For the particular embodiment shown, the memory means inputs A, memory means output D and switch means S closures assume the sequence shown in the following tableO
TABLE I .
, .. .. _ A2 Al A~ D0 Dl D2 D3 D4 Sl S2 S3 S4 S5 0 0 0 1l 0 0 0 l ON OFF OFF OFF ON
o 0 1 0 0 0 1 1 ON ON OFF OFF OFF

~ D-12~3 It will be seen that a complet.e cycle through the table thus occurs at l/(~N~l) of the com~utating switeh driYe frequency~ whereby a full cycle of switching of ~he input ~ignal to the various nodes and associa~ed capacitors os occurs at the desired frequency fO of the periodic signal to ~e fitered. The commutat~d wave is applied .
to each of the capacitors for the same N/(2N~l) portlon of the input fre~uency waveshape on each cycle o the inpu~ signal. Since the values of the inpu resis .-tances Rl-R5 (~r R in the general ca~e) are the same, the voltages across each of the capacitors Cl-CS re ch equilibrium at different voltases, in a number of desired frequency waveform cycles dependent upon the desired frequency sO, series resistance R and shun~ capacitance C.
As illustrated in Figure 2, the first capacitor Cl is connected to the input at the start of time in~erval Tl, after some delay time d after the positive-going zero crossing of each cycle~ Delay time d is totally arbitrary and does not affect operation of the commutating filter 10 It will be seen that first capacitor Cl, being connected during time interval Tl, receives only positive-polarity portions of the input wave and therefore e~uilibrates at some positive D.C, voltage. Capacitor C2 is connected to the input during time interval T2 (commencing midway through the first capacitor time interval Tl), has both positive-polarity and negative-polarity portions . .

. RD 12663 of the input wave applied thereto and equilibrates, in the illustrated example, at a positive polarity voltage lower than the po~itive polarity equilibrium voltage on capacitor Cl. Similarlyt capacitor C3r 05 connec~ed to the input d~ring . ime interval T3 ~commencing at the termination of time intlerval Tl, which is the mid-point of .time interval T2), receives both positive~
polari~y and nega~ive-polarity portions of the signal~
as the neg~ive-polarity portion is here greater than the positive-polari~y por~ion, a negative polarity equilibrium voltage appears across capacitor C3. The equilibrium voltage a~ross capacitor C4 is also of negative-polarity, as capacitor C4 i~ connected to the input during time interval T4 (commencing at the termination of time interval T2 and the mid-poin~ of time interval T3~, during which time interval capacitor C~ receives a greater negative-polarity portion of the input wave then a positive~polarity portion. Capacitor C5 is connected to the input during time interval T5 (commencing at the termination of time interval T3 and at the mid-point of time interval T4) and receives a positive-polarity input wave portion slightly larger than the negative-polarity input wave portion received, whereby the equilibrium voltage across capacitor C5 is positive. It will be seen that, midway through time interval 1'5, switch Sl again closes and connects capacitor Cl to the input at the start of the next KD~12663 first capacitor time interval T~'~ which time interval commences at ~he delay time d after the positive~going zero crossing of the nex~ input wave cycle. ~llustratively, if the peak magnitude of the inpu~ waveform is I volt 05 (or 2 volts peak-to-peak~ a~ the filter center frequency fO, and each capacitor is connlected to the same ~wo-fifths of the input wave on each cycle of ~he input si~nal~ the eguilibrium, or averaget voltages across capacitors Cl-C5 will respec~ively be ~0.754 volts, +0.233 volts~ -0.610 volts, -0.610 volts and ~0.2~3 vo~ts.
A differentia1 amplifier 17has the non-inverting+ input 17a therecf connected to a maximum bus Mthrough aresis~or Ra, andhas the inverting - input 17b t~ereof connected to aminimumbus m thr~ughanotherresistor Ra. A first plurality (2~+1~ of diodes each have the cathode thereof conrlected to maximum bus M, with each anode being connected to a different one of the node-shunt capacitance-junctions. Thust . a first diode DlM as its anode connected to node Nl and capacitor Cl, while diodes D2M-~5M respectively have individual anodes individually connected to respective associated nodes N2-N5 and respective associated capacitors C2-CS. Another plurality (2N~I) of diodes have their anodes all connected to minimum bus m with each cathode 2S being connected to a different junction of an associated one of the (2N~l) nodes and associated (2N+I) capacitances.
Thus, a first diode Dlm has the cathode thereof connected _g_ ~D~ 3 to node Nl and capacitive Cl t while the cathodes of diodes D2m-D5m are respectively individually connect~d to the associated one of node~ N2~N5 and the associated one of shunt capacitance C2-C5. The output 17c of 05 differentia1 amp1ifier 17 ~g connected through a feedback resistor Ra to input L7b and also to ~he commutating fi1ter outpu~ te~mina1 10c to provide an outpu~ vo1tage VO with respect to ground potential output terminal lOd.
When the input fre~uency is ~ubstan~ially equal to the fil ter frequency fO set by the fres~uen~:y of the digi~al control signal at control inpu~ 12a, that capacitor having the largest positive-polarity equili~rium voltage thereacross will cause the associated one of the maximum diodes to conduct and place that maximum-positive-polarity voltagè upon maximum bus M. In the illustrative example, the maximum voltage is across capacitance Cl, whereby associated diode DlM conducts and a voltage of ~0.754 volts appears at differential . amplifier non-inverting input l7a. Similarly, when the input waveform is substantially at the programmed filter waveform frequency fO, that one of the filter capacitances having the greatest magnitude of negative-polarity voltage thereacross causes the associa~ed one of the minimum diodes to conduct to place the greatest magnitude of negative~polarity voltage on minimum bus m.
Thus, in the illustrative example, both capacitances C3 and C4 have the same average voltage of -0.610 volts ~hereon, whereby either of the associated diodes D3m ~ RD~ 63 or D4m conduct and the -0~610 volts signal appears at differential amplifier inverting input 17b. The magnitude V~ of the output signal at differential amplifier outpu~ 17c, and ~herefore a~ the filter output ~erminal 10c, OS is therefore ~he difference between the positive-po1arity maximum bus M signal and the negative-polarity minimum bus m siynal, e.g. (0~75~ 0~610)3=1~364 volts for ~he l volt peak input sine waYe condition~ ~s the ~ignal on busses M and m are both D~ C. Ievels, the output signal Vo is also a D. C level.
When the input waveform frequency is much di~ferent from the programmed frequency fO, the filter capacitors average across a diffecent portion of the input sine wave during each commutation cyc-le and the ~verage voltage level across each capacitor falls toward zero magnitude; the resultant output signal Vo therefore tends toward a zero magnitude. Therefore, in operation, on!y if the signal applied between input terminals lOa and lOb is at, or close to, the programmed frequency fO, will a positive D.C. voltage appear at output terminal lOc, with respect to terminal lOd. It will be seen that the center frequency of filter 10 is easily changed, typically over a three order-of-magnitude (1000:1) range, by changing the frequency of the (~N~l) fO
transitions o~ the commutating switch drive circuitry input signal, at input terminal l2a.
It will also be seen that the effective bandwidth of the ilter and the center-frequency detection time ~ D-12663 will be dependent upon the particular values chosen for the input resistances R~ e.g. resistance elements Rl-R5, and for the filter capacity C, e~g. equa1 capaci-tances Cl -C5; typical bandwidths of 1.8% and tone detection U5 times of 50 milli-seconds, are obtainable, with either sine or squarewave input signals.
It will also be seen khat the ~olari~y of thP
output D. ~O leve~ can be reversed by rev~rsing connect of the maximum M and minimum m busses to inputs 17a and 17b.
The entire capacitive commutating filter 10 may be easily integrated in~o a single semiconductor integrated circuit/ if the end use so re~uires, and that such integrated circuit would be a low cost implementation reguiring no tuning, and ~tilizable in an extreme1y broad range of apptications.
While one presently preferred embodiment of my novel capacitive commutating filter has been described herein, many modifications and variations will now become apparent to those skilled in the art. It is my intent, therefore, to be limited only by the scope of the appending c1aims and not by the particular details presented by way of description herein.

Claims (10)

The embodiments of the invention in which an exclu-sive property or privilege is claimed are defined as follows:

1. A commutating filter for detecting the presence of a waveform substantially at a selected frequency, comprising:
input terminal means for receiving the waveform;
output terminal means;
a differential amplifier having an inverting input, a non-inverting input and an output connected to said output terminal means;
a first plurality N, where N is an integer greater than one, of resistance elements each having a first terminal and a second terminal;
a second plurality 2N + 1 of capacitive filter elements;
means responsive to said selected frequency for simultaneously connecting, in sequential but overlapping and cyclical manner, N adjacent ones of said capacitive filter elements each in series with an associated one of the plurality N of resistance elements to the signal at said input terminal means to cause D.C. equilibrium voltages to appear across each of said capacitive filter elements only when the input terminal waveform has a frequency substantially equal to the selected frequency;
means for respectively coupling only the greatest positive-polarity and negative-polarity D.C. equilibrium voltages established across different ones of the plurality of capacitive filter elements selected ones of the differential amplifier inputs to cause a D.C. voltage of level proportional to the amplitude of the selected frequency waveform to appear at said output terminal means.

2. The filter of claim 1, wherein said coupling means includes: a plurality 2N + 1 of diodes each connected from a different one of the capacitive filter elements to provide the maximum positive-polarity voltage on any one thereof to one of said differential amplifier inputs; and another plurality 2N + 1 of diodes each connected from a different one of the capacitive filter elements to provide the maximum or negative-polarity voltage on any one thereof to the remaining one of said differential amplifier inputs.

3. The filter of claim 2, wherein the maximum positive-polarity voltage is connected to the non-inverting input of the differential amplifier and the maximum negative-polarity voltages is connected to the inverting input of the differential amplifier.

4. The filterof claim 3, wherein the output voltage magnitude is equal to the sum of the absolute values of the voltages at the differential amplifier inverting and non-inverting inputs.

5. The filter of claim 1, wherein the number of resistive element is 2N + 1 and said connecting means includes:
a plurality of 2N + 1 of switching devices, each in series with one of said plurality 2N + 1 of resistive elements between said input terminal means and a different one of the capacitive filter elements; and means for closing each of the plurality of switch means for N/(2N + 1)ths of the time interval corresponding to said selected frequency, with closure of each of said switching devices occurring after completion of one-half of the closed time interval of the immediately previously-closed switching device.

6. The filter claim 5, wherein said closing means is responsive to a digital signal having a characteristic periodically occurring at 2N + 1 times the selected frequency.

7. The filter of claim 6, wherein the closing means includes means for dividing the periodically occurring characteristic to provide 2N + 1 output states during each cycle of the selective frequency waveform; and means for closing N selected ones of the switching devices each responsive to selected ones of the dividing means output states.

8. The filter of claim 7, wherein N = 2.

9. The filter of claim 7, wherein said selective closing means is a read-only memory storing a plurality (2N + 1) words each having 2N + 1 data bits.

10. The filter of claim 5, wherein said switching means includes a plurality of field-effect transistors.