CN112822129A - PCIe switching equipment - Google Patents

PCIe switching equipment Download PDF

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Publication number
CN112822129A
CN112822129A CN202110160866.9A CN202110160866A CN112822129A CN 112822129 A CN112822129 A CN 112822129A CN 202110160866 A CN202110160866 A CN 202110160866A CN 112822129 A CN112822129 A CN 112822129A
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dat
chip
pins
sfp
interface
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CN202110160866.9A
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Chinese (zh)
Inventor
朱珂
赵玉林
张波
徐庆阳
方旭升
汪欣
谭力波
王盼
王锐
钟丹
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Jingxin Microelectronics Technology Tianjin Co Ltd
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Jingxin Microelectronics Technology Tianjin Co Ltd
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Priority to CN202110160866.9A priority Critical patent/CN112822129A/en
Publication of CN112822129A publication Critical patent/CN112822129A/en
Priority to CN202210059122.2A priority patent/CN114301854B/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/109—Integrated on microchip, e.g. switch-on-chip
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Information Transfer Systems (AREA)

Abstract

The invention provides PCIe switching equipment, which comprises a switching chip, and a plurality of SFP + interfaces and QSFP + interfaces which are connected with the switching chip, wherein the number of the SFP + interfaces is multiple; one path of SFP + interface is connected with an external processor through a DAC passive cable and used as PCIe Root equipment, and other interfaces are downlink ports and are connected with an external exchange chip or PCIe EP equipment through the DAC passive cable. The PCIe exchange equipment board card carries a PCIe Gen2 exchange chip and supports at most 11 downlink channels, so that one PCIe RC of one processor can manage a plurality of high-speed ETH and SRIO exchange chips with PCIe configuration interfaces or other PCIe EP equipment.

Description

PCIe switching equipment
Technical Field
The invention belongs to the technical field of switches, and particularly relates to PCIe switching equipment.
Background
PCI express (peripheral component interconnect express) is a high-speed serial computer expansion bus standard, PCIe for short, proposed by intel in 2001, and is intended to replace the old PCI, PCI-X, and AGP bus standards.
The defects of the prior art are as follows:
at present, more and more chips, especially high-speed serial switch chips, such as ethernet and RapidIO switch chips, adopt PCIe as their configuration management and channels for sending and issuing on a protocol stack, and such switch chips are often used in a multi-device networking manner, while processor single chips on the market have only limited PCIe interfaces, which may not be enough in number to meet the number of switch chips in a system, and the use of multiple processors sometimes wastes a little, no matter in terms of cost or power consumption; at this time, a PCIe switch device is needed to extend the PCIe bus, and a processor is used as an RC to manage multiple EP devices and send their protocol stacks.
In some PCIe-related product development or chip development processes, a standard card-plug connection manner may be inconvenient, and particularly, some FPGA development boards or prototype verification boards are relatively large in volume and weight, and may be more inconvenient to plug into some processor (Root) systems as an EP (gold finger); in addition, with the increase of the chip scale, the stacking thickness of the PCB is often larger, and the thickness of a golden finger required by PCIe (peripheral component interconnect express) is required to be 1.6mm, so that the PCB needs to be specially processed, and the board manufacturing difficulty and cost are increased.
Disclosure of Invention
In view of the above, the present invention is directed to a novel PCIe switch device to overcome the above-mentioned drawbacks.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
PCIe switching equipment comprises a switching chip, and a plurality of SFP + interfaces and a QSFP + interface which are connected with the switching chip;
one path of SFP + interface is connected with an external processor through a DAC passive cable and used as PCIe Root equipment, and other interfaces are downlink ports and are connected with an external exchange chip or PCIe EP equipment through the DAC passive cable.
Further, the exchange chip is an 89HPES12NT12G2 chip.
Further, the number of the SFP + interfaces is 8;
each SFP + interface is correspondingly provided with an optical fiber connector;
the RX-DAT +, RX-DAT-, TX-DAT +, TX-DAT-pins of the optical fiber connector of one SFP + interface are respectively connected with the PE00TN0, PE00TP0, PE00RN0 and PE00RP0 pins of the 89HPES12NT12G2 chip;
the RX-DAT +, RX-DAT-, TX-DAT +, TX-DAT-pins of the optical fiber connector of one SFP + interface are respectively connected with the PE01TN0, PE01TP0, PE01RN0 and PE01RP0 pins of the 89HPES12NT12G2 chip;
the RX-DAT +, RX-DAT-, TX-DAT +, TX-DAT-pins of the optical fiber connector of one SFP + interface are respectively connected with the pins PE02TN0, PE02TP0, PE02RN0 and PE02RP0 of the 89HPES12NT12G2 chip;
the RX-DAT +, RX-DAT-, TX-DAT +, TX-DAT-pins of the optical fiber connector of one SFP + interface are respectively connected with the PE03TN0, PE03TP0, PE03RN0 and PE03RP0 pins of the 89HPES12NT12G2 chip;
the RX-DAT +, RX-DAT-, TX-DAT +, TX-DAT-pins of the optical fiber connector of one SFP + interface are respectively connected with the pins PE08TN0, PE08TP0, PE08RN0 and PE08RP0 of the 89HPES12NT12G2 chip;
the RX-DAT +, RX-DAT-, TX-DAT +, TX-DAT-pins of the optical fiber connector of one SFP + interface are respectively connected with PE09TN0, PE09TP0, PE09RN0 and PE09RP0 pins of the 89HPES12NT12G2 chip;
the RX-DAT +, RX-DAT-, TX-DAT +, TX-DAT-pins of the optical fiber connector of one SFP + interface are respectively connected with the PE10TN0, PE10TP0, PE10RN0 and PE10RP0 pins of the 89HPES12NT12G2 chip;
the RX-DAT +, RX-DAT-, TX-DAT +, TX-DAT-pins of the optical fiber connector of one SFP + interface are respectively connected with the PE11TN0, PE11TP0, PE11RN0 and PE11RP0 pins of the 89HPES12NT12G2 chip.
Further, the number of the QSFP + interfaces is 1;
the QSFP + interface adopts a QSFP-1888968 connector;
RX1P, RX1N, RX2P, RX2N, RX3P, RX3N, RX4P, RX4N, TX1P, TX1N, TX2P, TX2N, TX3P, TX3N, TX4P and TX4N pins of the QSFP-1888968 connector are respectively connected with PE16TN0, PE16TP0, PE17TN0, PE17TP0, PE18TN0, PE18TP0, PE19TN0, PE19TP0, PE16RN0, PE16RP0, PE17RN0, PE17RP0, PE18RN0, PE18RP0, PE19RN0 and PE19 0 pins of 89HPES 12G2 chips.
Furthermore, the system also comprises a Config module used for controlling the working mode of the switching chip, and the Config module is connected with the switching chip.
Furthermore, the power supply circuit is used for supplying power to the exchange chip and the interface.
Furthermore, the system also comprises a clock circuit, and the clock circuit is connected with the switching chip.
Further, the clock circuit comprises an 8T49N0041 chip, and pins Q0, NQ0, Q1 and NQ1 of the chip are respectively connected with pins GCLKP0, GCLKN0, GCLKP1 and GCLKN1 of the 89HPES12NT12G2 chip.
Compared with the prior art, the PCIe switching equipment provided by the invention has the following advantages:
(1) the PCIe exchange equipment board card carries a PCIe Gen2 exchange chip and supports at most 11 downlink channels, so that one PCIe RC of one processor can manage a plurality of high-speed ETH and SRIO exchange chips with PCIe configuration interfaces or other PCIe EP equipment.
(2) The PCIe exchange device board card is connected with external uplink or downlink devices by adopting a DAC cable of an SFP +/QSFP + interface, and most of FPGA prototype verification boards or other development boards used in the chip development process are provided with the interfaces of the SFP + or QSFP +, so that the PCIe exchange device board card and the FPGA prototype verification boards are very convenient to interconnect, and the problem of inconvenience in plug-in connection of a PCIe connector in the development process is solved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the invention without limitation. In the drawings:
FIG. 1 is a schematic block diagram of a PCIe switching device according to an embodiment of the present invention;
FIG. 2 is a first partial structure diagram of a switch chip according to an embodiment of the present invention;
FIG. 3 is a second partial structure diagram of a switch chip according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of an SFP + interface according to an embodiment of the present invention;
FIG. 5 is a circuit diagram of a QSFP + interface according to an embodiment of the present invention;
fig. 6 is a circuit diagram of a power supply module according to an embodiment of the present invention;
fig. 7 is a clock circuit diagram according to an embodiment of the present invention.
Detailed Description
It should be noted that the embodiments and features of the embodiments of the present invention may be combined with each other without conflict.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in the orientation or positional relationship indicated in the drawings, which are merely for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be construed as limiting the invention. Furthermore, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the invention, the meaning of "a plurality" is two or more unless otherwise specified.
In the description of the invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted", "connected" and "connected" are to be construed broadly, e.g. as being fixed or detachable or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the creation of the present invention can be understood by those of ordinary skill in the art through specific situations.
The invention will be described in detail with reference to the following embodiments with reference to the attached drawings.
As shown in fig. 1, a PCIe switch device includes a switch chip, and a plurality of SFP + interfaces and a QSFP + interface connected to the switch chip;
one path of SFP + interface is connected with an external processor through a DAC passive cable and used as PCIe Root equipment, and other interfaces are downlink ports and are connected with an external exchange chip or PCIe EP equipment through the DAC passive cable.
The exchange chip is 89HPES12NT12G2 chip.
The number of the SFP + interfaces is 8;
each SFP + interface is correspondingly provided with an optical fiber connector;
the RX-DAT +, RX-DAT-, TX-DAT +, TX-DAT-pins of the optical fiber connector of one SFP + interface are respectively connected with the pins PE00TN0, PE00TP0, PE00RN0 and PE00RP0 of the 89HPES12NT12G2 chip, as shown in FIG. 3 and FIG. 4;
the RX-DAT +, RX-DAT-, TX-DAT +, TX-DAT-pins of the optical fiber connector of one SFP + interface are respectively connected with the PE01TN0, PE01TP0, PE01RN0 and PE01RP0 pins of the 89HPES12NT12G2 chip;
the RX-DAT +, RX-DAT-, TX-DAT +, TX-DAT-pins of the optical fiber connector of one SFP + interface are respectively connected with the pins PE02TN0, PE02TP0, PE02RN0 and PE02RP0 of the 89HPES12NT12G2 chip;
the RX-DAT +, RX-DAT-, TX-DAT +, TX-DAT-pins of the optical fiber connector of one SFP + interface are respectively connected with the PE03TN0, PE03TP0, PE03RN0 and PE03RP0 pins of the 89HPES12NT12G2 chip;
the RX-DAT +, RX-DAT-, TX-DAT +, TX-DAT-pins of the optical fiber connector of one SFP + interface are respectively connected with the pins PE08TN0, PE08TP0, PE08RN0 and PE08RP0 of the 89HPES12NT12G2 chip;
the RX-DAT +, RX-DAT-, TX-DAT +, TX-DAT-pins of the optical fiber connector of one SFP + interface are respectively connected with PE09TN0, PE09TP0, PE09RN0 and PE09RP0 pins of the 89HPES12NT12G2 chip;
the RX-DAT +, RX-DAT-, TX-DAT +, TX-DAT-pins of the optical fiber connector of one SFP + interface are respectively connected with the PE10TN0, PE10TP0, PE10RN0 and PE10RP0 pins of the 89HPES12NT12G2 chip;
the RX-DAT +, RX-DAT-, TX-DAT +, TX-DAT-pins of the optical fiber connector of one SFP + interface are respectively connected with the PE11TN0, PE11TP0, PE11RN0 and PE11RP0 pins of the 89HPES12NT12G2 chip.
The number of the QSFP + interfaces is 1;
the QSFP + interface adopts a QSFP-1888968 connector;
as shown in fig. 3 and 5, RX1P, RX1N, RX2P, RX2N, RX3P, RX3N, RX4P, RX4N, TX1P, TX1N, TX2P, TX2N, TX3P, TX3N, TX4P, TX4N pins of QSFP-1888968 connector are respectively connected with PE16TN0, PE16TP0, PE17TN0, PE17TP0, PE18TN0, PE18TP0, PE19TN0, PE19TP0, PE16RN0, PE16RP0, PE17RN0, PE17RP0, PE18RN0, PE18RP0, PE19RP0, and PE19RP0 of the hpfp 12G2 chip.
The system also comprises a Config module used for controlling the working mode of the switching chip, and the Config module is connected with the switching chip.
And the power supply circuit is used for supplying power to the switching chip and the interface, and the power supply circuit is shown in fig. 6.
The switching chip is used for providing a switching signal for the switching chip; the clock circuit comprises an 8T49N0041 chip, and as shown in FIGS. 2 and 7, pins Q0, NQ0, Q1 and NQ1 of the chip are respectively connected with pins GCLKP0, GCLKN0, GCLKP1 and GCLKN1 of a 89HPES12NT12G2 chip.
The application takes 89HPES12NT12G2 of IDT as a switching chip, which supports 12 ports and 12 lanes at most, wherein 8 ports can be flexibly configured into 8 x1, 4 x2, 2 x4 and 1 x 8. SerDes supports 5GT/s maximum, i.e., supports PCIe Gen2 exchange at the highest, and is backward compatible with Gen 1. The uplink port is externally led through an SFP + interface, and PCIe cannot be transmitted through a common optical module and an optical fiber, so that a DAC (direct Attach Cable) passive cable of the SFP + interface is used for connecting an external processor and is used as a Root device of the PCIe; and other ports are all downlink ports and are connected with an external exchange chip or other PCIe EP equipment through a DAC cable.
The board is also provided with a power supply module for supplying power to the whole board device and a clock module for supplying a clock to the exchange chip. The function of the Config module is to configure the switching chip to operate in a required mode.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and should not be taken as limiting the invention, so that any modifications, equivalents, improvements and the like, which are within the spirit and principle of the present invention, should be included in the scope of the present invention.

Claims (8)

1. A PCIe switch device, characterized in that: the system comprises a switching chip, and a plurality of SFP + interfaces and a plurality of QSFP + interfaces which are connected with the switching chip;
one path of SFP + interface is connected with an external processor through a DAC passive cable and used as PCIe Root equipment, and other interfaces are downlink ports and are connected with an external exchange chip or PCIe EP equipment through the DAC passive cable.
2. The PCIe switch device of claim 1, wherein: the exchange chip is 89HPES12NT12G2 chip.
3. The PCIe switch device of claim 2, wherein: the number of the SFP + interfaces is 8;
each SFP + interface is correspondingly provided with an optical fiber connector;
the RX-DAT +, RX-DAT-, TX-DAT +, TX-DAT-pins of the optical fiber connector of one SFP + interface are respectively connected with the PE00TN0, PE00TP0, PE00RN0 and PE00RP0 pins of the 89HPES12NT12G2 chip;
the RX-DAT +, RX-DAT-, TX-DAT +, TX-DAT-pins of the optical fiber connector of one SFP + interface are respectively connected with the PE01TN0, PE01TP0, PE01RN0 and PE01RP0 pins of the 89HPES12NT12G2 chip;
the RX-DAT +, RX-DAT-, TX-DAT +, TX-DAT-pins of the optical fiber connector of one SFP + interface are respectively connected with the pins PE02TN0, PE02TP0, PE02RN0 and PE02RP0 of the 89HPES12NT12G2 chip;
the RX-DAT +, RX-DAT-, TX-DAT +, TX-DAT-pins of the optical fiber connector of one SFP + interface are respectively connected with the PE03TN0, PE03TP0, PE03RN0 and PE03RP0 pins of the 89HPES12NT12G2 chip;
the RX-DAT +, RX-DAT-, TX-DAT +, TX-DAT-pins of the optical fiber connector of one SFP + interface are respectively connected with the pins PE08TN0, PE08TP0, PE08RN0 and PE08RP0 of the 89HPES12NT12G2 chip;
the RX-DAT +, RX-DAT-, TX-DAT +, TX-DAT-pins of the optical fiber connector of one SFP + interface are respectively connected with PE09TN0, PE09TP0, PE09RN0 and PE09RP0 pins of the 89HPES12NT12G2 chip;
the RX-DAT +, RX-DAT-, TX-DAT +, TX-DAT-pins of the optical fiber connector of one SFP + interface are respectively connected with the PE10TN0, PE10TP0, PE10RN0 and PE10RP0 pins of the 89HPES12NT12G2 chip;
the RX-DAT +, RX-DAT-, TX-DAT +, TX-DAT-pins of the optical fiber connector of one SFP + interface are respectively connected with the PE11TN0, PE11TP0, PE11RN0 and PE11RP0 pins of the 89HPES12NT12G2 chip.
4. The PCIe switch device of claim 2, wherein: the number of the QSFP + interfaces is 1;
the QSFP + interface adopts a QSFP-1888968 connector;
QSFP-RX1P, RX1N, RX2P, RX2N, RX3P, RX3N, RX4P, RX4N, TX1P, TX1N, TX2P, TX2N, TX3P, TX3N, TX4P, TX4N pins of the 1888968 connector are connected to PE16TN0, PE16TP0, PE17TN0, PE17TP0, PE18TN0, PE18TP0, PE19TN0, PE19TP0, PE16RN0, PE16RP0, PE17RN0, PE17RP0, PE18RN0, PE18RP0, PE19RN0, PE19RP0 pins of the 89HPES12NT12G2 chip, respectively.
5. The PCIe switch device of claim 1, wherein: the system also comprises a Config module used for controlling the working mode of the switching chip, and the Config module is connected with the switching chip.
6. The PCIe switch device of claim 1, wherein: and the power supply circuit is used for supplying power to the switching chip and the interface.
7. The PCIe switch device of claim 2, wherein: the circuit also comprises a clock circuit, and the clock circuit is connected with the switching chip.
8. The PCIe switch device of claim 7, wherein: the clock circuit comprises an 8T49N0041 chip, and pins Q0, NQ0, Q1 and NQ1 of the chip are respectively connected with pins GCLKP0, GCLKN0, GCLKP1 and GCLKN1 of a 89HPES12NT12G2 chip.
CN202110160866.9A 2021-02-05 2021-02-05 PCIe switching equipment Pending CN112822129A (en)

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CN202210059122.2A CN114301854B (en) 2021-02-05 2022-01-19 PCIe switching device

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Application publication date: 20210518