CN114996193A - Computer supervision and front-end processor system - Google Patents
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
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- G—PHYSICS
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- G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
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- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/11—Arrangements specific to free-space transmission, i.e. transmission through air or vacuum
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Abstract
The invention discloses a computer supervision and front-end processor system, which belongs to the technical field of computers and comprises at least one computer, wherein the computer is respectively in signal connection with a digital-to-analog converter or an analog-to-digital converter through a data interface and signal modulation, the output end of the analog-to-digital converter is connected with the input end of a processing system, the output end of the processing system is connected with the input end of the digital-to-analog converter, the processing system comprises at least one connector, at least one SFP converter and at least one FPGA chip, the input end and the output end of the connector are connected with the FPGA chip, the input end and the output end of the FPGA chip are connected with the SFP converter, and the sending end of the SFP converter converts an electric signal into an optical signal; according to the method, the traditional network transmission technology is replaced by the visible light technology, the visible light technology is integrated with the front-end processor, the most competitive means for solving the problems of high communication speed, high density, deep coverage and the like including 5G is achieved, and the management and control of the terminal are facilitated by a computer.
Description
Technical Field
The invention belongs to the technical field of computers, and particularly relates to a computer supervision and front-end processor system.
Background
The front-end processor, also known as a communications controller, has the primary function of releasing the host to run applications. Thus, the host is not continuously interfered by the external device, thereby more effectively processing the application program. It may be a complex front-end mainframe computer interface or a simple device such as a multiplexer, bridge, and router. These devices convert the parallel data of the computer into serial data for transmission over the communication line and perform all necessary control functions, error detection and synchronization. Modern devices also perform data compression, routing, security, etc., and collect management information. The front-end processor is typically a small or mini-computer dedicated to the data communication and control functions of the large backbone computer. The front-end processor can control network access and allow a registered user to use the system; information is prior; registering all data communication activities; recording all network activities; routing information between network links greatly releases the data communication control function of a large-scale backbone computer, so that an upper computer can engage in other information processing tasks.
The basic principle of visible light communication is that under the premise of normal illumination, information is modulated into visible light and is emitted by an LED lamp. A receiving end converts visible light into an electric signal by using a Photoelectric Detector (PD) and demodulates corresponding modulation information from the electric signal; based on visible light communication, the FPGA-DA provides a perfect solution from over-fast hardware to high-speed AD. The hardware block diagram of the indoor LED visible light high-speed digital communication system is shown in FIG. 3. The left solid-line frame is a digital signal part and mainly comprises a PC data source, a data interface, a baseband processor and a DAC/ADC module, wherein the last three modules are integrated on a baseband processing board. The dotted line portion on the right side of fig. 3 is an analog signal, and mainly includes an LED driving circuit, an LED, an optical channel, a lens, a blue filter, a photodiode, and a photo processing circuit.
In order to increase the data transmission rate of the system as much as possible, additional measures need to be taken to mitigate the impact of the physical device-limited system bandwidth. Effective mitigation measures can be generalized into two categories, one is to use additional components or to use equalization techniques to mitigate the effects. The specific method includes using a blue filter to filter out yellow light elements at the receiving end and the response speed is slow, using the LED driver circuit module and the second method is to use a more efficient modulation technique, i.e. the propagation symbol can convey as much information as possible.
At present, the front-end processor system adopts the traditional information transmission technology to realize information interaction, and the problems of transmission speed, coverage depth and coverage density of the current optical fiber network are objective, so that a computer supervision and front-end processor system is provided.
Disclosure of Invention
The present invention is directed to a computer supervision and front-end processor system, which solves the above problems.
In order to achieve the purpose, the invention adopts the following technical scheme: a computer supervision and front-end processor system comprises at least one computer, wherein the computer is respectively in signal connection with a digital-to-analog converter or an analog-to-digital converter through a data interface and signal modulation, the output end of the analog-to-digital converter is connected with the input end of a processing system, the output end of the processing system is connected with the input end of the digital-to-analog converter, the processing system comprises at least one connector, at least one SFP converter and at least one FPGA chip, the input end and the output end of the connector are connected with the FPGA chip, the input end and the output end of the FPGA chip are connected with the SFP converter, the sending end of the SFP converter converts an electric signal into an optical signal, a receiving end converts the optical signal into the electric signal after the optical signal is transmitted through an optical fiber, the input end of the analog-to-digital converter is connected with the connector, and the output end of the connector is connected with the digital-to-analog converter, and an application program uses a visible light technology to replace a traditional network transmission technology, and the visible light technology and a front-end processor are integrated, which is a high-speed, high-density, deep report and the like with most competitive means for solving the current problems, including 5 grams, and is convenient for a computer to supervise and control a terminal.
Further, the processing system further comprises at least one crystal oscillator, a clock buffer, a memory, a JTGA interface, a flash memory, an auxiliary power interface, a power supply, and a PCI-E interface.
Furthermore, the connector comprises a daughter board module and a carrier card, the daughter board module and the carrier card are connected through the connector, the connector on the daughter board module uses a male socket, the connector on the carrier card uses a female socket, the pins of the carrier card connector are connected with the pins of the FPGA chip through PCB design, and the pins of the connector on the daughter board module are connected with the IO interface through PCB design.
Further, the output end of the crystal oscillator is connected with the input end of a clock buffer, the output end of the clock buffer is connected with the input end of the FPGA chip, the output end of the memory is connected with the FPGA chip, and the output end of the FPGA chip is connected with the memory.
Furthermore, the output end of the FPGA chip is connected with a JTGA interface, and the output end of the JTGA interface is connected with the input end of the FPGA chip.
Further, the power supply supplies power to the processing system.
Furthermore, the output end of the PCI-E interface is connected with the input end of the FPGA chip, and the input end of the FPGA chip is connected with the input end of the PCI-E interface.
Furthermore, the computer further comprises a first computer and a second computer, wherein the output end of the first computer is connected to the input end of the first data interface, the output end of the first data interface is connected to the input end of the first signal modulation part, and the output end of the first signal modulation part is connected to the ADC.
Furthermore, the output end of the processing system is connected to the DAC, the output end of the processing system is connected to the input end of the second signal modulation part, and the output end of the second signal modulation part is connected to the second computer through the second data interface.
Furthermore, the front end of the ADC is provided with the AD, and the rear end of the DAC is provided with the DA.
Compared with the prior art, the invention has the beneficial effects that:
the method and the system use the visible light technology to replace the traditional network transmission technology, integrate the visible light technology with the front-end processor, solve the problems of high communication speed, high density, deep coverage and the like including 5G, and are the most competitive means, so that a computer can conveniently supervise and control the terminal; meanwhile, the system can provide indoor positioning service for large buildings, underground parking lots, coal mines and the like, provides an information service system based on position ID for supermarket shopping guide, museum explanation, advertisement push and online-offline binding service, can effectively meet the wireless mobile communication requirements of electromagnetic sensitive or high-density electronic equipment areas such as hospitals, cabins, ships, mines, roads, gas stations and oil depots, and can realize millimeter-level positioning accuracy and high-precision control and measurement through the LED array. The underwater acoustic communication system has wide application prospects in the fields of industrial manipulators, household robots and the like, and underwater acoustic communication is a mainstream technology at present, but the transmission rate is low; the attenuation coefficient of the visible light blue green band in the seawater is small, and the realization rate is high; facing to the national ocean strategy, the method is expected to become the mainstream technology of underwater medium-short distance high-speed wireless communication.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention.
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a schematic diagram of the electrical signal conversion of the present invention;
FIG. 3 is a schematic diagram of current visible light technology;
in the figure: 1. AD; 2. an ADC; 3. DA; 4. a DAC; 5. a processing system; 501. a connector; 502. crystal oscillation; 503. a clock buffer; 504. a memory; 505. JTGA interface; 506. flashing; 507. an auxiliary power supply interface; 508. an SFP converter; 509. a power source; 510. an FPGA chip; 511. a PCI-E interface; 6. a first computer; 7. a first data interface; 8. a first signal modulation section; 9. a second signal modulation section; 10. a second data interface; 11. a second computer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", and the like, are used in the orientations and positional relationships indicated in the drawings, which are based on the orientations and positional relationships indicated in the drawings, and are used for convenience of description and simplicity of description, but do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention.
Referring to fig. 1 and 2, the present invention provides a technical solution: a computer supervision and front-end processor system comprises at least one computer, the computer is respectively connected with a digital-to-analog converter or an analog-to-digital converter through a data interface and signal modulation, the output end of the analog-to-digital converter is connected with the input end of a processing system 5, the output end of the processing system 5 is connected with the input end of the digital-to-analog converter, the processing system 5 comprises at least one connector 501, at least one SFP converter 508 and at least one FPGA chip 510, the input end and the output end of the connector 501 are connected with the FPGA chip 510, the connector 501 is composed of a daughter board module and a carrier card, the daughter board module and the carrier card are connected through a connector, the connector on the daughter board module uses a male socket, the connector on the carrier card uses a female socket, the pins of the carrier card connector are connected with the pins of the FPGA chip 510 through PCB design, the pins of the connector on the daughter board module are connected with an IO interface through PCB design, the input end and the output end of an FPGA chip 510 are connected with an SFP converter 508, a transmitting end of the SFP converter 508 converts an electric signal into an optical signal, after the optical signal is transmitted through an optical fiber, a receiving end converts the optical signal into the electric signal, the input end of an analog-to-digital converter is connected into a connector 501, the output end of the connector 501 is connected into the digital-to-analog converter, a novel indoor information network which is high-speed, compatible, green, low-carbon, healthy and safe is constructed by relying on a deep coverage lighting network, the power line communication industry is activated, and downstream industries such as lighting equipment, cables and electric wires are driven; the intelligent traffic management and control system is the most competitive means for solving the problems of high speed, high density and deep coverage in future mobile communication, can provide indoor positioning service for large buildings, underground parking lots, coal mines and the like, provides an information service system based on position ID for supermarket shopping guide, museum explanation, advertisement push, online and offline binding service and the like, can effectively meet the wireless mobile communication requirements of electromagnetically sensitive or electronic equipment intensive areas such as hospitals, engine rooms, ships, mines, highways, gas stations, oil depots and the like, is constructed on the basis of LED lamps, traffic signal lamps and street lamps, and provides a vehicle networking solution for unmanned driving and collision avoidance between vehicles. Other typical applications include lighthouse communications, ship-to-ship communications, outdoor emergency equipment, and the like.
Currently, modulation methods used in visible light communication systems include on-off keying, pulse position modulation, differential pulse position modulation, subcarrier pulse position modulation, variable pulse position modulation, color shift keying, and orthogonal frequency division multiplexing.
In this embodiment, the processing system 5 further includes at least one crystal oscillator 502, a clock buffer 503, a memory 504, a JTGA interface 505, a flash memory 506, an auxiliary power interface 507, a power supply 509, and a PCI-E interface 511, an output end of the crystal oscillator 502 is connected to an input end of the clock buffer 503, an output end of the clock buffer 503 is connected to an input end of the FPGA chip 510, an output end of the memory 504 is connected to the FPGA chip 510, an output end of the FPGA chip 510 is connected to the memory 504, and the power supply 509 supplies power to the processing system 5.
In this embodiment, the output end of the FPGA chip 510 is connected to the JTGA interface 505, and the output end of the JTGA interface 505 is connected to the input end of the FPGA chip 510.
In this embodiment, the output terminal of the PCI-E interface 511 is connected to the input terminal of the FPGA chip 510, and the input terminal of the FPGA chip 510 is connected to the input terminal of the PCI-E interface 511.
Specifically, the computer further includes a first computer 6 and a second computer 11, an output end of the first computer 6 is connected to an input end of the first data interface 7, an output end of the first data interface 7 is connected to an input end of the first signal modulation unit 8, an output end of the first signal modulation unit 8 is connected to the ADC2, an output end of the processing system 5 is connected to the DAC4, an output end of the DA3, which is installed at the rear end of the DAC4, of the processing system 5 is connected to an input end of the second signal modulation unit 9, an output end of the second signal modulation unit 9 is connected to the second computer 11 through the second data interface 10, and an AD1 is installed at the front end of the ADC 2.
The working principle and the using process of the invention are as follows: the system adopts AD1 and DA3 of 1Gsps and an FPGA processing system 5 with the model of XC7V690T, the ADC2 realizes GSPS analog-to-digital conversion of one channel, the ADC2 is ADS5400 and can realize twelve-bit single-channel 1G sampling rate, and through the adoption of the system, an FPGA chip 510 of the system completes the receiving and sending control of data, the configuration of AD1, DA3 and a clock buffer 503, the modulation and demodulation of data are realized, a novel indoor information network which is high-speed compatible, green, low-carbon, healthy and safe is constructed by depending on a deep coverage lighting network, the power line communication industry is activated, and the downstream industries such as lighting equipment, cables, electric wires and the like are driven; the method is the most competitive means for solving the problems of high speed, high density and deep coverage in future mobile communication, can provide indoor positioning service for large buildings, underground parking lots, coal mines and the like, provides an information service system based on position ID for supermarket shopping guide, museum explanation, advertisement push, online-offline binding service and the like, and can realize millimeter-level positioning accuracy by utilizing an LED array based on a photogrammetric principle, thereby realizing high-accuracy control and measurement. The underwater acoustic communication system has wide application prospect in the fields of industrial manipulators, household robots and the like, and the underwater acoustic communication is the mainstream technology at present, but the transmission rate is low; the attenuation coefficient of the visible light blue green band in the seawater is small, and the realization rate is high; facing to the national ocean strategy, the method is expected to become the mainstream technology of underwater medium-short distance high-speed wireless communication.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered as the technical solutions and the inventive concepts of the present invention within the technical scope of the present invention.
Claims (10)
1. A computer supervision and front-end processor system comprises at least one computer, the computer is respectively connected with a digital-to-analog converter or an analog-to-digital converter through a data interface and signal modulation, the computer supervision and front-end processor system is characterized in that the output end of the analog-to-digital converter is connected with the input end of a processing system (5), the output end of the processing system (5) is connected with the input end of the digital-to-analog converter, the processing system (5) comprises at least one connector (501), at least one SFP converter (508) and at least one FPGA chip (510), the input end and the output end of the connector (501) are connected with the FPGA chip (510), the input end and the output end of the FPGA chip (510) are connected with the SFP converter (508), the sending end of the SFP converter (508) converts an electric signal into an optical signal, and after the optical signal is transmitted through an optical fiber, the receiving end converts the optical signal into the electric signal, the input end of the analog-to-digital converter is connected with a connector (501), and the output end of the connector (501) is connected with the digital-to-analog converter.
2. The computer supervisory and front-end processor system of claim 1, wherein: the processing system (5) further comprises at least one crystal oscillator (502), a clock buffer (503), a memory (504), a JTGA interface (505), a flash memory (506), an auxiliary power interface (507), a power supply (509), and a PCI-E interface (511).
3. The computer supervisory and front-end processor system of claim 2, wherein: connector (501) comprises daughter board module, year card two parts, and daughter board module and year are connected by the connector between the card, and the connector uses public seat on the daughter board module, and the connector uses female seat on carrying the card, carries the card connector pin and passes through the PCB design with FPGA chip (510) pin to be connected, and the last connector pin of daughter board module passes through the PCB design with the IO interface to be connected.
4. The computer supervision and front-end processor system according to claim 2, characterized in that: the output end of the crystal oscillator (502) is connected with the input end of a clock buffer (503), the output end of the clock buffer (503) is connected with the input end of an FPGA chip (510), the output end of the memory (504) is connected with the FPGA chip (510), and the output end of the FPGA chip (510) is connected with the memory (504).
5. The computer supervision and front-end processor system according to claim 2, characterized in that: the output end of the FPGA chip (510) is connected with a JTGA interface (505), and the output end of the JTGA interface (505) is connected with the input end of the FPGA chip (510).
6. The computer supervisory and front-end processor system of claim 2, wherein: the power supply (509) supplies power to the processing system (5).
7. The computer supervisory and front-end processor system of claim 2, wherein: the output end of the PCI-E interface (511) is connected with the input end of the FPGA chip (510), and the input end of the FPGA chip (510) is connected with the input end of the PCI-E interface (511).
8. The computer supervision and front-end processor system according to claim 1, characterized in that: the computer further comprises a first computer (6) and a second computer (11), wherein the output end of the first computer (6) is connected with the input end of a first data interface (7), the output end of the first data interface (7) is connected with the input end of a first signal modulation part (8), and the output end of the first signal modulation part (8) is connected with the ADC (2).
9. The computer supervision and front-end processor system according to claim 8, characterized in that: the output end of the processing system (5) is connected with the DAC (4), the output end of the processing system (5) is connected with the input end of the second signal modulation part (9), and the output end of the second signal modulation part (9) is connected with the second computer (11) through the second data interface (10).
10. The computer supervision and front-end processor system according to claim 1, characterized in that: AD (1) is installed to the front end of ADC (2), DA (3) is installed to the rear end of DAC (4).
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102833002A (en) * | 2012-08-23 | 2012-12-19 | 哈尔滨工业大学 | Data transmission device and method supporting fibre channel protocol |
| CN103986680A (en) * | 2014-05-14 | 2014-08-13 | 北京航空航天大学 | Miniaturization dual-channel OFDM communication system and achieving method of miniaturization dual-channel OFDM communication system |
| CN106970894A (en) * | 2017-04-20 | 2017-07-21 | 广东浪潮大数据研究有限公司 | A kind of FPGA isomery accelerator cards based on Arria10 |
| US20170330045A1 (en) * | 2015-10-28 | 2017-11-16 | Dario B. Crosetto | Method and apparatus to build new electronic instruments and devices: the 3d-flow opra to solve applications of fast, real-time, multi-dimension object pattern recognition algorithms (opra) and the 3d-cbs (3-d complete body screening) to accurately measure minimum abnormal biological processes of diseases at an early curable stage such as cancer improving diagnosis and prognoses for maximizing reduction of premature deaths and minimize the cost per each life saved |
| CN207869146U (en) * | 2018-03-05 | 2018-09-14 | 西安彼睿电子科技有限公司 | A kind of FPGA reconfigurable networks processing board |
| US20190278720A1 (en) * | 2018-03-09 | 2019-09-12 | Samsung Electronics Co., Ltd. | Method and apparatus for supporting a field programmable gate array (fpga) based add-in-card (aic) solid state drive (ssd) |
| CN211528250U (en) * | 2019-11-15 | 2020-09-18 | 中国科学院高能物理研究所 | 8-channel high-speed nuclear imaging electronics system based on JESD204 interface |
| CN112822129A (en) * | 2021-02-05 | 2021-05-18 | 井芯微电子技术(天津)有限公司 | PCIe switching equipment |
-
2021
- 2021-06-28 CN CN202110733148.6A patent/CN114996193B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102833002A (en) * | 2012-08-23 | 2012-12-19 | 哈尔滨工业大学 | Data transmission device and method supporting fibre channel protocol |
| CN103986680A (en) * | 2014-05-14 | 2014-08-13 | 北京航空航天大学 | Miniaturization dual-channel OFDM communication system and achieving method of miniaturization dual-channel OFDM communication system |
| US20170330045A1 (en) * | 2015-10-28 | 2017-11-16 | Dario B. Crosetto | Method and apparatus to build new electronic instruments and devices: the 3d-flow opra to solve applications of fast, real-time, multi-dimension object pattern recognition algorithms (opra) and the 3d-cbs (3-d complete body screening) to accurately measure minimum abnormal biological processes of diseases at an early curable stage such as cancer improving diagnosis and prognoses for maximizing reduction of premature deaths and minimize the cost per each life saved |
| CN106970894A (en) * | 2017-04-20 | 2017-07-21 | 广东浪潮大数据研究有限公司 | A kind of FPGA isomery accelerator cards based on Arria10 |
| CN207869146U (en) * | 2018-03-05 | 2018-09-14 | 西安彼睿电子科技有限公司 | A kind of FPGA reconfigurable networks processing board |
| US20190278720A1 (en) * | 2018-03-09 | 2019-09-12 | Samsung Electronics Co., Ltd. | Method and apparatus for supporting a field programmable gate array (fpga) based add-in-card (aic) solid state drive (ssd) |
| CN211528250U (en) * | 2019-11-15 | 2020-09-18 | 中国科学院高能物理研究所 | 8-channel high-speed nuclear imaging electronics system based on JESD204 interface |
| CN112822129A (en) * | 2021-02-05 | 2021-05-18 | 井芯微电子技术(天津)有限公司 | PCIe switching equipment |
Non-Patent Citations (1)
| Title |
|---|
| 徐方晨 等: ""一种FPGA 芯片JTAG 接口切换电路的设计"", 《互联网+安全》, pages 153 - 154 * |
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