CN108062055B - PXIe controller remote control system and method based on optical fiber - Google Patents
PXIe controller remote control system and method based on optical fiber Download PDFInfo
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- CN108062055B CN108062055B CN201711471638.3A CN201711471638A CN108062055B CN 108062055 B CN108062055 B CN 108062055B CN 201711471638 A CN201711471638 A CN 201711471638A CN 108062055 B CN108062055 B CN 108062055B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25197—Optical, glass fiber
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
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Abstract
The invention belongs to the technical field of test and measurement. A remote control system and method of PXIe controller based on optic fibre, include PCIe adapter and PXIe controller connected through PCIe active optical cable; the PCIe adapter comprises a PCIe golden finger, a first PCIe switch and a PCIe connector which are connected in sequence; the first PCIe switch is connected with the external main control computer through PCIe golden fingers; the PXIe controller comprises an upstream port PCIe connector, a downstream port PCIe connector and a second PCIe switch, wherein the second PCIe switch is connected to the PXIe chassis backboard; the second PCIe switch also extends a 1 way x 4PCIe connection to the downstream port PCIe connector; the invention realizes remote control.
Description
Technical Field
The invention belongs to the technical field of test and measurement, and particularly relates to a remote control system and a remote control method for an optical fiber-based PXIe controller, which extend the remote control distance of a traditional coaxial cable-based PXIe controller from a few meters to hundreds of meters and meet the application demands of the increasingly diversified test and measurement fields.
Background
As test applications become more diverse, such as in the fields of missiles, radars, spacecraft, underwater weapons, etc., there is an increasing need for ground systems with high-speed data processing capabilities, transmission bandwidth, and long-range transmission. The PXIe remote controller utilizes a high-bandwidth PCIe technology to realize remote control of the automatic test system by the main control computer. Because the high-speed signal of PCIe Gen3 technology causes serious dielectric loss and high-frequency attenuation along with the increase of transmission rate and distance, the remote control distance of the current coaxial cable-based PXIe controller is limited, and the control distance of a few meters can be realized only, so that the urgent requirement of a test system for long-distance transmission is difficult to meet.
Currently, optical fiber communication is implemented through a Field Programmable Gate Array (FPGA), and there are two main implementations: 1. the GTX/GTH transceiver is an integrated module capable of realizing high-speed serial data receiving and transmitting in the FPGA and supports protocols such as PCIe, optical fiber and gigabit Ethernet without protocol conversion, but at present, most of the protocols comprise PCIe Gen1 (2.5 Gbps)/PCIe Gen2 (5 Gbps) speed and single-channel optical fiber communication, and the requirements on the speed and the number of the GTX/GTH transceivers of the FPGA are high for PCIe Gen3 (8 Gbps) transmission speed and 4-channel optical fiber communication; 2. the method is realized by an FPGA IP core, a high-speed serial transceiver and an optical transceiver module, the PCIe protocol and the optical fiber protocol are required to be converted, and the FPGA IP core is complex to develop.
On the other hand, as shown in fig. 1. A coaxial cable based PXIe controller control system supports a spread spectrum clock (Spread Spectrum Clock) to reduce electromagnetic interference using a Common clock (Common Refclk) approach. In the common clock approach, a 100MHz clock input is obtained from a reference clock source and a reference clock is provided to a plurality of endpoints or ports through zero delay clock buffers. The reference clock source is derived from a 100MHz reference clock (SSC support) of the computer slot, provides a reference clock for the first PCIe switch and PCIe connector through a zero-delay clock buffer, and is transmitted to an upstream port of the PXIe controller through a coaxial cable, and provides a reference clock for the second PCIe switch, downstream port PCIe connector and PXIe chassis backplane through the zero-delay clock buffer.
The PXIe controller control system based on the optical fiber adopts an independent Clock (Separate Clock) mode, and due to the limitation of signal technology, when the link length exceeds 7m, the PCIe standard no longer supports a spread spectrum Clock, and a constant Clock (Constant Frequency Clock) is adopted. In the independent clock mode, clock inputs are obtained from multiple clock sources. As shown in fig. 2, the 100MHz constant clock reference clock is generated by a PCIe clock generator, providing a reference clock through a zero delay clock buffer for the first PCIe switch and PCIe connector. Unlike coaxial cables, the reference clock cannot be transmitted over fiber, so the PXIe controller generates a 100MHz constant clock through the PCIe clock generator, providing the reference clock through the zero delay clock buffer for the second PCIe switch, upstream port PCIe connector, downstream port PCIe connector, and PXIe chassis backplane.
Again, unlike the coaxial cable based PXIe controller control system, the fiber based PXIe controller remote control system has no electrical connection during the fiber transmission process, and the differential transmission signals of each channel of the PCIe adapter cannot detect whether the PXIe controller exists through the common mode pulse, so that the PCIe adapter and the PXIe controller cannot establish a link.
Disclosure of Invention
Aiming at the limitation of the remote transmission distance of the PXIe controller based on the coaxial cable, the invention provides a remote control system and a remote control method of the PXIe controller based on the optical fiber, which utilize the advantages of long transmission distance, high transmission bandwidth, strong anti-interference performance and the like of the optical fiber, greatly prolong the online distance of the PXIe controller and realize the control distance reaching hundreds of meters.
The technical scheme of the invention is as follows:
a remote control system of a PXIe controller based on optical fibers comprises a PCIe adapter and the PXIe controller which are connected through a PCIe active optical cable; the method is characterized in that: the PCIe adapter comprises a PCIe golden finger, a first PCIe switch and a PCIe connector which are connected in sequence; the first PCIe switch is connected with the external main control computer through PCIe golden fingers; the first PCIe switch extends PCIe Gen3×4 signals; the PXIe controller comprises an upstream port PCIe connector, a downstream port PCIe connector and a second PCIe switch, wherein the second PCIe switch expands PCIe Gen3×4 signals transmitted by the upstream port to obtain 4-path×4PCIe signals or 2-path×8PCIe signals, and the 4-path×4PCIe signals are connected to the PXIe chassis backboard; the second PCIe switch also expands 1-way x 4PCIe to be connected to a downstream port PCIe connector, and the downstream port PCIe connector is connected to an upstream port PCIe connector of a PXIe controller of the lower-level chassis through a PCIe active optical cable, so that expansion cascade of the multiple chassis is realized;
the PXIe controller also comprises an FPGA control module, and the FPGA control module is connected with the PXIe chassis backboard through the SMBus controller; the FPGA control module is also connected with the second PCIe switch through a PCIe interface chip;
the PCIe active optical cable is connected with the PCIe adapter and the PXIe controller through connectors at two ends of the PCIe active optical cable, a micro optical transceiver is integrated in the connector, a micro optical transceiver at the connection end of a downstream port of the PCIe adapter or the PXIe controller converts PCIe Gen3×4 signals into optical fiber signals, and a micro optical transceiver at the connection end of an upstream port of the PXIe controller converts the optical fiber signals into PCIe Gen3×4 signals and transmits the PCIe Gen3×4 signals to the PXIe controller;
the PCIe adapter and the PXIe controller also comprise PCIe clock generators which are respectively a transmitting end PCIe clock generator and a receiving end PCIe clock generator, and the transmitting end PCIe clock generator is respectively connected with the PCIe connector and the first PCIe switch through zero delay clock buffers; the receiving end PCIe clock generator is respectively connected with the upstream port PCIe connector, the downstream port PCIe connector and the second PCIe switch through the zero delay clock buffer;
the PCIe adapter also comprises a resistance network simulation common mode pulse detection response unit, wherein one end of the resistance network simulation common mode pulse detection response unit is electrically connected with the first PCIe switch, and the other end of the resistance network simulation common mode pulse detection response unit is electrically connected with the PCIe connector; the resistor network simulation common-mode pulse detection response unit comprises a first branch and a second branch which are connected in parallel on a first PCIe exchange switch and a PCIe connector, wherein the first branch and the second branch comprise two first resistors which are sequentially connected in series, and second resistors are arranged between an input end between the first branch and the second branch and an output end between the first branch and the second branch; differential transmit signal pairs for each lane of PCIe Gen3 x 4 signals extending from the first switch are connected to PCIe connectors through a resistive network.
The PXIe controller also comprises a PXIe controller front panel TRIG connector, and the PXIe controller front panel TRIG connector is connected with the PXIe controller chassis backboard through the FPGA control module, so that bidirectional triggering with the PXIe chassis backboard is realized.
The PCIe connector, the upstream port PCIe connector and the downstream port PCIe connector adopt Molex iPass TM The Connector System serial products have the signal rate of up to 14Gbps, and the differential pair of up to 8 channels, and can meet the requirements of PCIe Gen3 (8 Gbps) transmission rate and 4 channels. The PCIe active optical cable adopts PCIe Optical Cable System series products of Samtec, supports PCIe Gen1 (2.5 Gbps), PCIe Gen2 (5 Gbps) and PCIe Gen3 (8 Gbps) rate transmission, can realize transmission distance of up to 100m, transmits PCIe signals through 4 paths of independent full-duplex optical fiber channels, and meets the requirements of PCIEGen3 (8 Gbps) transmission rate and 4 channels.
A PXIe controller remote control method based on optical fiber uses a PXIe controller remote control system based on optical fiber as described above, and the process is as follows: the PCIe adapter is arranged in a slot of a computer PCIe multiplied by 4 or more through a PCIe golden finger, and PCIe Gen3 multiplied by 4 signals of the computer connected by the PCIe golden finger are subjected to signal extension through a first PCIe switch, led out to a PCIe connector and transmitted to the PXIe controller through a PCIe active optical cable; the PXIe controller is arranged in a system slot of the PXIe chassis, the upstream port PCIe connector expands the function of PCIe Gen3×4 signals transmitted by the received PCIe adapter through a second PCIe switch to obtain 4-path 4PCIe signals or 2-path 8PCIe signals, and the 4-path 4PCIe signals or 2-path 8PCIe signals are connected to the PXIe chassis backboard, so that the control of the external main control computer on the PXIe chassis is realized; on the other hand, the second PCIe switch also expands 1-path×4PCIe signals, and leads out to a downstream port PCIe connector, wherein the downstream port PCIe connector is connected to an upstream port of a PXIe controller of a lower-level chassis through a PCIe active optical cable, so that a link is established with the lower-level PXIe chassis, and the expansion cascade of multiple chassis is realized.
And the PCIe adapter and the PXIe controller respectively generate 100MHz constant clocks through PCIe clock generators, the PCIe adapter provides reference clocks for the first PCIe switch and the PCIe connector through zero delay clock buffers, and the PXIe controller also provides reference clocks for the second PCIe switch, the upstream port PCIe connector, the downstream port PCIe connector and the PXIe chassis backboard through zero delay clock buffers.
The PCIe Gen3×4 signal transmitted by the PCIe adapter comprises 4-channel PCIe differential signal pairs, each channel differential signal consists of a differential transmitting signal pair and a differential receiving signal pair, the simulation receiving ends of the common-mode pulse detection response unit are simulated through a resistor network to correspond to each other, if the differential transmitting signal pair of each channel always detects 50 ohm/100 ohm load, the PXIe controller is judged to exist, and accordingly a link is established with the PXIe controller, and control and communication of the PXIe controller are achieved.
The FPGA control module is connected with the second PCIe switch through the PCIe interface chip, and the register of the FPGA control module is mapped to the base address space of the second PCIe switch, so that interaction and control with an external main control computer are realized; the SMBus controller is connected with the FPGA control module, and performs bidirectional conversion and communication between the parallel bus of the FPGA control module and the SMBus bus of the back board of the PXIe chassis, so as to realize the control function of the external main control computer on the SMBus interface; the FPGA control module analyzes a command issued by the external main control computer to the second PCIe interface chip, transmits the command to the SMbus controller, and uploads data transmitted back by the SMbus controller to the second PCIe interface chip and further transmits the data back to the external main control computer.
The FPGA control module controls the input and output directions of TRIG signals transmitted by a TRIG connector of a front panel of the PXIe controller and 8 paths of PXI_TRIG [0 … ] signals transmitted by a back panel of the PXIe machine box, connects the TRIG signals transmitted by the TRIG connector of the PXIe controller and the 8 paths of PXI_TRIG [0 … ] signals transmitted by the back panel of the PXIe machine box to an IO port of the FPGA control module, and realizes the TRIG signal bidirectional triggering function of the front panel TRIG connector and the back panel of the machine box by controlling the input and output of the IO port.
The invention has the technical effects that:
the invention utilizes the simple and friendly interface characteristics and good file description of the Media Access Control (MAC) and the physical layer (PHY) of PCIe, drives the optical transceiver module to realize optical fiber communication through the PCIe switch, realizes remote control, greatly prolongs the online distance of the PXIe controller and realizes the construction of a multistage chassis system. And the optical transceiver module is driven by the FPGA with strong performance and function requirements at the two ends of the PCIe adapter and the PXIe controller, so that the cost is effectively reduced. The invention uses PCIe active optical cable, integrates micro optical transceiver inside, realizes photoelectric conversion and conversion of PCIe protocol and optical fiber communication protocol, and does not need communication protocol conversion. On the other hand, the PCIe clock generator solves the problem that the PCIe standard no longer supports spread spectrum clocks based on optical fibers and the link length exceeds 7 m. And thirdly, the resistor network simulation common mode pulse detection response unit solves the problem that the PCIe adapter and the PXIe controller cannot establish a link because no electrical connection exists in the optical fiber transmission process.
Drawings
Fig. 1 is a schematic diagram of a coaxial cable based PXIe controller control system reference clock distribution.
Fig. 2 is a schematic diagram of a fiber-based PXIe controller control system reference clock distribution.
Fig. 3 is a schematic diagram of a fiber-based PXIe controller remote control system.
Fig. 4 is a schematic diagram of an extended cascade for implementing multiple chassis based on optical fibers.
Fig. 5 is a schematic circuit diagram of a resistor network analog common mode impulse detection response unit.
Detailed Description
A remote control system of a PXIe controller based on optical fibers comprises a PCIe adapter and the PXIe controller which are connected through a PCIe active optical cable; the method is characterized in that: the PCIe adapter comprises a PCIe golden finger, a first PCIe switch and a PCIe connector which are connected in sequence; the first PCIe switch is connected with the external main control computer through PCIe golden fingers; the first PCIe switch extends PCIe Gen3×4 signals; the PXIe controller comprises an upstream port PCIe connector, a downstream port PCIe connector and a second PCIe switch, wherein the second PCIe switch expands PCIe Gen3×4 signals transmitted by the upstream port to obtain 4-path×4PCIe signals or 2-path×8PCIe signals, and the 4-path×4PCIe signals are connected to the PXIe chassis backboard; the second PCIe switch also expands 1-way x 4PCIe to be connected to a downstream port PCIe connector, and the downstream port PCIe connector is connected to an upstream port PCIe connector of a PXIe controller of the lower-level chassis through a PCIe active optical cable, so that expansion cascade of the multiple chassis is realized; the PXIe controller also comprises an FPGA control module, and the FPGA control module is connected with the PXIe chassis backboard through the SMBus controller; the FPGA control module is also connected with the second PCIe switch through a PCIe interface chip;
the FPGA control module is connected with the second PCIe switch through the PCIe interface chip, and the register of the FPGA control module is mapped to the base address space of the second PCIe switch, so that interaction and control with an external main control computer are realized; the SMBus controller is connected with the FPGA control module, and performs bidirectional conversion and communication between the parallel bus of the FPGA control module and the SMBus bus of the back board of the PXIe chassis, so as to realize the control function of the external main control computer on the SMBus interface; the FPGA control module analyzes a command issued by the external main control computer to the second PCIe interface chip, transmits the command to the SMbus controller, and uploads data transmitted back by the SMbus controller to the second PCIe interface chip and further transmits the data back to the external main control computer.
The PCIe active optical cable is connected with the PCIe adapter and the PXIe controller through connectors at two ends of the PCIe active optical cable, a micro optical transceiver is integrated in the connector, the micro optical transceiver at the connection end of the PCIe adapter or the downstream port of the PXIe controller converts PCIe Gen3×4 signals into optical fiber signals, and the micro optical transceiver at the connection end of the upstream port of the PXIe controller converts the optical fiber signals into PCIe Gen3×4 signals and transmits the PCIe Gen3×4 signals to the PXIe controller.
The PCIe adapter and the PXIe controller also comprise PCIe clock generators which are respectively a transmitting end PCIe clock generator and a receiving end PCIe clock generator, and the transmitting end PCIe clock generator is respectively connected with the PCIe connector and the first PCIe switch through zero delay clock buffers; the receiving end PCIe clock generator is respectively connected with the upstream port PCIe connector, the downstream port PCIe connector and the second PCIe switch through the zero delay clock buffer.
And the PCIe adapter and the PXIe controller respectively generate 100MHz constant clocks through PCIe clock generators, the PCIe adapter provides reference clocks for the first PCIe switch and the PCIe connector through zero delay clock buffers, and the PXIe controller also provides reference clocks for the second PCIe switch, the upstream port PCIe connector, the downstream port PCIe connector and the PXIe chassis backboard through zero delay clock buffers.
The PCIe adapter also comprises a resistance network simulation common mode pulse detection response unit, wherein one end of the resistance network simulation common mode pulse detection response unit is electrically connected with the first PCIe switch, and the other end of the resistance network simulation common mode pulse detection response unit is electrically connected with the PCIe connector; the resistor network simulation common-mode pulse detection response unit comprises a first branch and a second branch which are connected in parallel on a first PCIe exchange switch and a PCIe connector, wherein the first branch and the second branch comprise two first resistors which are sequentially connected in series, and second resistors are arranged between an input end between the first branch and the second branch and an output end between the first branch and the second branch; differential transmit signal pairs for each lane of PCIe Gen3 x 4 signals extending from the first switch are connected to PCIe connectors through a resistive network. As shown in fig. 5, one skilled in the art can set parameters in the resistor network analog common mode impulse detection response unit according to the provided schematic.
The PCIe Gen3×4 signal transmitted by the PCIe adapter comprises 4-channel PCIe differential signal pairs, each channel differential signal consists of a differential transmitting signal pair and a differential receiving signal pair, the simulation receiving ends of the common-mode pulse detection response unit are simulated through a resistor network to correspond to each other, if the differential transmitting signal pair of each channel always detects 50 ohm/100 ohm load, the PXIe controller is judged to exist, and accordingly a link is established with the PXIe controller, and control and communication of the PXIe controller are achieved.
The PXIe controller also comprises a PXIe controller front panel TRIG connector, and the PXIe controller front panel TRIG connector is connected with the PXIe controller chassis backboard through the FPGA control module, so that bidirectional triggering with the PXIe chassis backboard is realized.
The FPGA control module controls the input and output directions of TRIG signals transmitted by a TRIG connector of a front panel of the PXIe controller and 8 paths of PXI_TRIG [0 … ] signals transmitted by a back panel of the PXIe machine box, connects the TRIG signals transmitted by the TRIG connector of the PXIe controller and the 8 paths of PXI_TRIG [0 … ] signals transmitted by the back panel of the PXIe machine box to an IO port of the FPGA control module, and realizes the TRIG signal bidirectional triggering function of the front panel TRIG connector and the back panel of the machine box by controlling the input and output of the IO port.
The PCIe connector, the upstream port PCIe connector and the downstream port PCIe connector adopt Molex ibas TM The Connector System serial products have the signal rate of up to 14Gbps, and the differential pair of up to 8 channels, and can meet the requirements of PCIe Gen3 (8 Gbps) transmission rate and 4 channels. The PCIe active optical cable adopts PCIe Optical Cable System series products of Samtec, supports PCIe Gen1 (2.5 Gbps), PCIe Gen2 (5 Gbps) and PCIe Gen3 (8 Gbps) rate transmission, can realize transmission distance of up to 100m, transmits PCIe signals through 4 paths of independent full-duplex optical fiber channels, and meets the requirements of PCIEGen3 (8 Gbps) transmission rate and 4 channels.
A PXIe controller remote control method based on optical fiber uses a PXIe controller remote control system based on optical fiber as described above, and the process is as follows: the PCIe adapter is arranged in a slot of a computer PCIe multiplied by 4 or more through a PCIe golden finger, and PCIe Gen3 multiplied by 4 signals of the computer connected by the PCIe golden finger are subjected to signal extension through a first PCIe switch, led out to a PCIe connector and transmitted to the PXIe controller through a PCIe active optical cable; the PXIe controller is arranged in a system slot of the PXIe chassis, the upstream port PCIe connector expands the function of PCIe Gen3×4 signals transmitted by the received PCIe adapter through a second PCIe switch to obtain 4-path 4PCIe signals or 2-path 8PCIe signals, and the 4-path 4PCIe signals or 2-path 8PCIe signals are connected to the PXIe chassis backboard, so that the control of the external main control computer on the PXIe chassis is realized; on the other hand, the second PCIe switch also expands 1-path×4PCIe signals, and leads out to a downstream port PCIe connector, wherein the downstream port PCIe connector is connected to an upstream port of a PXIe controller of a lower-level chassis through a PCIe active optical cable, so that a link is established with the lower-level PXIe chassis, and the expansion cascade of multiple chassis is realized.
Claims (8)
1. A remote control system of a PXIe controller based on optical fibers comprises a PCIe adapter and the PXIe controller which are connected through a PCIe active optical cable; the method is characterized in that: the PCIe adapter comprises a PCIe golden finger, a first PCIe switch and a PCIe connector which are connected in sequence; the first PCIe switch is connected with the external main control computer through PCIe golden fingers; the first PCIe switch extends PCIe Gen3×4 signals; the PXIe controller comprises an upstream port PCIe connector, a downstream port PCIe connector and a second PCIe switch, wherein the second PCIe switch expands PCIe Gen3×4 signals transmitted by the upstream port to obtain 4-path×4PCIe signals or 2-path×8PCIe signals, and the 4-path×4PCIe signals are connected to the PXIe chassis backboard; the second PCIe switch also expands 1-way x 4PCIe to be connected to a downstream port PCIe connector, and the downstream port PCIe connector is connected to an upstream port PCIe connector of a PXIe controller of the lower-level chassis through a PCIe active optical cable, so that expansion cascade of the multiple chassis is realized;
the PXIe controller also comprises an FPGA control module, and the FPGA control module is connected with the PXIe chassis backboard through the SMBus controller; the FPGA control module is also connected with the second PCIe switch through a PCIe interface chip;
the PCIe active optical cable is connected with the PCIe adapter and the PXIe controller through connectors at two ends of the PCIe active optical cable, a micro optical transceiver is integrated in the connector, a micro optical transceiver at the connection end of a downstream port of the PCIe adapter or the PXIe controller converts PCIe Gen3×4 signals into optical fiber signals, and a micro optical transceiver at the connection end of an upstream port of the PXIe controller converts the optical fiber signals into PCIe Gen3×4 signals and transmits the PCIe Gen3×4 signals to the PXIe controller;
the PCIe adapter and the PXIe controller also comprise PCIe clock generators which are respectively a transmitting end PCIe clock generator and a receiving end PCIe clock generator, and the transmitting end PCIe clock generator is respectively connected with the PCIe connector and the first PCIe switch through zero delay clock buffers; the receiving end PCIe clock generator is respectively connected with the upstream port PCIe connector, the downstream port PCIe connector and the second PCIe switch through the zero delay clock buffer;
the PCIe adapter also comprises a resistance network simulation common mode pulse detection response unit, wherein one end of the resistance network simulation common mode pulse detection response unit is electrically connected with the first PCIe switch, and the other end of the resistance network simulation common mode pulse detection response unit is electrically connected with the PCIe connector; the resistor network simulation common-mode pulse detection response unit comprises a first branch and a second branch which are connected in parallel on a first PCIe exchange switch and a PCIe connector, wherein the first branch and the second branch comprise two first resistors which are sequentially connected in series, and second resistors are arranged between an input end between the first branch and the second branch and an output end between the first branch and the second branch; differential transmit signal pairs for each lane of PCIe Gen3 x 4 signals extending from the first switch are connected to PCIe connectors through a resistive network.
2. A fiber-based PXIe controller remote control system as recited in claim 1, wherein: the PXIe controller also comprises a PXIe controller front panel TRIG connector, and the PXIe controller front panel TRIG connector is connected with the PXIe controller chassis backboard through the FPGA control module, so that bidirectional triggering with the PXIe chassis backboard is realized.
3. A fiber-based PXIe controller remote control system as recited in claim 2, wherein: the PCIe connector, the upstream port PCIe connector and the downstream port PCIe connector adopt Molex ibas TM A Connector System series product; the PCIe active optical cable adopts a PCIe Optical Cable System series product of Samtec.
4. A method for remotely controlling a PXIe controller based on optical fiber, using a PXIe controller remote control system based on optical fiber as defined in claim 1, comprising the following steps: the PCIe adapter is arranged in a slot of a computer PCIe multiplied by 4 or more through a PCIe golden finger, and PCIe Gen3 multiplied by 4 signals of the computer connected by the PCIe golden finger are subjected to signal extension through a first PCIe switch, led out to a PCIe connector and transmitted to the PXIe controller through a PCIe active optical cable; the PXIe controller is arranged in a system slot of the PXIe chassis, the upstream port PCIe connector expands the function of PCIe Gen3×4 signals transmitted by the received PCIe adapter through a second PCIe switch to obtain 4-path 4PCIe signals or 2-path 8PCIe signals, and the 4-path 4PCIe signals or 2-path 8PCIe signals are connected to the PXIe chassis backboard, so that the control of the external main control computer on the PXIe chassis is realized; on the other hand, the second PCIe switch also expands 1-path×4PCIe signals, and leads out to a downstream port PCIe connector, wherein the downstream port PCIe connector is connected to an upstream port of a PXIe controller of a lower-level chassis through a PCIe active optical cable, so that a link is established with the lower-level PXIe chassis, and the expansion cascade of multiple chassis is realized.
5. The method for remotely controlling the PXIe controller based on the optical fiber as recited in claim 4, wherein: and the PCIe adapter and the PXIe controller respectively generate 100MHz constant clocks through PCIe clock generators, the PCIe adapter provides reference clocks for the first PCIe switch and the PCIe connector through zero delay clock buffers, and the PXIe controller also provides reference clocks for the second PCIe switch, the upstream port PCIe connector, the downstream port PCIe connector and the PXIe chassis backboard through zero delay clock buffers.
6. The method for remotely controlling a PXIe controller based on optical fiber as recited in claim 5, further comprising: the PCIe Gen3×4 signal transmitted by the PCIe adapter comprises 4-channel PCIe differential signal pairs, each channel differential signal consists of a differential transmitting signal pair and a differential receiving signal pair, the simulation receiving ends of the common-mode pulse detection response unit are simulated through a resistor network to correspond to each other, if the differential transmitting signal pair of each channel always detects 50 ohm/100 ohm load, the PXIe controller is judged to exist, and accordingly a link is established with the PXIe controller, and control and communication of the PXIe controller are achieved.
7. The method for remotely controlling a PXIe controller based on optical fiber as recited in claim 6, further comprising: the FPGA control module is connected with the second PCIe switch through the PCIe interface chip, and the register of the FPGA control module is mapped to the base address space of the second PCIe switch, so that interaction and control with an external main control computer are realized; the SMBus controller is connected with the FPGA control module, and performs bidirectional conversion and communication between the parallel bus of the FPGA control module and the SMBus bus of the back board of the PXIe chassis, so as to realize the control function of the external main control computer on the SMBus interface; the FPGA control module analyzes a command issued by the external main control computer to the second PCIe interface chip, transmits the command to the SMbus controller, and uploads data transmitted back by the SMbus controller to the second PCIe interface chip and further transmits the data back to the external main control computer.
8. The method for remotely controlling a PXIe controller based on optical fiber as recited in claim 7, further comprising: the FPGA control module controls the input and output directions of TRIG signals transmitted by a TRIG connector of a front panel of the PXIe controller and 8 paths of PXI_TRIG [0 … ] signals transmitted by a back panel of the PXIe machine box, connects the TRIG signals transmitted by the TRIG connector of the PXIe controller and the 8 paths of PXI_TRIG [0 … ] signals transmitted by the back panel of the PXIe machine box to an IO port of the FPGA control module, and realizes the TRIG signal bidirectional triggering function of the front panel TRIG connector and the back panel of the machine box by controlling the input and output of the IO port.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711471638.3A CN108062055B (en) | 2017-12-29 | 2017-12-29 | PXIe controller remote control system and method based on optical fiber |
Applications Claiming Priority (1)
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| CN109710025A (en) * | 2019-01-07 | 2019-05-03 | 深圳忆联信息系统有限公司 | A kind of PCIE clock compatibility method, device, computer equipment and the storage medium of solid state hard disk |
| CN110222001B (en) * | 2019-05-20 | 2023-06-20 | 中国科学技术大学 | Feedback control system and feedback control method based on PXIe chassis |
| CN110278032B (en) * | 2019-06-11 | 2021-03-09 | 中国科学技术大学 | PCIe data transmission device and method based on optical fiber |
| CN111212000B (en) * | 2019-12-26 | 2022-04-08 | 北京航天测控技术有限公司 | Exchange backplate based on PXIe bus |
| CN112597097B (en) * | 2020-12-28 | 2022-11-22 | 山东浪潮科学研究院有限公司 | Communication system based on ADC data acquisition card, application method and medium thereof |
| CN112822129A (en) * | 2021-02-05 | 2021-05-18 | 井芯微电子技术(天津)有限公司 | PCIe switching equipment |
| CN113904970B (en) * | 2021-12-09 | 2022-03-01 | 伟恩测试技术(武汉)有限公司 | Transmission system and method of semiconductor test equipment |
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