CN112802837A - 一种高静电防护能力的沟槽mosfet器件 - Google Patents

一种高静电防护能力的沟槽mosfet器件 Download PDF

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CN112802837A
CN112802837A CN202011602651.XA CN202011602651A CN112802837A CN 112802837 A CN112802837 A CN 112802837A CN 202011602651 A CN202011602651 A CN 202011602651A CN 112802837 A CN112802837 A CN 112802837A
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刘锋
周祥瑞
殷允超
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JIANGSU JIEJIE MICROELECTRONICS CO Ltd
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Abstract

本发明涉及一种高静电防护能力的沟槽MOSFET器件，包括有源区、栅电极区及环绕有源区和栅电极区的终端保护区，栅电极区包括ESD静电保护区，ESD静电保护区连续环绕设置在栅电极区的边缘；ESD静电保护区包括第一导电类型漂移区、位于第一导电类型漂移区下方且邻接的第一导电类型衬底及位于第一导电类型漂移区内的第二导电类型阱区，第二导电类型阱区上方设有绝缘氧化层，在绝缘介质层上设有连续螺旋环绕的PN结组，连续螺旋环绕的PN结组设于栅极金属和源极金属之间；本发明通过在栅电极区设置ESD静电防护结构，且ESD防护结构采用连续环绕设置的PN结组，这样能加长栅极和源极间的PN结组的长度，进而可大大增加沟槽MOSFET的ESD防护能力，提升器件的可靠性。

Description

一种高静电防护能力的沟槽MOSFET器件
技术领域
本发明涉及一种沟槽MOSFET器件，尤其是一种高静电防护能力的沟槽 MOSFET器件，属于半导体技术领域。
背景技术
目前，在半导体制造工艺和其应用过程中，经常可能出现静电放电(Electrostatics Discharge，ESD)现象。ESD现象发生会引起高电压电位的放电脉冲，这会导致器件被高压脉冲击穿，造成整个系统的功能失效。因而，对半导体器件来说ESD防护是必不可少的。
现有的沟槽功率MOSFET的栅氧化层厚度较薄，这种结构决定了沟槽功率 MOS器件是静电敏感型器件，对器件抗静电放电(electro-staticdischarge，ESD) 承受能力较高。因此，改善沟槽功率MOS器件静电放电防护的能力对提高产品的可靠性具有不可忽视的作用。
目前，半导体器件常用的ESD防护结构，一般设置在有源区的器件单胞内，或是设置在终端保护区，有如下缺点：
1)ESD防护结构设置在有源区内，占用有源区面积，芯片面积利用率大大降低；
2)ESD防护结构设置在终端保护区，不仅占用终端面积，而且严重影响器件终端的耐压性能；
3)现有技术的ESD防护结构不管是设置在有源区还是终端保护区，防静电结构基本都是多个PN结二极管组形成，且抗静电能力的高低主要受PN结二极管组的长度影响，长度越长，抗静电能力越高，而在有源区和终端保护区的 ESD结构面积有限，因此，ESD防护能力有限。
发明内容
本发明的目的在于克服现有沟槽MOSFET器件缺点，提出一种高静电防护能力的沟槽MOSFET器件，通过在栅电极区设置ESD静电防护结构，且ESD 防护结构采用连续螺旋环绕设置的PN结组，这样能加长栅极和源极间的PN结组的长度，进而可大大增加沟槽MOSFET的ESD防护能力，提升器件的可靠性。
为解决上述技术问题，本发明所采用的技术方案如下：一种高静电防护能力的沟槽MOSFET器件，其特征在于：包括有源区、栅电极区及环绕所述有源区和栅电极区的终端保护区，所述栅电极区包括ESD静电保护区，所述ESD静电保护区连续环绕设置在所述栅电极区的边缘；
在所述ESD静电保护区的截面上，所述ESD静电保护区包括第一导电类型漂移区、位于所述第一导电类型漂移区下方且邻接的第一导电类型衬底及位于所述第一导电类型漂移区内的第二导电类型阱区，所述第二导电类型阱区上方的设有绝缘氧化层，在所述绝缘介质层上设有连续螺旋环绕的PN结组，所述连续螺旋环绕的PN结组设于栅极金属和源极金属之间。
进一步地，所述连续螺旋环绕的PN结组包括多晶硅PN结组，所述多晶硅PN 结组的组数不小于2组。
进一步地，所述终端保护区还包括终端沟槽分压区和终端截止区。
进一步地，在所述沟槽MOSFET的截面上，所述有源区包括若干个并联的元胞单元，所述元胞单元包括位于所述第一导电类型漂移区内的沟槽，所述沟槽两侧设有第二导电类型阱区及位于所述第二导电类型阱区内的第一导电类型源区，所述第一导电类型源区与所述沟槽邻接，所述沟槽内设有紧贴沟槽壁的氧化层、被所述氧化层包裹的栅多晶硅，所述栅多晶硅两侧的氧化层为栅氧化层，在所述沟槽上方覆盖有介质层，所述介质层上覆盖有源极金属，所述源极金属穿通介质层分别与第二导电类型阱区、第一导电类型源区欧姆接触。
进一步地，对于N型沟槽MOSFET器件结构，所述第一导电类型为N型导电，所述第二导电类型为P型导电；对于P型沟槽MOSFET器件结构，所述第一导电类型为P型导电，所述第二导电类型为N型导电。
与传统ESD结构相比，本发明具有以下优点：
1)传统的ESD防护结构设置在终端保护区，影响器件的耐压性能，或设置在有源区，占用有源区面积，芯片的利用率降低；本发明的ESD静电防护结构设置在栅电极区，既不影响器件参数特性，又能有效利用芯片面积；
2)本发明ESD静电防护结构采用连续螺旋环绕的PN结二极管组，在有限的空间内可加长PN结二极管组的长度，因此，可提升器件的ESD防护能力，进而提升器件的可靠性。
附图说明
图1是本发明的俯视结构示意图。
图2是图1中A-A’(即ESD静电保护区)的剖视结构示意图。
图3是图1中B-B’(即有源区的元胞单元)的剖视结构示意图。
附图说明：1-N型衬底、2-N型漂移区、3-介质层、4-沟槽、6-源极金属、 7-栅多晶硅、8-栅氧化层、9-P型体区、10-N型源极区、11-连续螺旋环绕的PN 结组、12-栅极金属、100-栅电极区、101-有源区、102-终端保护区。
具体实施方式
下面结合具体实施例对本发明作进一步说明。
如下实施例中的一种高静电防护能力的沟槽MOSFET器件，以N型为例，所述第一导电类型为N型，所述第二导电类型为P型；
实施例1
如图1所示，一种高静电防护能力的沟槽MOSFET器件，包括有源区101、栅电极区100及环绕所述有源区101和栅电极区100的终端保护区102，所述栅电极区100包括ESD静电保护区，所述ESD静电保护区连续环绕设置在所述栅电极区100的边缘；
所述终端保护区102还包括终端沟槽分压区和终端截止区。
如图2所示，在所述ESD静电保护区的截面上，所述ESD静电保护区包括N 型漂移区2、位于所述N型漂移区2下方且邻接的N型衬底1及位于所述N型漂移区 2内的P型阱区9，所述P型阱区9上方的设有绝缘氧化层3，在所述绝缘氧化层3上设有连续螺旋环绕的PN结组11，所述连续螺旋环绕的PN结组11设于栅极金属12 和源极金属6之间；所述连续螺旋环绕的PN结组11包括多晶硅PN结组，所述多晶硅PN结组的组数不小于2组；
本实施例1中所述连续螺旋环绕的PN结组包括多晶硅PN结组，所述多晶硅 PN结组的组数为2组。
在所述沟槽MOSFET的截面上，所述有源区101包括若干个并联的元胞单元，所述元胞单元包括位于所述N型漂移区2内的沟槽4，所述沟槽4两侧设有P型阱区 9及位于所述P型阱区9内的N型源区10，所述N型源区10与所述沟槽4邻接，所述沟槽4内设有紧贴沟槽壁的氧化层、被所述氧化层包裹的栅多晶硅7，所述栅多晶硅7两侧的氧化层为栅氧化层8，在所述沟槽4上方覆盖有绝缘氧化层3，所述绝缘氧化层3上覆盖有源极金属6，所述源极金属6穿通绝缘介质层3分别与P型阱区9、N型源区10欧姆接触。
本发明的基本工作原理如下：
当有静电发生时，栅极金属12和源极金属6间因静电产生正向或反向高电压脉冲冲击，使得当栅极电压大于ESD保护结构触发电压时，ESD保护结构开启，电流经过栅极金属12-ESD保护结构(连续螺旋环绕的PN结组11)-源极金属6， PN结组能够先于栅氧化层8被击穿，瞬间泄放电压电流，避免栅氧化层11被高压击穿，ESD能力可以有效增加60％左右，提升了沟槽MOSFET器件可靠性。

Claims (5)

1.一种高静电防护能力的沟槽MOSFET器件，其特征在于：包括有源区、栅电极区及环绕所述有源区和栅电极区的终端保护区，所述栅电极区包括ESD静电保护区，所述ESD静电保护区连续环绕设置在所述栅电极区的边缘；
在所述ESD静电保护区的截面上，所述ESD静电保护区包括第一导电类型漂移区、位于所述第一导电类型漂移区下方且邻接的第一导电类型衬底及位于所述第一导电类型漂移区内的第二导电类型阱区，所述第二导电类型阱区上方的设有绝缘介质层，在所述绝缘介质层上设有连续螺旋环绕的PN结组，所述连续螺旋环绕的PN结组设于栅极金属和源极金属之间。
2.根据权利要求1所述的一种高静电防护能力的沟槽MOSFET器件，其特征在于：所述连续螺旋环绕的PN结组包括多晶硅PN结组，所述多晶硅PN结组的组数不小于2组。
3.根据权利要求1所述的一种高静电防护能力的沟槽MOSFET器件，其特征在于：所述终端保护区还包括终端沟槽分压区和终端截止区。
4.根据权利要求1所述的一种高静电防护能力的沟槽MOSFET器件，其特征在于：在所述沟槽MOSFET的截面上，所述有源区包括若干个并联的元胞单元，所述元胞单元包括位于所述第一导电类型漂移区内的沟槽，所述沟槽两侧设有第二导电类型阱区及位于所述第二导电类型阱区内的第一导电类型源区，所述第一导电类型源区与所述沟槽邻接，所述沟槽内设有紧贴沟槽壁的氧化层、被所述氧化层包裹的栅多晶硅，所述栅多晶硅两侧的氧化层为栅氧化层，在所述沟槽上方覆盖有绝缘介质层，所述绝缘介质层上覆盖有源极金属，所述源极金属穿通介质层分别与第二导电类型阱区、第一导电类型源区欧姆接触。
5.根据权利要求1所述的一种高静电防护能力的沟槽MOSFET器件，其特征在于：对于N型沟槽MOSFET器件结构，所述第一导电类型为N型导电，所述第二导电类型为P型导电；对于P型沟槽MOSFET器件结构，所述第一导电类型为P型导电，所述第二导电类型为N型导电。
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Cited By (2)

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CN113611744A (zh) * 2021-07-07 2021-11-05 上海华虹宏力半导体制造有限公司 适用soi型的静电保护mos结构
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