CN112216691B - 一种集成箝位二极管的半导体功率器件 - Google Patents

一种集成箝位二极管的半导体功率器件 Download PDF

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CN112216691B
CN112216691B CN202011000415.0A CN202011000415A CN112216691B CN 112216691 B CN112216691 B CN 112216691B CN 202011000415 A CN202011000415 A CN 202011000415A CN 112216691 B CN112216691 B CN 112216691B
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Abstract

本发明公开了一种屏蔽栅结构位于有源区、沟槽式场板终端区围绕有源区周围的半导体功率器件。连接在漏金属和源金属(或栅金属)之间的齐纳二极管，用作SD(或GD)箝位二极管。沟槽式场板终端区围绕在有源区的周围，其中，仅有芯片阵列的存在并不会导致集成SD或GD多晶硅箝位二极管时，击穿电压的下降。

Description

一种集成箝位二极管的半导体功率器件
技术领域
本发明主要涉及半导体功率器件的单元结构和器件设计。更具体地，本发明涉及一种集成有具有沟槽式场板终端区以避免击穿电压下降的箝位二极管的半导体功率器件的布局优化和器件结构。
背景技术
在30V～200V的电压范围内，屏蔽栅技术可使器件的芯片尺寸缩小30％～70％，然而，器件的雪崩能力也会同比例衰减。为了解决这一问题，集成漏-源(SD)或栅-漏(GD)箝位二极管于器件中，实现保护漏极和源极的目的。
图1A所示为一个现有技术美国专利公开号5,631,187所揭示的一种集成有栅-漏箝位二极管的MOSFET的电路图，其横截面如图1B所示。所述MOSFET形成于N型衬底200之上，在衬底200上表面的N+源区210被一个P体区211所包围。金属层220与N+源区210和P体区211相连，作为源极。同时，沉积金属层222和221于单元结构之上，分别作为栅极和漏极。在栅极和漏极之间，形成一系列背靠背的横穿终端区的多晶硅二极管230，以增强半导体功率器件的雪崩能力。一个保护环(GR)212，位于终端区内、多晶硅二极管230附近，作为维持终端区击穿电压的金属场板的一部分。
上述现有技术(美国专利公开号5,631,187)面临的技术难题是：栅-漏(或IGBT的栅-集)箝位二极管必须跨越终端区，而终端区又包围着栅金属垫片和有源区，由于多晶硅层阻挡了终端区的电场，最终导致击穿电压的下降。另一个现有技术(IEEE ElectronDevice Letters Vol.20,No.8,Aug.1999；Page 424～427))揭示了多晶硅箝位二极管下方的电场限制环(FLR)导致的击穿电压下降的问题。
因此，有必要提供一种新的改进的器件结构，以防止击穿电压的下降。
发明内容
本发明的一个优点是，本发明结构中的沟槽式场板终端区仅仅围绕在具有多个单元阵列的有源区的周围。栅金属垫片用于集成栅-漏箝位二极管和栅-源箝位二极管于MOSFET，其电路图如图2所示，俯视图如图3所示。其中，栅-漏(或IGBT的栅-集)箝位二极管并没有横穿终止区。因此，本发明的栅-漏(或IGBT的栅-集)箝位二极管在集成GD或SD多晶硅箝位二极管时并不会引起击穿电压的下降，这归因于多晶硅箝位二极管的下方并无保护环或FLR的存在。
根据本发明的一个优选实施例，如图4A和4B所示，分别为图3所示结构的A’-B’-C’和C’-D’的横截面图。本发明公开了一种沟槽式金属氧化物半导体场效应晶体管器件，其形成于具有第一掺杂类型(如N+)的重掺杂衬底之上。在所述衬底上，生长一层N外延层，并在其上刻蚀多个不同类型的栅沟槽。每个第一类型栅沟槽412均填充以屏蔽栅结构，包括位于栅沟槽较低部分的、作为屏蔽电极的第一多晶硅层以及位于栅沟槽较高部分的、作为栅电极的第二多晶硅层。其中，屏蔽电极与外延层之间通过第一绝缘层411实现绝缘，栅电极与外延层之间通过栅绝缘层413实现绝缘，并且所述栅绝缘层413的厚度小于所述第一绝缘层411，其中，屏蔽电极和栅电极之间通过第二绝缘层415实现绝缘；一个沟槽式场板终端区包括至少一个围绕在有源区周围的第二类型栅沟槽414，其中，每个第二类型414均只填充以屏蔽栅电极，并连接至源金属；一个栅-源(GS)箝位二极管形成在栅金属440和源金属450之间；一个栅-漏(GD)箝位二极管形成在栅金属440和沿着器件外围的漏金属导线460之间；一个填充以屏蔽栅电极的第三类型栅沟槽416，所述屏蔽栅电极直接对称地分布在所述GS和GD箝位二极管中阳极和阴极的沟槽接触区的正下方，起到缓冲层的作用，以防止栅-漏间的短路。
根据本发明的另一个优选实施例，如图5A和5B所示，分别为图3所示发明结构的另一种A’-B’-C’和C’-D’的横截面图。本发明公开的这种沟槽式金属氧化物半导体场效应晶体管器件，与图4A和图4B所揭示的器件结构类似，除了在图5A和5B所示的结构中并无仅填充以屏蔽栅电极的第三类型沟槽的存在。
根据本发明优选的实施例还包括以下一个或多个细节特征：所述屏蔽电极掺杂以第二导电类型，所述第二导电类型与所述第一导电类型的掺杂类型相反，且所述栅电极掺杂以所述第一导电类型；所述屏蔽电极和栅电极均掺杂以第一导电类型；本发明还进一步包括一个仅填充以屏蔽栅电极的第三类型栅沟槽，所述屏蔽栅电极直接对称地分布在所述GD和GS箝位二极管中阳极和阴极的沟槽接触区的正下方，起到缓冲层的作用，以防止栅-漏间的短路；所述GD和GS箝位二极管包括至少一对背靠背的齐纳二极管，所述齐纳二极管由多个交替排列的具有第一导电类型的掺杂区和具有第二导电类型的掺杂区构成，其中所述的第一类型和第二类型掺杂区的掺杂类型相反。
通过参考以下各个附图，阅读下文对优选实施例的详细描述，本发明的上述及其他的目的和优点对于本领域的普通技术人员来说无疑是显而易见的。
附图说明
图1A是现有技术所揭示的一个集成有栅-漏箝位二极管的MOSFET单元的电路图。
图1B是图1A所示集成有栅-漏箝位二极管的MOSFET单元的横截面图。
图2是根据本发明的一个优选的沟槽式MOSFET器件实施例的电路图，该实施例集成有GD和GS多晶硅齐纳箝位二极管，以实现GD和GS保护。
图3是图2所示优选实施例的俯视图，其至少包括一个围绕在有源区周围的沟槽式场板终端区，其中GS二极管围绕在栅金属垫片和源金属之间，GD二极管围绕在栅金属导线和沿着器件外围的漏金属导线之间。
图4A是图3中标记的沿A’-B’-C’轴上沟槽式MOSFET的一个优选的横截面图。
图4B是图3中标记的沿C’-D’轴上沟槽式MOSFET的一个优选的横截面图。
图5A是图3中标记的沿A’-B’-C’轴上沟槽式MOSFET的另一个优选的横截面图。
图5B是图3中标记的沿C’-D’轴上沟槽式MOSFET的另一个优选的横截面图。
图6是根据本发明的一个优选的沟槽式MOSFET器件实施例的电路图，该实施例集成有GS和SD多晶硅齐纳箝位二极管，用于实现GS和SD保护。
图7是图6所示优选实施例的俯视图，其中GS二极管围绕在栅金属垫片和源金属之间，SD二极管围绕在源金属和沿着器件外围的漏金属导线之间。
图8A是图7中标记的沿A”-B”-C”轴上沟槽式MOSFET的一个优选的横截面图。
图8B是图7中标记的沿D”-E”轴上沟槽式MOSFET的一个优选的横截面图。
图9A是图7中标记的沿A”-B”-C”轴上沟槽式MOSFET的另一个优选的横截面图。
图9B是图7中标记的沿D”-E”轴上沟槽式MOSFET的另一个优选的横截面图。
图10A是图7中标记的沿A”-B”-C”轴上沟槽式MOSFET的另一个优选的横截面图。
图10B是图7中标记的沿D”-E”轴上沟槽式MOSFET的另一个优选的横截面图。
具体实施方式
下面参照附图更详细地说明本发明，其中示出了本发明的优选实施例。本发明可以，但是以不同的方式体现，但是不应该局限于在此所述的实施例。例如，这里的说明更多地引用N沟道的半导体集成电路，但是很明显其他器件也是可能的。下文是通过参考各个附图来对实践本发明的优选实施例进行详细描述。一些方向术语，例如“顶部”、“底部”、“前”、“后”、“上方”、“下方”等，是参考各个附图的方向进行描述的。由于实施例中的元件可以被放置在许多不同的方向，因此，本发明中的方向术语只是用于描述而不能被视为对本发明的限制。应该理解的是，实施例中各种结构或者逻辑上的替代和修改都应该被涵盖在本发明的真正精神和范围内。因此，以下的详细描述不能被视为对本发明的限制，本发明的涵盖范围由附后的权利要求界定。应该理解的是，本发明中所描述的各个优选实施例的发明特征可以相互结合，有特别说明的除外。
图2所示为根据本发明的一个优选的沟槽式MOSFET单元实施例的电路图，该实施例集成有GD和GS多晶硅齐纳箝位二极管201，用于实现GD和GS保护。栅金属垫片用于集成栅-漏箝位二极管和栅-源箝位二极管于MOSFET。
图3所示为图2所示优选实施例的俯视图，所示优选实施例至少包含一个围绕在有源区周围的沟槽式场板终端区301，其中GS二极管305围绕在栅金属垫片302和源金属303之间，GD二极管307围绕在栅金属导线304和沿着器件外围的漏金属导线315之间。
图4A和4B所示，分别为图3所示实施例的一个优选的A’-B’-C’和C’-D’的横截面图。其中，所述的集成有栅-源箝位二极管的沟槽式MOSFET器件单元，形成于重掺杂的N+衬底400之上，所述衬底的背面涂有漏金属层490作为漏金属。在所述衬底400上，生长一层轻掺杂N外延层401，并在其上刻蚀多个不同类型的栅沟槽。每个第一类型栅沟槽412均填充以屏蔽栅结构，包括位于栅沟槽较低部分的、作为屏蔽电极的第一多晶硅层以及位于栅沟槽较高部分的、作为栅电极的第二多晶硅层。其中，屏蔽电极与外延层之间通过第一绝缘层411实现彼此间的绝缘，栅电极与外延层之间通过栅绝缘层413实现彼此间的绝缘，并且所述栅绝缘层413的厚度小于所述第一绝缘层411，其中，屏蔽电极和栅电极之间通过第二绝缘层415实现彼此间的绝缘；一个沟槽式场板终端区包括至少一个围绕在有源区周围的第二类型栅沟槽414，其中，每个第二类型414均只填充以屏蔽栅电极，并连接至源金属；一个栅-漏(GD)箝位二极管形成在栅金属440和沿着器件外围的漏金属导线460之间；一个栅-源(GS)箝位二极管形成在栅金属440和源金属450之间；一个填充以屏蔽栅电极的第三类型栅沟槽416，所述屏蔽栅电极直接对称地分布在所述GD和GS箝位二极管中阳极和阴极的沟槽接触区的正下方，起到缓冲层的作用，以防止栅-漏间的短路。所述GD和GS箝位二极管包括至少一对背靠背的齐纳二极管，所述齐纳二极管由多个交替排列的具有第一导电类型的掺杂区和具有第二导电类型的掺杂区构成，其中所述的第一类型和第二类型掺杂区的掺杂类型相反。自外延层的上表面向下延伸，分别为沟槽栅，P体区425，p+掺杂区426以及源区427，外延层的上表面覆盖有NSG和BPSG绝缘保护层435。金属层形成在绝缘保护层435的上方，并被光刻作为源金属450、栅金属440和漏金属导线460。填充以金属钨并衬以Ti/TiN阻挡层的接触金属插塞，穿过绝缘保护层435，用作源-体沟槽式接触区452、漏极沟槽式接触区462以及栅沟槽式接触区，其中p+接触区426形成于接触区底部的正下方，以改善源/体和漏之间的电接触。为了集成GS多晶硅齐纳箝位二极管和GD多晶硅齐纳箝位二极管，在位于衬底表面的氧化层455上形成多晶硅层，并掺杂形成交替相邻的n+区和p区。
图5A和5B所示，分别为图3所示优选实施例的另一个A’-B’-C’和C’-D’的横截面图。本发明所揭示的沟槽式MOSFET结构与图4A和图4B所示的器件结构类似，除了在图5A和5B所示的结构中并无仅填充以屏蔽栅电极的第三类型栅沟槽的存在。
图6所示为根据本发明的另一个优选的沟槽式MOSFET单元实施例的电路图，该实施例集成有GS和SD多晶硅齐纳箝位二极管601，用于实现GS和SD保护。该器件集成了一个位于栅电极和源电极之间的GS箝位二极管和一个位于源电极和漏电极之间的SD箝位二极管。
图7是图6所示优选实施例的俯视图，其中GS二极管705围绕在栅金属垫片702和源金属703之间，SD二极管708围绕在源金属703和沿着器件外围的漏金属导线705之间。
图8A和8B所示，分别为图6所示优选实施例的一个A”-B”-C”和D”-E”的横截面图。本发明所揭示的沟槽式MOSFET结构与图4A和图4B所示的发明结构类似。图8B所示的沟槽式MOSFET结构与图4B所示的结构类似，除了在图8B的结构中，集成有SD多晶硅齐纳箝位二极管用以实现SD保护；而在图4B所示的结构中，集成有GD多晶硅齐纳箝位二极管用以实现GD保护。
图9A和9B所示，分别为图6所示优选实施例的另一个A”-B”-C”和D”-E”的横截面图。本发明所揭示的沟槽式MOSFET结构与图8A和图8B所示的发明结构类似，除了在图9A和9B所示的结构中并无仅填充以屏蔽栅电极的第三类型沟槽的存在。
图10A和10B所示，分别为图6所示优选实施例的另一个A”-B”-C”和D”-E”的横截面图。本发明所揭示的沟槽式MOSFET结构与图9A和图9B所示的发明结构类似，除了栅电极的掺杂类型为第二导电类型P，与第一导电类型N相反。
虽然依照优选实施例对本发明进行了描述，但应该理解的是上述公开不能被视为是对本发明的限制。在阅读了上述公开的内容之后，各种替代和修改对于本技术领域的技术人员无疑是显而易见的。因此，附后的权利要求应被解释为涵盖落入本发明的真正精神和范围内的所有替代和修改。

Claims (4)

1.一种半导体功率器件，包括：
一个第一导电类型的外延层，位于衬底之上；
多个第一类型栅沟槽，位于有源区内的所述外延层中，且每个所述的第一类型栅沟槽均填充以一个屏蔽栅结构，所述屏蔽栅结构包括一个位于沟槽较低部分、作为第一屏蔽电极的第一多晶硅层，以及一个位于较高部分、作为栅电极的第二多晶硅层，其中，所述第一屏蔽电极与所述外延层间通过第一绝缘层实现绝缘，所述栅电极与所述外延层间通过一层栅绝缘层实现绝缘，其中所述栅绝缘层的厚度小于所述第一绝缘层，所述第一屏蔽电极和所述栅电极间通过第二绝缘层实现彼此间的绝缘；
一个沟槽式场板终端区，其包括至少一个围绕在所述有源区周围的第二类型栅沟槽，其中每个所述第二类型栅沟槽均填充以第二屏蔽电极并连接至源金属；
一个源-漏(SD)箝位二极管，位于源金属和沿着所述器件外围的漏金属之间；
一个栅-源(GS)箝位二极管，位于栅金属和所述源金属之间。
2.如权利要求1所述的半导体功率器件，其特征在于：
所述第一屏蔽电极、所述第二屏蔽电极以及所述栅电极均掺杂所述第一导电类型的载流子。
3.如权利要求1所述的半导体功率器件，其特征在于：
还包括一个填充以所述第二屏蔽电极的第三类型栅沟槽，所述第二屏蔽电极直接对称地分布在所述SD和GS箝位二极管中阳极和阴极的沟槽接触区的正下方，起到缓冲层的作用，以防止栅-漏间的短路。
4.如权利要求1所述的半导体功率器件，其特征在于：
所述SD和GS箝位二极管包括至少一对背靠背的齐纳二极管，所述齐纳二极管由多个交替排列的具有第一导电类型的掺杂区和具有第二导电类型的掺杂区构成，其中所述的第一类型和第二类型掺杂区的掺杂类型相反。
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