CN112038407A - 一种集成静电放电保护二极管的半导体功率器件 - Google Patents

一种集成静电放电保护二极管的半导体功率器件 Download PDF

Info

Publication number
CN112038407A
CN112038407A CN202010913672.7A CN202010913672A CN112038407A CN 112038407 A CN112038407 A CN 112038407A CN 202010913672 A CN202010913672 A CN 202010913672A CN 112038407 A CN112038407 A CN 112038407A
Authority
CN
China
Prior art keywords
gate
type
source
region
trench
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010913672.7A
Other languages
English (en)
Inventor
黄英杰
顾南雁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Dipu Electronics Co ltd
Original Assignee
Shenzhen Dipu Electronics Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Dipu Electronics Co ltd filed Critical Shenzhen Dipu Electronics Co ltd
Publication of CN112038407A publication Critical patent/CN112038407A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/866—Zener diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes

Abstract

本发明公开了一种改进的集成有ESD箝位二极管的沟槽式半导体功率器件，对ESD箝位二极管总周长进行了优化，其中所述的ESD箝位二极管包括由交替排列的第一导电类型的掺杂区和第二导电类型的掺杂区组成的多个背靠背的齐纳二极管，其中ESD箝位二极管的阳极连接至有源区内的沟槽栅，以降低栅电阻。

Description

一种集成静电放电保护二极管的半导体功率器件
技术领域
本发明主要涉及半导体功率器件的布图和器件结构。更具体地，本发明涉及一种集成有阳极连接至沟槽栅以提高开关速度的静电放电(ESD,electrostatic discharge)保护二极管的半导体功率器件的优化布局和器件结构。
背景技术
对于集成有栅(gate，栅极，下同)-源(Source，源极，下同)ESD箝位二极管的半导体功率器件来说，传统的布图和器件结构仍有一定的限制。例如在现有技术美国专利公开号8,053,808(如图1A和1B所示)中，在栅金属垫片和源金属垫片之间仅有一种ESD二极管区域。对于具有高ESD等级的小型器件而言，并没有太多的空间预算，这就要求增加栅金属垫片上的ESD二极管的外周总长度以增强ESD的性能。
为了改善空间的限制，图1C和1D分别为上述美国专利公开号8,053,808的另两种结构。其中，图1C所示为金属氧化物半导体场效应晶体管(MOSFET)器件100，其包括一个位于器件100外周边缘的连至栅金属导线125的栅金属垫片110以及一个源金属垫片120。在源金属垫片120、栅金属垫片110以及栅金属导线110’之间存在一个金属间隙115。栅-源ESD箝位二极管130连接于栅金属导线125和源金属垫片120之间。图1D是另一个MOSFET器件200的俯视图，其中包括一个源金属垫片211和一个连接至栅金属导线213的栅金属垫片212，且二者中间存在一个金属间隙214。与图1C中所示的MOSFET器件100不同，图1D所示的MOSFET200还进一步包括多晶硅电阻215连同栅-源ESD箝位二极管216，它们连接至栅金属导线213和源金属垫片211之间。此外，在图1D中，还有另一种栅-源ESD箝位二极管217，其连接在栅金属垫片212和源金属垫片211之间。图1C和图1D中所有的栅-源ESD箝位二极管包括具有许多交替排列的n+掺杂区和p+掺杂区组成的多个背靠背的齐纳二极管，其中，所述的许多交替排列的n+掺杂区和p+掺杂区都具有带状结构，这使得在器件的制造过程对多晶硅进行干法刻蚀的步骤中可能会损坏所述的栅-源ESD箝位二极管的边缘区域，从而导致在损坏的栅-源ESD箝位二极管的边缘区域处存在电流泄露通道。因此，现有技术中仅有两种类型的栅-源ESD箝位二极管：第一种类型形成于栅金属垫片和源金属垫片之间，第二种类型形成于源金属垫片和栅金属导线之间。特别对于小型器件而言，由于芯片尺寸的限制，栅-源ESD箝位二极管并没有足够的空间预算，这就需要增加栅-源ESD箝位二极管的总周长来增强ESD的性能。
图1E示为美国专利公开号8,466,514公开的一种改进的布局版图，在沟槽式半导体功率器件300的源电极和栅电极之间，存在用于提供ESD保护的四种类型的栅-源ESD箝位二极管：第一类型栅-源ESD箝位二极管(ESD1)连接在栅金属垫片301和源金属垫片303之间；第二类型栅-源ESD箝位二极管(ESD2)连接在栅金属垫片301和源金属导线304之间；第三类型栅-源ESD箝位二极管(ESD3)连接在栅金属导线302和源金属垫片303之间；第四类型栅-源ESD箝位二极管(ESD4)连接在栅金属导线302和源金属导线304之间。因此，与仅含有两种类型的栅-源ESD箝位二极管的现有技术(图1A～1D所示)相比，根据美国专利公开号8,466,514公开的改进的布局版图和器件结构多了两种类型的栅-源ESD箝位二极管，通过增加栅-源ESD箝位二极管的总周长来增强ESD的性能，这对于小型器件来讲意义重大。然而，在上述发明中，有源区周围用作ESD二极管阳极的栅金属导线并没有连接至沟槽栅，使得栅极电阻Rg较大从而导致开关速度慢，特别是对于P沟道沟槽式MOSFET而言。
因此，在集成有栅-源ESD箝位二极管的半导体功率器件领域中，有必要提供一种新的布局和器件结构，可以在不牺牲器件其他性能的条件下，通过优化栅-源ESD箝位二极管的总周长来增强ESD性能，降低栅电阻Rg并提高开关速度。
发明内容
本发明的一个方面是公开了一种半导体功率器件，该半导体功率器件集成有四种栅-源ESD箝位二极管，从而使得栅-源ESD箝位二极管的总外周长相比于现有技术显著增大，并且可以在不牺牲半导体功率器件其它性能的条件下增强ESD能力。
根据本发明的内容，公开了一种在半导体硅层中形成的集成有与栅-源ESD箝位二极管的半导体功率器件，其特征在于，包括：
(a)一个衬底，其具有第一导电类型；
(b)一个外延层，位于所述衬底之上，且具有第一导电类型，其中所述外延层的掺杂浓度低于所述衬底；
(c)位于有源区内的多个晶体管单元，并且所述的栅-源ESD箝位二极管包括由许多交替排列的第一导电类型的掺杂区和第二导电类型的掺杂区构成的多个背靠背的齐纳二极管；
(d)多个第一类型沟槽栅，其被所述的第一导电类型的源区环绕，其中所述的源区位于所述的第二导电类型的体区中；
(e)多个沟槽式源-体接触区，其穿过所述的源区并延伸入所述的体区中，所述的沟槽式源-体接触区填充以接触金属插塞并连接至所述的源极金属垫片；
所述的所述的栅-源ESD箝位二极管进一步包括：
(f)一个栅金属垫片，连接至第一类型栅金属导线，其下方为多晶硅层，所述多晶硅层作为栅-源ESD箝位二极管的阳极并围绕半导体功率器件的外围区域；
(g)第一类型栅-源ESD箝位二极管，其连接于所述栅金属垫片和源金属垫片之间；
(h)第二类型栅-源ESD箝位二极管，其连接于第一类型栅金属导线和源金属垫片之间；
(i)第一类型栅金属导线延伸至有源区中，并连接至第一类型沟槽栅以降低栅电阻。
在一些优选的实施例中，第一类型栅金属导线延伸至有源区中，并通过围绕半导体功率器件外围区域的第一类型栅金属导线连接至第一类型沟槽栅。在另一些优选的实施例中，第一类型栅金属导线延伸至有源区内，并通过至少一个第二类型栅金属导线连接至第一类型沟槽栅，所述第二类型栅金属导线下方并没有非掺杂多晶硅层的存在。
在一些优选的实施例中，根据本发明的半导体功率器件，其特征还包括：源金属垫片连接至至少一个源金属导线，所述源金属导线位于栅金属垫片和栅金属导线之间，所述源金属垫片与栅金属垫片、栅金属导线间通过一个金属间隙分隔开，其中所述源金属导线下方并无第一类型沟槽栅的存在；一个第三类型栅-源ESD箝位二极管，其连接至栅金属垫片和源金属导线之间；以及一个第四类型栅-源ESD箝位二极管，其连接至源金属导线和栅金属导线之间。
在一些优选的实施例中，根据本发明的半导体功率器件，其特征还包括：一个终端区，其包括至少一个具有悬浮电压的体掺杂区，其中所述的体掺杂区为所述的第二导电类型，且与所述的体区同时形成；一个源掺杂区，其为所述的第一导电类型，并且位于所述的半导体功率器件的边缘区域，且与所述的源区同时形成；一个沟槽式漏接触区，其填充以所述的接触金属插塞，穿过所述的源掺杂区并延伸入所述的半导体硅层中；一个欧姆接触掺杂区，其为所述的第二导电类型，并且位于所述的源掺杂区下方并至少包围所述的沟槽式漏接触区的底部，并且所述的欧姆接触掺杂区的掺杂浓度大于所述的体区。
根据本发明的优选的实施例还包括以下一个或多个细节特征：栅-源ESD箝位二极管的每个交替掺杂区均为闭合环状结构；体区形成于栅-源ESD箝位二极管的正下方，且进一步延伸至每两个相邻的第二类型沟槽栅之间，所述第二类型沟槽栅作为刻蚀缓冲沟槽栅，穿过体区，置于栅-源ESD箝位二极管中沟槽栅式ESD接触区的正下方，其中，刻蚀缓冲沟槽栅的沟槽宽度大于沟槽式ESD接触区，从而防止栅-体之间短路；所述的沟槽式漏接触区上方没有覆盖任何金属层，还包括位于终端区内的多个具有悬浮电压的第三类型沟槽栅；所述接触金属插塞为一个钨金属层，其衬以一层Ti/TiN或Co/TiN作为势垒金属层；所述的前金属层(源极金属垫片、所述的源极金属导线、所述的栅极金属垫片以及所述的栅极金属导线)都包括一层Al合金或Cu，其衬有一层Ti或Ti/TiN作为降阻层。所述第一类型沟槽栅为单一沟槽栅；所述第一类型沟槽栅为具有双栅电极的屏蔽沟槽栅，其包括一个位于较高部分的栅电极和一个位于较低部分的屏蔽栅电极，其中所述栅电极和所述屏蔽栅电极间通过一层电极隔离层实现彼此绝缘；若第一导电类型为N型时，第二导电类型为P型；若第一导电类型为P型时，第二导电类型为N型。
通过参考以下各个附图，阅读下文对优选实施例的详细描述，本发明的上述及其他目的和优点对于本领域的普通技术人员来说无疑是显而易见的。
附图说明
图1A是现有技术所揭示的一种MOSFET器件的俯视图。
图1B是现有技术所揭示的另一种MOSFET器件的俯视图。
图1C是现有技术所揭示的另一种MOSFET器件的俯视图。
图1D是现有技术所揭示的另一种MOSFET器件的俯视图。
图1E是现有技术所揭示的另一种MOSFET器件的俯视图。
图2A是根据本发明的一个优选的实施例的沟槽式半导体功率器件的俯视图。
图2B是根据本发明的另一个优选的实施例的，显示ESD箝位二极管在栅金属垫片和外围多晶硅区内掺杂区的俯视图。
图2C是根据本发明的另一个优选的实施例的俯视图。
图2D是根据本发明的另一个优选的实施例的俯视图。
图3是根据本发明的另一个优选的实施例的俯视图。
图4是根据本发明的另一个优选的实施例的俯视图。
图5是根据本发明的另一个优选的实施例的俯视图。
图6A是图3中E-F-G截面的一个优选的横截面图。
图6B是图3中E-F-G截面的一个另优选的横截面图。
图7是图3中E-F-G截面的另一个优选的横截面图。
图8A是图3中E-F-G截面的另一个优选的横截面图。
图8B是图3中E-F-G截面的另一个优选的横截面图。
图9是图3中E-F-G截面的另一个优选的横截面图。
具体实施方式
下面参照附图更详细地说明本发明，其中示出了本发明的优选实施例。本发明可以，但是以不同的方式体现，但是不应该局限于在此所述的实施例。例如，这里的说明更多地引用N沟道的半导体集成电路，但是很明显其他器件也是可能的。下文是通过参考各个附图来对实践本发明的优选实施例进行详细描述。一些方向术语，例如“顶部”、“底部”、“前”、“后”、“上方”、“下方”等，是参考各个附图的方向进行描述的。由于实施例中的元件可以被放置在许多不同的方向，因此，本发明中的方向术语只是用于描述而不能被视为对本发明的限制。应该理解的是，实施例中各种结构或者逻辑上的替代和修改都应该被涵盖在本发明的真正精神和范围内。因此，以下的详细描述不能被视为对本发明的限制，本发明的涵盖范围由附后的权利要求界定。应该理解的是，本发明中所描述的各个优选实施例的发明特征可以相互结合，有特别说明的除外。
图2A所示为根据本发明的一个优选的实施例的集成有栅-源ESD箝位二极管的半导体功率器件的俯视图，其包括一个用于与第一类型栅金属导线402实现栅极金属键合的栅金属垫片401，其正下方为一层作为ESD箝位二极管阳极的、并围绕沟槽式半导体功率器件外区区域的多晶硅层，以及一个第二类型栅金属导线403，其底部并没有连接至沟槽栅407的多晶硅层的存在，其中沟槽栅407用作栅接触区，第二类型栅金属导线403位于两有源区之间，并从ESD二极管阳极的一侧连至另外一侧，并连至沟槽栅。此沟槽式半导体功率器件还包括一个位于有源区顶部区域的顶部源金属垫片404，和一个位于有源区底部区域的底部源金属垫片405，用于与围绕栅金属垫片401外围区域的源金属导线406实现源极导线的键合，其中，底部源金属垫片405与源金属导线406，栅金属垫片401与第一类型栅金属导线402，第二类型栅金属导线403与沟槽栅，以及顶部源金属垫片404均为铝合金层，作为前金属层覆盖在Ti或Ti/TiN减阻层上。所述源金属垫片连接至有源区下方的多个第一类型沟槽栅周围的多个源区和体区，同时，源金属导线下方并无第一类型沟槽栅的存在。栅金属垫片401为正方形或圆形，并用于栅极导线键合，源金属垫片用于源极导线键合。该半导体功率器件还包括四种类型的实现源-栅间ESD保护的栅-源ESD箝位二极管：第一类型栅-源ESD箝位二极管连接于栅金属垫片和底部源金属垫片之间；第二类型栅-源ESD箝位二极管连接于源金属垫片和栅金属导线之间；第三类型栅-源ESD箝位二极管连接于栅金属垫片和源金属导线之间；第四类型栅-源ESD箝位二极管连接于栅金属导线与源金属导线之间。因此，根据本优选实施例改进的版图布局和器件结构，包括ESD箝位二极管的阳极，其连接至有源区内的沟槽栅，从而降低了栅电阻。
图2B所示为ESD二极管在栅金属垫片和外围多晶硅区域的掺杂区结构的俯视图。所述栅-源ESD箝位二极管包括多个背靠背的齐纳二极管，所述齐纳二极管由交替排列的第一导电类型的掺杂区(以n+为例)和第二导电类型的掺杂区(以p+为例)构成，且位于沟槽式功率器件的栅金属垫片401(如图2A所示，未示出)和第一类型栅金属导线402的正下方，如图2A所示。其中，该多个掺杂区为多个形成于多晶硅层上的n+和p+闭合环，这些闭合环不会造成栅-源ESD箝位二极管的边缘损伤，因此，本发明优化的布图和器件结构不会出现现有技术中存在的电流泄露通道。根据本发明的栅-源ESD箝位二极管还包括多个沟槽式ESD接触区，其填充以接触金属插塞，并延伸入每个栅-源ESD箝位二极管两端的掺杂区。以N沟道半导体功率器件为例，该沟槽式ESD接触区分别延伸入位于每个栅-源ESD箝位二极管两端的n+掺杂区。
图2C所示为根据本发明的另一个优选实施例，本发明与图2A所示发明的结构相似，除了在本发明的结构中(如图2C所示)，第二类型栅金属导线413从ESD二极管的阳极延伸入有源区，连接至沟槽栅。
图2D所示为根据本发明的另一个优选实施例，本发明与图2A所示发明的结构相似，除了在本发明的结构中(如图2D所示)，第二类型栅金属导线423从ESD二极管的阳极两侧延伸入有源区，连接至沟槽栅。
图3所示为根据本发明的另一个沟槽式半导体功率器件的优选实施例，在本优选实施例中，不仅栅金属垫片501连接至沟槽栅503，有源区周围的用作ESD二极管阳极的第一类型栅金属导线502也连接至器件边角和/或器件边角之间的沟槽栅。
图4所示为根据本发明的另一个优选实施例，本发明与图2A所示发明的结构相似，除了在本发明(如图4所示)的结构中，栅金属垫片511附近并无源金属导线的存在。
图5所示为根据本发明的另一个优选实施例，本发明与图2C所示发明的结构相似，除了在本发明(如图5所示)的结构中，栅金属垫片521附近并无源金属导线的存在。上述所以发明都大大降低了栅电阻Rg。
图6A所示为图3中E-F-G截面的一个优选的横截面图，以具有沟槽终端区的单沟槽栅N沟道MOSFET为例。其形成在一个半导体硅层上，该半导体硅层包括一个重掺杂N+衬底612和位于其上的N外延层611。形成多个沟槽栅614,642和671，彼此间由P体区615隔开，并延伸至N外延层611中。一个用于提供ESD保护的栅-源ESD箝位二极管，其包括由交替排列的n+掺杂区646和p+掺杂区647组成的多个背靠背的齐纳二极管，还进一步包括填充以接触金属插塞648-2的沟槽ESD接触区648-1，例如，一层衬以Ti/TiN或Co/TiN或Ta/TiN阻挡层的钨金属层，并透过接触金属隔层621，延伸至栅-源ESD箝位二极管的n+区646。所述栅-源ESD箝位二极管的沟槽式ESD接触区648-1，还连接至第一类型栅金属导线622。在沟槽式ESD接触区648-1的正下方，刻蚀缓冲沟槽栅642作为缓冲层以防止栅-体之间的短路。一个沟槽式体接触区639，填充以接触金属插塞640，其与接触金属插塞648-2实施方式一样，，例如，一层衬以Ti/TiN或Co/TiN或Ta/TiN阻挡层的钨金属层，并透过接触金属隔层621，延伸至刻蚀缓冲沟槽栅614，实现沟槽栅614和位于接触金属隔层621之上的第一类型栅金属导线622间的连接。一个终端区，包括多个由P体区615分隔开的第三类型沟槽栅671，其中，所述的多个第三类型沟槽栅671与第一类型沟槽栅642具有相同的结构，具有作为终端区沟槽式悬浮环的悬浮电压。
图6B所示是图3中E-F-G截面的一个优选的横截面图，其包括具有多个P体区悬浮环的单沟槽栅MOSFET。本发明所揭示的结构除了终端区外，均与图6A所示的结构一样。本发明所揭示的终端区包括：位于N外延层611的P体掺杂区654，填充以接触金属插塞656的沟槽式漏接触区655，所述沟槽式漏接触区655穿过接触隔层621，n+源掺杂区657以及至少围绕其底部的p+欧姆接触掺杂区623延伸入N外延层611中，其中，n+源掺杂区657可降低N外延层611和填充于沟槽式漏接触区655的接触金属插塞656之间的接触电阻，且沟槽式漏接触区655最终连接至位于N外延层611内的漏区。位于沟槽式漏接触区655中的接触金属插塞656的上表面并没有覆盖前金属层。
图7所示是图3中E-F-G截面的一个优选的横截面图，其包括具有沟槽式场板终端区的屏蔽栅沟槽式MOSFET。本发明所揭示的结构与图6A所示发明的结构类似，除了在本发明(图7所示)中，在沟槽714内的为双电极，所述双电极包括一个栅电极761和一个屏蔽栅电极762；以及位于终端区内的为沟槽式场板771。第一类型栅金属导线延伸至有源区中，并连接至第一类型沟槽栅的栅电极761。
图8A所示是图3中E-F-G截面的一个优选的横截面图，其包括一个具有沟槽式终端区的单沟槽栅P沟道MOSFET。图8A所示发明的结构与图6A所示发明的结构类似，除了在本发明(图7所示)中，衬底812，外延层811，区域815,846和847的掺杂类型与图6A所示发明的对应区域的掺杂类型相反。
图8B所示是图3中E-F-G截面的一个优选的横截面图，其包括具有多个P体区悬浮环的单沟槽栅P沟道MOSFET。图8B所示发明的结构与图6B所示发明的结构类似，除了在本发明(图8B所示)中，衬底812，外延层811，区域815,823，846，847和857的掺杂类型与图6B所示发明的对应区域的掺杂类型相反。
图9所示是图3中E-F-G截面的一个优选的横截面图，其包括具有沟槽式场板终端区的屏蔽栅沟槽式P沟道MOSFET。本发明所揭示的结构与图7所示发明的结构类似，除了在本发明(图9所示)中，衬底912，外延层911，区域915,946和947的掺杂类型与图7所示发明的对应区域的掺杂类型相反。
作为上面所描述的这些实施例的替换，半导体功率器件也可以被做成沟槽IGBT。就这点而言，一些术语，例如“源区”、“体区”、“漏区”应当相应地被改为“发射区”、“基区”、“集电区”。
虽然依照优选实施例对本发明进行了描述，但应该理解的是上述公开不能被视为是对本发明的限制。在阅读了上述公开的内容之后，各种替代和修改对于本技术领域的技术人员无疑是显而易见的。因此，附后的权利要求应被解释为涵盖落入本发明的真正精神和范围内的所有替代和修改。

Claims (15)

1.一种集成有栅-源箝位二极管的半导体功率器件，包括：
一个衬底，其具有第一导电类型；
一个外延层，位于所述衬底之上，且具有第一导电类型，其中所述外延层的掺杂浓度低于所述衬底；
位于有源区内的多个晶体管单元，并且所述的栅-源ESD箝位二极管包括由许多交替排列的第一导电类型的掺杂区和第二导电类型的掺杂区构成的多个背靠背的齐纳二极管；
多个第一类型沟槽栅，其被所述的第一导电类型的源区环绕，其中所述的源区位于所述的第二导电类型的体区中；
多个沟槽式源-体接触区，其穿过所述的源区并延伸入所述的体区中，所述的沟槽式源-体接触区填充以接触金属插塞并连接至所述的源极金属垫片；
所述的所述的栅-源ESD箝位二极管进一步包括：
一个栅金属垫片，连接至第一类型栅金属导线，其下方为多晶硅层，所述多晶硅层作为栅-源ESD箝位二极管的阳极并围绕半导体功率器件的外围区域；
第一类型栅-源ESD箝位二极管，其连接于所述栅金属垫片和源金属垫片之间；
第二类型栅-源ESD箝位二极管，其连接于第一类型栅金属导线和源金属垫片之间；和
第一类型栅金属导线延伸至有源区中，并连接至第一类型沟槽栅以降低栅电阻。
2.如权利要求1所述的半导体功率器件，其特征在于，所述第一类型栅导线从所述第一类型栅金属导线的任何部分延伸至有源区并连至所述第一类型沟槽栅，其中所述栅金属导线围绕所述功率器件的外围区域。
3.如权利要求1所述的半导体功率器件，其特征在于，所述第一类型栅导线穿过至少一个第二类型栅金属导线，延伸至有源区内并连至所述第一类型沟槽栅，其中所述第二类型栅金属导线下方并无所述多晶硅层的存在。
4.如权利要求1所述的半导体功率器件，其特征在于，还包括：
所述源金属垫片连至至少一个源金属导线，其中所述源金属导线位于所述栅金属垫片和所述栅金属导线之间，并与所述栅金属垫片和所述栅金属导线之间由金属间隙分隔开，其特征在于，所述源金属导线下方并无所述第一类型沟槽栅的存在；
一个第三类型栅-源ESD箝位二极管，连接至所述栅金属垫片和所述源金属导线之间；
一个第四类型栅-源ESD箝位二极管，连接至所述源金属导线和所述栅金属导线之间。
5.如权利要求1所述的半导体功率器件，其特征在于，每个所述栅-源ESD箝位二极管的所述交替掺杂区具有闭合的环状结构。
6.如权利要求1所述的半导体功率器件，其特征在于，所述体区位于所述栅-源ESD箝位二极管的下方，并进一步延伸至每两个相邻的第二类型沟槽栅之间，所述第二类型沟槽栅作为刻蚀-缓冲沟槽栅，且所述刻蚀-缓冲沟槽栅穿过所述体区，位于所述栅-源ESD箝位二极管中的沟槽ESD接触区的正下方，其特征在于，所述刻蚀-缓冲沟槽栅的沟槽宽度大于所述沟槽ESD接触区，以防止栅-体短路。
7.如权利要求1所述的半导体功率器件，其特征在于，还包括：
一个终端区，其包括至少一个具有悬浮电压的体掺杂区，其中所述的体掺杂区为所述的第二导电类型，且与所述体区同时形成；
一个源掺杂区，其为所述的第一导电类型，且位于所述的半导体功率器件的边缘区域，且与所述源区同时形成；
一个沟槽式漏接触区，其填充以所述接触金属插塞并穿过所述的源掺杂区并延伸入所述的半导体硅层中；
一个欧姆接触掺杂区，其为所述的第二导电类型，且位于所述源掺杂区下方并至少包围所述的沟槽式漏接触区；
并且所述欧姆接触掺杂区的掺杂浓度高于所述体区。
8.如权利要求7所述的半导体功率器件，其特征在于，所述的沟槽式漏接触区上方没有覆盖任何金属层。
9.如权利要求1所述的半导体功率器件，其特征在于，还包括一个终端区，所述终端区中包括多个具有悬浮电压的第三类型沟槽栅。
10.如权利要求1所述的半导体功率器件，其特征在于，所述的接触金属插塞为一层钨金属层，其衬以Ti/TiN或Co/TiN作为势垒金属层。
11.如权利要求1所述的半导体功率器件，其特征在于，所述前金属层为Al合金层，其衬以一层Ti或Ti/TiN作为降阻层。
12.如权利要求1所述的半导体功率器件，其特征在于，所述第一类型沟槽栅为单一沟槽栅。
13.如权利要求1所述的半导体功率器件，其特征在于，所述第一类型沟槽栅为具有双栅电极的屏蔽沟槽栅，其包括一个位于较高部分的栅电极和一个位于较低部分的屏蔽栅电极，其中所述栅电极和所述屏蔽栅电极间通过一层电极隔离层实现彼此绝缘；所述第一类型栅金属导线延伸至所述有源区内并连接至所述第一类型沟槽栅的所述栅电极。
14.如权利要求1所述的半导体功率器件，其特征在于，若所述的第一导电类型为N型，所述的第二导电类型为P型。
15.如权利要求1所述的半导体功率器件，其特征在于，若所述的第一导电类型为P型，所述的第二导电类型为N型。
CN202010913672.7A 2019-12-31 2020-09-03 一种集成静电放电保护二极管的半导体功率器件 Pending CN112038407A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/731,114 2019-12-31
US16/731,114 US20210202470A1 (en) 2019-12-31 2019-12-31 Mosfet with integrated esd protection diode having anode electrode connection to trenched gates for increasing switch speed

Publications (1)

Publication Number Publication Date
CN112038407A true CN112038407A (zh) 2020-12-04

Family

ID=73591370

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010913672.7A Pending CN112038407A (zh) 2019-12-31 2020-09-03 一种集成静电放电保护二极管的半导体功率器件

Country Status (2)

Country Link
US (1) US20210202470A1 (zh)
CN (1) CN112038407A (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11410990B1 (en) * 2020-08-25 2022-08-09 Semiq Incorporated Silicon carbide MOSFET with optional asymmetric gate clamp
WO2023002767A1 (ja) * 2021-07-21 2023-01-26 ローム株式会社 半導体装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070187753A1 (en) * 2004-04-30 2007-08-16 Siliconix Incorporated Super trench MOSFET including buried source electrode and method of fabricating the same
JP2009141007A (ja) * 2007-12-04 2009-06-25 Toyota Industries Corp 半導体装置
CN102244095A (zh) * 2010-05-11 2011-11-16 力士科技股份有限公司 一种功率半导体器件
US20130092976A1 (en) * 2011-10-17 2013-04-18 Force Mos Technology Co., Ltd. A semiconductor power device integratred with improved gate source esd clamp diodes
CN105355653A (zh) * 2010-06-01 2016-02-24 万国半导体股份有限公司 自对准工艺制备的半导体功率器件以及更加可靠的电接触
CN110277452A (zh) * 2018-03-17 2019-09-24 Ixys有限责任公司 嵌入式场极板场效应晶体管
CN110534574A (zh) * 2019-07-16 2019-12-03 娜美半导体有限公司 沟槽式金属氧化物半导体场效应管

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070187753A1 (en) * 2004-04-30 2007-08-16 Siliconix Incorporated Super trench MOSFET including buried source electrode and method of fabricating the same
JP2009141007A (ja) * 2007-12-04 2009-06-25 Toyota Industries Corp 半導体装置
CN102244095A (zh) * 2010-05-11 2011-11-16 力士科技股份有限公司 一种功率半导体器件
CN105355653A (zh) * 2010-06-01 2016-02-24 万国半导体股份有限公司 自对准工艺制备的半导体功率器件以及更加可靠的电接触
US20130092976A1 (en) * 2011-10-17 2013-04-18 Force Mos Technology Co., Ltd. A semiconductor power device integratred with improved gate source esd clamp diodes
CN110277452A (zh) * 2018-03-17 2019-09-24 Ixys有限责任公司 嵌入式场极板场效应晶体管
CN110534574A (zh) * 2019-07-16 2019-12-03 娜美半导体有限公司 沟槽式金属氧化物半导体场效应管

Also Published As

Publication number Publication date
US20210202470A1 (en) 2021-07-01

Similar Documents

Publication Publication Date Title
US8466514B2 (en) Semiconductor power device integrated with improved gate source ESD clamp diodes
US7800185B2 (en) Closed trench MOSFET with floating trench rings as termination
US7282386B2 (en) Schottky device and method of forming
US8362556B2 (en) Semiconductor device
JP5511124B2 (ja) 絶縁ゲート型半導体装置
US20120037983A1 (en) Trench mosfet with integrated schottky rectifier in same cell
US7956410B2 (en) Trench MOSFET with trench gates underneath contact areas of ESD diode for prevention of gate and source shortage
US8004036B2 (en) MOSFET-Schottky rectifier-diode integrated circuits with trench contact structures for device shrinkage and performance improvement
US20210119030A1 (en) Shielded gate trench mosfet integrated with super barrier rectifier
US8564053B2 (en) Trench MOSFET with trenched floating gates in termination
US8564052B2 (en) Trench MOSFET with trenched floating gates in termination
CN111081779B (zh) 一种屏蔽栅沟槽式mosfet及其制造方法
US8816348B2 (en) Shielded gate MOSFET-Schottky rectifier-diode integrated circuits with trenched contact structures
CN112216691B (zh) 一种集成箝位二极管的半导体功率器件
US10930774B2 (en) Shielded gate trench MOSFETs with floating trenched gates and channel stop trenched gates in termination
US11362207B2 (en) Semiconductor device
US10340147B2 (en) Semiconductor device with equipotential ring contact at curved portion of equipotential ring electrode and method of manufacturing the same
CN112038407A (zh) 一种集成静电放电保护二极管的半导体功率器件
JP2012049562A (ja) 半導体装置
US9257501B2 (en) Semiconductor device
US8853787B2 (en) High voltage semiconductor device
JP4964797B2 (ja) 半導体装置
KR20120004954A (ko) 반도체 장치
KR20150142220A (ko) 전력 반도체 소자
US20230215920A1 (en) Super barrier rectifier with shielded gate electrode and multiple stepped epitaxial structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20201204

WD01 Invention patent application deemed withdrawn after publication