CN112802749A - Trench IGBT structure polycrystalline silicon morphology optimization process - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
Abstract
The invention discloses a polysilicon appearance optimization process for a trench IGBT structure, which comprises an IGBT body and is characterized in that: the IGBT body is controlled by a grid electrode, an emitting electrode and a collector electrode, and the main static parameters of the IGBT body are as follows: blocking voltage V (BR) CES-withstand voltage of the device under the forward blocking state; on voltage drop VCE (on) -voltage drop of the device under the conducting state; threshold voltage VGE (th) -grid voltage VG required to be applied to the device from a blocking state to a conducting state, the carrier concentration of the trench gate IGBT is gradually increased, and the higher carrier concentration is beneficial to reducing on-state loss; on the other hand, the fewer carriers are, the more favorable the turn-off loss is, the more favorable the width of each IGBT conducting channel is to reduce UEmitter-Drain, the more favorable the trench gate IGBT vertical structure conducting channel is to design compact unit cells, namely more IGBT unit cells can be made on the same chip area, thereby increasing the width of the conducting channel, and in addition, UEmitter-Drain can be further reduced by eliminating JFET effect.
Description
Technical Field
The invention relates to the technical field of trench type IGBT semiconductors, in particular to a polysilicon morphology optimization process for a trench IGBT structure.
Background
Silicon has two allotropes of crystalline state and amorphous state, the crystalline state silicon is divided into monocrystalline silicon and polycrystalline silicon, the crystalline state silicon and the polycrystalline silicon have diamond crystal lattices, the crystal is hard and brittle, has metallic luster, can conduct electricity, but has lower electric conductivity than metal, and can increase along with the increase of temperature, the polycrystalline silicon has semiconductor property, the polycrystalline silicon is a form of simple substance silicon, when the molten simple substance silicon is solidified under the undercooling condition, silicon atoms are arranged into a plurality of crystal nucleuses in the form of the diamond crystal lattices, if the crystal nucleuses grow into crystal grains with different crystal face orientations, the crystal grains are combined to crystallize into the polycrystalline silicon, the polycrystalline silicon has the diamond crystal lattices, the crystal is hard and brittle, has metallic luster, can conduct electricity, but has lower electric conductivity than metal, and can increase along with the increase of temperature, the semiconductor property is provided, the melting point of the crystalline state silicon is 1410 ℃, the boiling point of the crystalline state silicon is 2355 ℃, the dense amorphous, it is a high and new technology product across multiple subjects and fields such as chemical industry, metallurgy, machinery, electronics, and the like, is an important basic raw material of semiconductor, large-scale integrated circuit and solar cell industry, is an extremely important intermediate product in silicon product industry chain, has the development and application level which becomes an important mark for measuring the comprehensive national strength, national defense strength and modernization level of a country, and along with the enhancement of application terminal requirements and the continuous promotion of energy efficiency requirements, the requirements on the performance of the power device are continuously improved, the continuous development of the device structure is promoted, the IGBT device is developed from a planar structure to a groove structure, the development of the groove device is also started by domestic power device wafer manufacturers, the IGBT and the derived structure thereof are also rapidly developed, but the device reliability is directly affected by the limitation of the equipment capability and the matching of the trench morphology and the process.
Disclosure of Invention
The invention aims to provide a process for optimizing the appearance of a polysilicon of a trench IGBT structure, so as to solve the problems in the background technology.
In order to achieve the purpose, the invention provides the following technical scheme: the utility model provides a polycrystalline silicon appearance optimization technology of trench IGBT structure, includes the IGBT body, its characterized in that: the IGBT body is controlled by a grid electrode, an emitting electrode and a collector electrode, and the main static parameters of the IGBT body are as follows:
(a) blocking voltage V (BR) CES-withstand voltage of the device under the forward blocking state;
(b) on voltage drop vce (on) -voltage drop of the device in the on state;
(c) threshold voltage vge (th) -the gate voltage VG that needs to be applied to the device from the blocking state to the conducting state.
A polysilicon appearance optimization process for a trench IGBT structure comprises the following steps:
the method comprises the following steps: a window area is formed on the upper surface of the N-type substrate, an oxide layer is grown in the window area through a selective oxidation method of silicon, and grooves are respectively etched on two sides of the window area;
step two: depositing a gate oxide layer on the upper surface of the N-type substrate and the side wall of the groove, depositing a polycrystalline silicon layer on the gate oxide layer, etching the polycrystalline silicon layer except the inside of the two grooves and the space between the two grooves, respectively forming a p-substrate area on the outer sides of the two grooves, and forming an N + injection area in the p-substrate area;
step three: depositing an isolation oxide layer on the p-substrate region and the polycrystalline silicon layer, and etching part of the isolation oxide layer to form a contact hole of the emitter;
step four: the groove is formed in the substrate, the heavily doped polysilicon structure is positioned at a lower part of the groove, and at least one side edge of the heavily doped polysilicon structure directly contacts the substrate;
step five: the grid polycrystalline silicon structure is positioned on the upper part of the groove, the grid dielectric layer is positioned between the grid polycrystalline silicon structure and the heavily doped polycrystalline silicon structure, and the doping of the heavily doped polycrystalline silicon structure is diffused outwards to form a heavily doped region;
step six: when the IGBT is switched on, an inversion channel of the P-type emitter region is vertical rather than horizontal, a large amount of electrons are injected, and the conductivity modulation efficiency near the emitter region is high;
step seven: from the collector to the emitter, the carrier concentration of the trench gate IGBT is gradually increased, the higher carrier concentration is beneficial to reducing on-state loss, and on the other hand, the fewer carriers are, the more beneficial to reducing turn-off loss is.
Preferably, the switching mechanism of the IGBT is the same as that of the VDMOS, and the MOS gate controls the on and off of the IGBT, except that the IGBT has one more PN junction at the drain than the VDMOS, and there is little sub-hole participation during the on process, which is a so-called conductance modulation effect, and this effect makes the on-state voltage drop of the IGBT at the same withstand voltage lower than that of the VDMOS, and because of the presence of holes in the drift region, these holes must be lost from the drift region when the IGBT is turned off.
Preferably, the Eon and Eoff of the IGBT are mainly determined by the gate resistance RG, the gate-source capacitance CGE and the gate-drain capacitance CGC, and the gain α PNP of the PNP transistor in the IGBT, and reducing RG, CGE and CGC can reduce Eon and Eoff at the same time, but it is noted that the influence of the emission efficiency γ PNP on the turn-on energy and the turn-off energy is opposite, i.e., α PNP is large.
Preferably, the oxide layer on the inner surface and the upper surface of the trench and the polysilicon filled in the trench are provided with a passivation layer between the first trench gate structure and the emitter metal.
Preferably, the UEmitter-Drain is the voltage between the emitter and the equivalent MOSFET Drain of the IGBT, the UDrain-Collector is the voltage between the Drain and the Collector, the width of each IGBT conducting channel is widened by 2mm, the UEmitter-Drain is the voltage between the emitter and the equivalent MOSFET Drain of the IGBT, and the UDrain-Collector is the voltage between the Drain and the Collector, the UEmitter-Drain can be reduced by increasing the width of each IGBT conducting channel, the conducting channel of the trench gate IGBT vertical structure is more favorable for designing compact unit cells, that is, more IGBT unit cells can be manufactured on the same chip area, so as to increase the width of the conducting channel, and in addition, the UEmitter-Drain can be further reduced by eliminating the JFET effect.
Preferably, the carrier concentration of the trench gate IGBT body is gradually increased from the collector to the emitter.
Preferably, the polysilicon is deposited with additional photoresist or BARC coating.
Preferably, in the fourth step, the polysilicon etch back menu is adjusted, so that the etching rate selection ratio of polysilicon to photoresist or polysilicon to BARC is greater than 0.8: 1.
compared with the prior art, the invention has the beneficial effects that:
1. according to the trench IGBT structure polycrystalline silicon morphology optimization process, the carrier concentration of the trench gate IGBT is gradually increased, and the higher carrier concentration is beneficial to reducing on-state loss; on the other hand, the fewer the carriers, the more advantageous the turn-off loss is.
2. According to the trench IGBT structure polycrystalline silicon appearance optimization process, the UEmiter-Drain is the voltage of an emitting electrode of an IGBT and an equivalent MOSFET Drain electrode, the UDrain-Collector is the voltage between the Drain electrode and a Collector electrode, the UEmiter-Drain can be reduced by increasing the width of each IGBT conducting channel, the conducting channel of the trench gate IGBT vertical structure is more beneficial to designing compact cells, namely more IGBT cells can be manufactured on the same chip area, so that the width of the conducting channel is increased, and in addition, the UEmiter-Drain can be further reduced by eliminating the JFET effect.
3. According to the trench IGBT structure polysilicon morphology optimization process, a photoresist or BARC coating step is added after polysilicon deposition to improve the planarization effect.
4. The polysilicon appearance optimization process for the trench IGBT structure adjusts a polysilicon back-etching menu, so that the etching rate selection ratio of polysilicon to photoresist or polysilicon to BARC is larger than 0.8: and 1, simultaneously controlling the etching selection ratio to etch downwards together in the etching process so as to obtain the result that the distance between the polycrystalline silicon and the surface of the groove is consistent.
Drawings
FIG. 1 is a graph of the internal carrier concentration of an IGBT body according to the present invention;
FIG. 2 is a schematic view of the internal structure of the trench IGBT body according to the present invention;
FIG. 3 is a schematic diagram of the electric field distribution and gate structure of the IGBT body of the invention;
FIG. 4 is a schematic diagram of a trench gate field termination IGBT structure of the present invention;
fig. 5 is a circuit diagram showing the present invention of the IGBT body.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1-5, the present invention provides a technical solution: the utility model provides a polycrystalline silicon appearance optimization technology of trench IGBT structure, includes the IGBT body, its characterized in that: the IGBT body is controlled by a grid electrode, an emitting electrode and a collector electrode, and the main static parameters of the IGBT body are as follows:
(a) blocking voltage V (BR) CES-withstand voltage of the device under the forward blocking state;
(b) on voltage drop vce (on) -voltage drop of the device in the on state;
(c) threshold voltage vge (th) -the gate voltage VG that needs to be applied to the device from the blocking state to the conducting state.
A polysilicon appearance optimization process for a trench IGBT structure comprises the following steps:
the method comprises the following steps: a window area is formed on the upper surface of the N-type substrate, an oxide layer is grown in the window area through a selective oxidation method of silicon, and grooves are respectively etched on two sides of the window area;
step two: depositing a gate oxide layer on the upper surface of the N-type substrate and the side wall of the groove, depositing a polycrystalline silicon layer on the gate oxide layer, etching the polycrystalline silicon layer except the inside of the two grooves and the space between the two grooves, respectively forming a p-substrate area on the outer sides of the two grooves, and forming an N + injection area in the p-substrate area;
step three: depositing an isolation oxide layer on the p-substrate region and the polycrystalline silicon layer, and etching part of the isolation oxide layer to form a contact hole of the emitter;
step four: the groove is formed in the substrate, the heavily doped polysilicon structure is positioned at a lower part of the groove, and at least one side edge of the heavily doped polysilicon structure directly contacts the substrate;
step five: the grid polycrystalline silicon structure is positioned on the upper part of the groove, the grid dielectric layer is positioned between the grid polycrystalline silicon structure and the heavily doped polycrystalline silicon structure, and the doping of the heavily doped polycrystalline silicon structure is diffused outwards to form a heavily doped region;
step six: when the IGBT is switched on, an inversion channel of the P-type emitter region is vertical rather than horizontal, a large amount of electrons are injected, and the conductivity modulation efficiency near the emitter region is high;
step seven: from the collector to the emitter, the carrier concentration of the trench gate IGBT is gradually increased, and the higher carrier concentration is beneficial to reducing on-state loss; on the other hand, the fewer the carriers, the more advantageous the turn-off loss is.
Further, the switching mechanism of the IGBT is the same as that of the VDMOS, and the MOS gate controls the on and off of the IGBT, except that the IGBT has one more PN junction at the drain than the VDMOS, and there is little sub-hole participation during the on process, which is called conductance modulation effect, which makes the on-state voltage drop of the IGBT at the same withstand voltage lower than that of the VDMOS.
Further, Eon and Eoff of the IGBT mainly depend on a gate resistance RG, a gate-source capacitance CGE and a gate-drain capacitance CGC, and a gain α PNP of a PNP triode in the IGBT, and reducing RG, CGE and CGC can reduce Eon and Eoff at the same time, but it is noted that the influence of emission efficiency γ PNP on the turn-on energy and the turn-off energy is opposite, that is, α PNP is large.
Furthermore, a passivation layer is arranged between the trench gate structure and the emitter metal, wherein the passivation layer is arranged on the oxide layers on the inner surface and the upper surface of the trench and the polycrystalline silicon filled in the trench.
Furthermore, the UEmitter-Drain is the voltage of an emitter of the IGBT and the Drain of the equivalent MOSFET, the UDrain-Collector is the voltage between the Drain and a Collector, the width of each IGBT conducting channel is widened by 2mm, the UEmitter-Drain is the voltage of the emitter of the IGBT and the Drain of the equivalent MOSFET, and the UDrain-Collector is the voltage between the Drain and the Collector, so that the UEmitter-Drain can be reduced by increasing the width of each IGBT conducting channel, the conducting channel of the trench gate IGBT vertical structure is more beneficial to designing compact unit cells, namely more IGBT unit cells can be manufactured on the same chip area, and the width of the conducting channel is increased, and in addition, the UEmitter-Drain can be further reduced by eliminating the JFET effect.
Further, from the collector to the emitter, the carrier concentration of the trench gate IGBT body is gradually increased, the higher carrier concentration is beneficial to reducing on-state loss, and on the other hand, the fewer carriers are beneficial to reducing turn-off loss.
Furthermore, a photoresist or BARC coating step is added after the polysilicon deposition to improve the planarization effect.
Further, in the fourth step, the polysilicon etching back menu is adjusted, so that the etching rate selection ratio of the polysilicon to the photoresist or the polysilicon to the BARC is larger than 0.8: 1.
the working principle is as follows: the method comprises the following steps: opening a window area on the upper surface of the N-type substrate, growing an oxide layer in the window area by a selective oxidation method of silicon, etching a groove on two sides of the window area respectively, and performing a second step: depositing a gate oxide layer on the upper surface of the N-type substrate and the side wall of the groove, depositing a polycrystalline silicon layer on the gate oxide layer, etching the polycrystalline silicon layer except the inside of the two grooves and the space between the two grooves, respectively forming a p-substrate area on the outer sides of the two grooves, and forming an N + injection area in the p-substrate area, wherein the third step is that: depositing an isolation oxide layer on the p-substrate area and the polycrystalline silicon layer, etching part of the isolation oxide layer to form a contact hole of the emitter, and the fourth step: forming a groove in the substrate, wherein the heavily doped polysilicon structure is positioned at a lower part of the groove, at least one side edge of the heavily doped polysilicon structure is in direct contact with the substrate, and the fifth step: the grid polycrystalline silicon structure is positioned on the upper part of the groove, the grid dielectric layer is positioned between the grid polycrystalline silicon structure and the heavy doping polycrystalline silicon structure, the doping of the heavy doping polycrystalline silicon structure is diffused outwards to form a heavy doping area, and the sixth step is that: when the IGBT is switched on, the inversion channel of the P-type emitter region is vertical rather than horizontal, a large amount of electrons are injected, the conductivity modulation efficiency near the emitter region is high, and the seventh step is that: from the collector to the emitter, the carrier concentration of the trench gate IGBT is gradually increased, and the higher carrier concentration is beneficial to reducing on-state loss; on the other hand, the fewer the carriers, the more advantageous the turn-off loss is.
In conclusion, according to the trench IGBT structure polycrystalline silicon morphology optimization process, the carrier concentration of the trench gate IGBT is gradually increased, and the higher carrier concentration is beneficial to reducing on-state loss; on the other hand, the fewer carriers are, the turn-off loss is reduced, the UEmitter-Drain is the voltage between an emitter and a Drain of an equivalent MOSFET of the IGBT, the UDrain-Collector is the voltage between the Drain and a Collector, the UEmitter-Drain can be reduced by increasing the width of a conducting channel of each IGBT, the conducting channel of the trench gate IGBT vertical structure is more beneficial to designing compact cells, namely more IGBT cells can be manufactured on the same chip area, so that the width of the conducting channel is increased, and in addition, the UEmitter-Drain can be further reduced by eliminating the JFET effect
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (8)
1. The utility model provides a polycrystalline silicon appearance optimization technology of trench IGBT structure, includes the IGBT body, its characterized in that includes the following step:
the method comprises the following steps: a window area is formed on the upper surface of the N-type substrate, an oxide layer is grown in the window area through a selective oxidation method of silicon, and grooves are respectively etched on two sides of the window area;
step two: depositing a gate oxide layer on the upper surface of the N-type substrate and the side wall of the groove, depositing a polycrystalline silicon layer on the gate oxide layer, etching the polycrystalline silicon layer except the inside of the two grooves and the space between the two grooves, respectively forming a p-substrate area on the outer sides of the two grooves, and forming an N + injection area in the p-substrate area;
step three: depositing an isolation oxide layer on the p-substrate region and the polycrystalline silicon layer, and etching part of the isolation oxide layer to form a contact hole of the emitter;
step four: the groove is formed in the substrate, the heavily doped polysilicon structure is positioned at a lower part of the groove, and at least one side edge of the heavily doped polysilicon structure directly contacts the substrate;
step five: the grid polycrystalline silicon structure is positioned on the upper part of the groove, the grid dielectric layer is positioned between the grid polycrystalline silicon structure and the heavily doped polycrystalline silicon structure, and the doping of the heavily doped polycrystalline silicon structure is diffused outwards to form a heavily doped region;
step six: when the IGBT is switched on, an inversion channel of the P-type emitter region is vertical rather than horizontal, a large amount of electrons are injected, and the conductivity modulation efficiency near the emitter region is high;
step seven: from the collector to the emitter, the carrier concentration of the trench gate IGBT is gradually increased, and the higher carrier concentration is beneficial to reducing on-state loss; on the other hand, the fewer the carriers, the more advantageous the turn-off loss is.
2. The process of claim 1 for optimizing the polysilicon morphology of the trench IGBT structure, wherein the process comprises the following steps: the IGBT is controlled to be switched on and switched off by an MOS grid, and a PN junction is added to the drain electrode of the IGBT compared with the VDMOS.
3. The process of claim 1 for optimizing the polysilicon morphology of the trench IGBT structure, wherein the process comprises the following steps: the Eon and Eoff of the IGBT depend mainly on the gate resistance RG.
4. The process of claim 1 for optimizing the polysilicon morphology of the trench IGBT structure, wherein the process comprises the following steps: and the passivation layer is arranged between the first trench gate structure and the emitter metal.
5. The process of claim 1 for optimizing the polysilicon morphology of the trench IGBT structure, wherein the process comprises the following steps: the UEmitter-Drain is the voltage of the emitter of the IGBT and the Drain of the equivalent MOSFET, the UDrain-Collector is the voltage between the Drain and the Collector, and the width of the conducting channel of each IGBT is widened by 2 mm.
6. The process of claim 1 for optimizing the polysilicon morphology of the trench IGBT structure, wherein the process comprises the following steps: the carrier concentration of the trench gate IGBT body is gradually increased from the collector to the emitter.
7. The process of claim 1 for optimizing the polysilicon morphology of the trench IGBT structure, wherein the process comprises the following steps: and adding photoresist or BARC coating after the polysilicon deposition.
8. The process of claim 7 for optimizing the polysilicon morphology of the trench IGBT structure, wherein the process comprises the following steps: in the fourth step, the polysilicon back etching menu is adjusted, and the etching rate selection ratio of the polysilicon to the photoresist or the polysilicon to the BARC is more than 0.8: 1.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070138542A1 (en) * | 2005-11-04 | 2007-06-21 | Infineon Technologies Ag | Vertical semiconductor device |
| US20070272978A1 (en) * | 2006-05-23 | 2007-11-29 | Infineon Technologies Austria Ag | Semiconductor device including a vertical gate zone, and method for producing the same |
| CN102339851A (en) * | 2010-07-15 | 2012-02-01 | 科轩微电子股份有限公司 | Power semiconductor with polysilicon structure at bottom of trench and method for manufacturing same |
| CN103839802A (en) * | 2012-11-23 | 2014-06-04 | 中国科学院微电子研究所 | Method for manufacturing groove-shaped IGBT structure |
-
2021
- 2021-01-06 CN CN202110011375.8A patent/CN112802749A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070138542A1 (en) * | 2005-11-04 | 2007-06-21 | Infineon Technologies Ag | Vertical semiconductor device |
| US20070272978A1 (en) * | 2006-05-23 | 2007-11-29 | Infineon Technologies Austria Ag | Semiconductor device including a vertical gate zone, and method for producing the same |
| CN102339851A (en) * | 2010-07-15 | 2012-02-01 | 科轩微电子股份有限公司 | Power semiconductor with polysilicon structure at bottom of trench and method for manufacturing same |
| CN103839802A (en) * | 2012-11-23 | 2014-06-04 | 中国科学院微电子研究所 | Method for manufacturing groove-shaped IGBT structure |
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Application publication date: 20210514 |