CN112798925B - Synchronous testing device and method based on automatic testing system - Google Patents
Synchronous testing device and method based on automatic testing system Download PDFInfo
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- CN112798925B CN112798925B CN202011415579.XA CN202011415579A CN112798925B CN 112798925 B CN112798925 B CN 112798925B CN 202011415579 A CN202011415579 A CN 202011415579A CN 112798925 B CN112798925 B CN 112798925B
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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Abstract
The invention discloses a synchronous testing device based on an automatic testing system, which comprises a driving unit and a comparison unit, wherein the driving unit is provided with a signal input end connected with a driving signal end of the automatic testing system and a tested integrated circuit clock, and the driving unit is provided with a signal output end connected with the signal input end of the tested integrated circuit; the comparison unit is provided with an input end connected with the automatic test system clock and the signal output end of the integrated circuit to be tested, and the comparison unit is provided with a signal output end connected with the automatic test system. The invention also discloses a synchronous testing method based on the automatic testing system, which comprises the following steps: 1. the driving unit sends a driving signal to the integrated circuit to be tested; 2. the comparison unit sends the response signal to the automatic test system; 3. the automatic test system compares the response signal to its clock. The invention can solve the problems of clock matching and synchronous testing between the automatic test system and the integrated circuit to be tested, and can be widely applied to the field of integrated circuit testing.
Description
Technical Field
The present invention relates to integrated circuit testing technologies, and in particular, to a synchronous testing apparatus and method based on an automatic testing system.
Background
Currently, testing of integrated circuits relies primarily on automatic test systems (ATE) to test, which apply stimulus vectors and receive responses to the integrated circuit under test (DUT). However, many integrated circuits have their own clocks, which have errors and cannot be completely matched with the clock period of the automatic test system, resulting in unstable test results. Therefore, it is necessary to invent a test method to solve the clock matching and synchronization test problem between the automatic test system and the integrated circuit under test.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned drawbacks of the prior art, and provides a synchronous testing apparatus and method based on an automatic testing system, so as to solve the problems of clock matching and synchronous testing between the automatic testing system and an integrated circuit under test.
The invention provides a synchronous testing device based on an automatic testing system, which comprises a driving unit and a comparison unit, wherein the driving unit and the comparison unit are connected with the automatic testing system and an integrated circuit to be tested; the comparison unit is provided with a signal input end which is respectively connected with the automatic test system clock and the signal output end of the integrated circuit to be tested, and the comparison unit is provided with a signal output end which is connected with the comparison signal end of the automatic test system.
In the above technical solution, the driving unit includes a delay module and a first synchronization module, a signal input end of the first synchronization module is provided with a signal input end connected to a driving signal end of the automatic test system and a clock of the integrated circuit to be tested, the delay module is provided with a signal output end connected to a signal input end of the integrated circuit to be tested, and a signal output end of the first synchronization module is connected to a signal input end of the delay module.
In the above technical solution, the comparison unit has a second synchronization module, the second synchronization module is provided with a signal input end connected to the automatic test system clock and the signal output end of the integrated circuit under test respectively, and the second synchronization module is provided with a signal output end connected to the comparison signal end of the automatic test system.
In the above technical solution, the first synchronization module and the second synchronization module are both latches.
In the above technical solution, the system further comprises a control unit for performing enable control and parameter control on the first synchronization module, the second synchronization module and the delay module, wherein a control end of the control unit is connected with a controlled end of the delay module, a control end of the control unit is connected with a controlled end of the first synchronization module, and a control end of the control unit is connected with a controlled end of the second synchronization module.
In the above technical solution, the control unit is a microcontroller as a CPU or a single chip microcomputer.
In the above technical solution, the delay module is an FPGA (Field Programmable Gate Array).
The invention also provides a synchronous testing method based on the automatic testing system, which comprises the following steps: s1, a driving unit processes a driving signal generated by an automatic testing system and sends the driving signal to an integrated circuit to be tested; s2, the comparison unit processes the response signal generated by the integrated circuit to be tested and then sends the processed response signal to the automatic test system; and S3, comparing and synchronizing the response signal and the automatic test system clock by the comparison signal end of the automatic test system.
In the above technical solution, in the step S1, before the driving unit processes the driving signal generated by the automatic test system, the control unit performs enable control and parameter control on the driving unit; in step S2, before the comparing unit processes the response signal generated by the tested integrated circuit, the control unit performs enable control and parameter control on the comparing unit.
In the above technical solution, the driving unit includes a delay module and a first synchronization module, the comparison unit has a second synchronization module, and the control unit is a microcontroller; the specific process of step S1 is as follows: s11, the control unit performs enabling control on the first synchronization module and performs programming processing on the delay module and the automatic test system clock; s12, the first synchronization module latches the driving signal generated by the automatic test system by taking the clock generated by the integrated circuit to be tested as a reference, so that the driving signal generated by the automatic test system is synchronous with the clock signal of the integrated circuit to be tested; s13, the delay module carries out delay processing on the latched driving signal to enable the driving signal to meet the requirement of the set-up time of the signal of the integrated circuit to be tested; the specific process of the step S2 is as follows: s21, the control unit performs enabling control on the second synchronous module and performs programming processing on the clock of the integrated circuit to be tested; and S22, the second synchronization module latches the response signal generated by the integrated circuit to be tested by taking the clock of the automatic test system as a reference, so that the response signal generated by the integrated circuit to be tested is synchronous with the clock period of the automatic test system.
The synchronous testing device and method based on the automatic testing system have the following beneficial effects: the first synchronization module latches the driving signal generated by the automatic test system by taking the clock generated by the integrated circuit to be tested as a reference, so that the driving signal generated by the automatic test system is synchronized with the integrated circuit to be tested. The delay module carries out delay processing on the drive signal after the latch processing so as to enable the drive signal to meet the requirement of the signal setup time of the integrated circuit to be tested, then the comparison unit processes the response generated by the integrated circuit to be tested and sends the response to the automatic test system, and the automatic test system carries out result comparison. The technical content can achieve the clock matching between the automatic test system and the self-owned clock integrated circuit and achieve the aim of synchronous test.
Drawings
FIG. 1 is a schematic structural diagram of a synchronous testing device based on an automatic testing system according to the present invention;
FIG. 2 is a schematic flow chart of a synchronous testing method based on an automatic testing system according to the present invention;
FIG. 3 is a schematic flow chart of step S1 of the synchronous testing method based on the automatic testing system according to the present invention;
fig. 4 is a schematic flow chart of step S2 in the synchronous testing method based on the automatic testing system according to the present invention.
Detailed Description
The invention is described in further detail below with reference to the following figures and examples, which should not be construed as limiting the invention.
Referring to fig. 1, the synchronous testing device based on the automatic testing system of the present invention comprises a driving unit and a comparing unit both connected with the automatic testing system and the integrated circuit under test, wherein the driving unit is provided with a signal input end respectively connected with a driving signal end of the automatic testing system and a clock of the integrated circuit under test, and is provided with a signal output end connected with the signal input end of the integrated circuit under test; the comparison unit is provided with a signal input end which is respectively connected with the automatic test system clock and the signal output end of the integrated circuit to be tested, and the comparison unit is provided with a signal output end which is connected with the comparison signal end of the automatic test system.
The driving unit comprises a delay module and a first synchronization module, wherein a signal input end of the first synchronization module is provided with a signal input end which is respectively connected with a driving signal end of the automatic test system and a clock of the integrated circuit to be tested, a signal output end which is connected with the signal input end of the integrated circuit to be tested is arranged on the delay module, and the signal output end of the first synchronization module is connected with the signal input end of the delay module.
The comparison unit is provided with a second synchronization module, the second synchronization module is provided with a signal input end which is respectively connected with the automatic test system clock and the signal output end of the integrated circuit to be tested, and the second synchronization module is provided with a signal output end which is connected with the comparison signal end of the automatic test system. The first synchronization module and the second synchronization module are latches.
The synchronous testing device based on the automatic testing system also comprises a control unit for performing enabling control and parameter control on the first synchronous module, the second synchronous module and the delay module, wherein the control end of the control unit is connected with the controlled end of the delay module, the control end of the control unit is connected with the controlled end of the first synchronous module, and the control end of the control unit is connected with the controlled end of the second synchronous module.
The control unit is a microcontroller as a CPU or a single chip microcomputer. The delay module is an FPGA.
Referring to fig. 2, the synchronous testing method based on the automatic testing system of the present invention includes the following steps:
s1, enabling control and parameter control are carried out on a driving unit by a control unit, the driving unit processes a driving signal generated by an automatic test system and then sends the driving signal to an integrated circuit to be tested, and the specific process is as follows, as shown in FIG. 3:
s11, the control unit performs enabling control on the first synchronization module and performs programming processing on the delay module and the automatic test system clock;
s12, the first synchronization module latches the driving signal generated by the automatic test system by taking the clock generated by the integrated circuit to be tested as a reference, so that the driving signal generated by the automatic test system is synchronous with the clock signal of the integrated circuit to be tested;
s13, the delay module carries out delay processing on the latched driving signal to enable the driving signal to meet the requirement of the set-up time of the signal of the integrated circuit to be tested;
s2, the control unit performs enabling control and parameter control on the comparison unit, the comparison unit processes a response signal generated by the integrated circuit to be tested and then sends the response signal to the automatic test system, and the specific process is as follows, and is shown in FIG. 4:
s21, the control unit performs enabling control on the second synchronous module and performs programming processing on the clock of the integrated circuit to be tested;
s22, the second synchronization module latches the response signal generated by the integrated circuit to be tested by taking the clock of the automatic test system as a reference, so that the response signal generated by the integrated circuit to be tested is synchronous with the clock period of the automatic test system;
and S3, comparing and synchronizing the response signal and the automatic test system clock by the comparison signal end of the automatic test system.
The counting principle of the invention is as follows:
the first synchronization module is mainly composed of a latch and takes a clock CLKDut generated by an integrated circuit to be tested as a reference. And carrying out latch processing on the driving signal generated by the automatic test system, and synchronizing the driving signal generated by the automatic test system with the clock signal of the integrated circuit to be tested. The delay module can be composed of a programmable clock chip and is used for carrying out delay processing on the drive signal after the latch processing so as to meet the requirement of the setup time of the signal of the integrated circuit to be tested.
The second synchronization module of the comparison unit mainly comprises a latch, and latches the response signal generated by the integrated circuit to be tested by taking the clock generated by the automatic test system as a reference, so that the response signal generated by the integrated circuit to be tested is synchronous with the clock CLKAte period of the automatic test system, and the automatic test system compares the result.
The control unit is composed of a microcontroller, including but not limited to a CPU or a single chip microcomputer. The method controls the enabling of the latch of the main part of the synchronous module in the test process, can program a programmable clock chip (a delay module of an FPGA), and carries out delay processing on the synchronized driving signal so as to meet the requirement of the setup time of the integrated circuit to be tested.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Those not described in detail in this specification are well within the skill of the art.
Claims (4)
1. The utility model provides a synchronous testing arrangement based on automatic test system which characterized in that: the automatic test system comprises a driving unit and a comparison unit which are connected with an automatic test system and an integrated circuit to be tested, wherein the driving unit is provided with a signal input end which is respectively connected with a driving signal end of the automatic test system and a clock of the integrated circuit to be tested, and the driving unit is provided with a signal output end which is connected with the signal input end of the integrated circuit to be tested; the comparison unit is provided with a signal input end which is respectively connected with the automatic test system clock and the signal output end of the integrated circuit to be tested, and the comparison unit is provided with a signal output end which is connected with the comparison signal end of the automatic test system;
the driving unit comprises a delay module and a first synchronization module, wherein a signal input end of the first synchronization module is provided with a signal input end which is respectively connected with a driving signal end of the automatic test system and a clock of the integrated circuit to be tested, the delay module is provided with a signal output end which is connected with the signal input end of the integrated circuit to be tested, and the signal output end of the first synchronization module is connected with the signal input end of the delay module;
the comparison unit is provided with a second synchronization module, the second synchronization module is provided with a signal input end which is respectively connected with the automatic test system clock and the signal output end of the integrated circuit to be tested, and the second synchronization module is provided with a signal output end which is connected with the comparison signal end of the automatic test system;
the first synchronization module and the second synchronization module are latches;
the control unit is used for performing enabling control and parameter control on the first synchronization module, the second synchronization module and the delay module, the control end of the control unit is connected with the controlled end of the first synchronization module, and the control end of the control unit is connected with the controlled end of the second synchronization module.
2. The automatic test system based synchronous test device of claim 1, wherein: the control unit is a microcontroller as a CPU or a single chip microcomputer.
3. The automated test system-based synchronous test apparatus of claim 2, wherein: the delay module is an FPGA.
4. A synchronous test method based on an automatic test system is characterized in that: the method comprises the following steps:
s1, a driving unit processes a driving signal generated by an automatic testing system and sends the driving signal to an integrated circuit to be tested;
s2, the comparison unit processes the response signal generated by the integrated circuit to be tested and then sends the processed response signal to the automatic test system;
s3, a comparison signal end of the automatic test system compares and synchronizes a response signal with an automatic test system clock;
in the step S1, before the driving unit processes the driving signal generated by the automatic test system, the control unit performs enable control and parameter control on the driving unit;
in the step S2, before the comparison unit processes the response signal generated by the tested integrated circuit, the control unit performs enable control and parameter control on the comparison unit;
the driving unit comprises a delay module and a first synchronization module, the comparison unit is provided with a second synchronization module, and the control unit is a microcontroller;
the specific process of step S1 is as follows:
s11, the control unit performs enabling control on the first synchronization module and performs programming processing on the delay module and the automatic test system clock;
s12, the first synchronization module latches the driving signal generated by the automatic test system by taking the clock generated by the integrated circuit to be tested as a reference, so that the driving signal generated by the automatic test system is synchronous with the clock signal of the integrated circuit to be tested;
s13, the delay module carries out delay processing on the latched driving signal to enable the driving signal to meet the requirement of the set-up time of the signal of the integrated circuit to be tested;
the specific process of the step S2 is as follows:
s21, the control unit performs enabling control on the second synchronous module and performs programming processing on the clock of the integrated circuit to be tested;
and S22, the second synchronization module latches the response signal generated by the integrated circuit to be tested by taking the clock of the automatic test system as a reference, so that the response signal generated by the integrated circuit to be tested is synchronous with the clock period of the automatic test system.
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| KR100736676B1 (en) * | 2006-08-01 | 2007-07-06 | 주식회사 유니테스트 | Tester for testing semiconductor device |
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