TWI490515B - Automatic test equipment and clock synchronization method - Google Patents

Description

Automatic test equipment and clock synchronization method

The invention relates to an automatic test device and a clock synchronization method, and in particular to an automatic test device and a clock synchronization method for quickly synchronizing clocks of different detection modules.

Automatic test equipment (ATE), such as semiconductor integrated circuit (IC) test machines, often encounter different test speed requirements under the same integrated circuit, resulting in various tests in automatic test equipment. The signal of the module generates a frequency offset or a phase offset, so that the clock rate (also known as the clock speed) of each detection module is not synchronized.

After the automatic test equipment detects the above-mentioned integrated circuit, it is necessary to synchronize the clocks of the respective detection modules in the automatic test equipment, otherwise the next stage of the detection process is not performed.

However, the synchronization architecture of the conventional automatic test equipment mostly synchronizes by delaying or accelerating the clock of each detection module. In addition to complicated and complicated control, it takes time to synchronize, and each detection module When the clock corresponds to the time axis, the alignment synchronization cannot be accurately performed, resulting in subsequent The test procedure may be inaccurate.

In view of the above problems, the present disclosure provides an automatic test device and a clock synchronization method, which perform a synchronization process on a plurality of detection modules in an automatic test device, so that the plurality of detection modules of the synchronization program are executed. The clock can be synchronized to the preset clock.

According to an embodiment of the present disclosure, an automatic test device includes a first detection module, a second detection module, a clock generation module, and a processing module. The processing module is electrically connected to the first detecting module, the second detecting module and the clock generating module. The first detection module operates on the first initial clock. The second detection module operates on the second initial clock. The clock generation module is used to generate a preset clock. The processing module is configured to provide a trigger signal to the first detecting module and the second detecting module, where the trigger signal is used to instruct the first detecting module and the second detecting module to perform a synchronization process. In the synchronization process, the first detection module resets the clock of the first detection module in the first time interval, and sets the time of the first detection module by referring to the preset clock after the end of the first time interval. The pulse is the first clock; the second detecting module resets the clock of the second detecting module in the second time interval, and sets the time of the second detecting module with reference to the preset clock after the second time interval ends. The pulse is the second clock.

According to a clock synchronization method in an embodiment of the present disclosure, the pulse synchronization method is applicable to an automatic test device, and the automatic test device includes at least a first detection module and a second detection module. Wherein, the first detection module and The second detecting module operates on the first initial clock and the second initial clock, respectively. The flow of the steps of the clock synchronization method is as follows. First, provide a preset clock. Then, a trigger signal is generated, and the trigger signal is used to instruct the first detection module and the second detection module to perform a synchronization process. Finally, in the synchronization process, the first detection module resets the clock of the first detection module in the first time interval, and sets the time of the first detection module with reference to the preset clock after the end of the first time interval. The pulse is the first clock. At the same time, in the synchronization process, the second detection module resets the clock of the second detection module in the second time interval, and sets the second detection module with reference to the preset clock after the second time interval ends. The clock is the second clock.

In summary, the present disclosure provides an automatic test device and a clock synchronization method, which provide a stable preset clock, and when a plurality of detection modules in an automatic test device execute a synchronization program, the detection modes are The groups reset their respective clocks in their respective time intervals, and set their respective initial clocks as preset clocks after the respective time intervals have ended, so that the plurality of detections after the synchronization procedure is executed The clock of the module will be synchronized to the preset clock.

The above description of the disclosure and the following description of the embodiments of the present invention are intended to illustrate and explain the spirit and principles of the invention, and to provide further explanation of the scope of the invention.

1‧‧‧Automatic test equipment

10‧‧‧First detection module

12‧‧‧Second test module

14‧‧‧ clock generation module

16‧‧‧Processing module

T1‧‧‧ first time interval

T2‧‧‧ second time interval

T1~t5‧‧‧ time point

S300~S304‧‧‧Step process

Figure 1 is a diagram showing the work of an automatic test equipment according to an embodiment of the present disclosure. Can block diagram.

Fig. 2 is a waveform diagram of the automatic test apparatus according to Fig. 1 when the synchronization procedure is executed.

Figure 3 is a flow chart showing the steps of the clock synchronization method according to an embodiment of the present disclosure.

The detailed features and advantages of the present invention are set forth in the Detailed Description of the Detailed Description of the <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; The objects and advantages associated with the present invention can be readily understood by those skilled in the art. The following examples are intended to describe the present invention in further detail, but are not intended to limit the scope of the invention.

[An example of an automatic test equipment]

Please refer to FIG. 1 and FIG. 2 together. FIG. 1 is a functional block diagram of an automatic test equipment according to an embodiment of the present disclosure; and FIG. 2 is a diagram of an automatic test apparatus according to FIG. 1 when performing a synchronization procedure. Waveform diagram. As shown in FIG. 1 , the automatic test equipment 1 mainly includes a first detection module 10 , a second detection module 12 , a clock generation module 14 , and a processing module 16 . The processing module 16 is electrically connected to the first detecting module 10, the second detecting module 12, and the clock generating module 14. The function modules of each part of the automatic test equipment 1 will be described in detail below.

The first detecting module 10 is configured to detect a first device to be tested (device under test, DUT), and detecting the first device under test when operating at the first initial clock (for example, the clock of the first detecting module 10 in FIG. 2 before time point t1). The second detecting module 12 is configured to detect a second device to be tested, and is operated when the second initial clock (for example, the clock of the first detecting module 10 in FIG. 2 before the time point t1) The second device under test performs detection. In practice, the device to be tested may be a chip in an interface card such as a display card or a network card (network interface card), but is not limited thereto.

In addition, the present invention does not limit the number of detection modules and the type of devices to be tested that can be detected by the detection module. In other words, the first detection module 10 and the second detection module 12 can simultaneously detect the same type. Device to be tested. In the embodiment of the present invention, the frequency of the first initial clock when the first detecting module 10 detects the first device to be tested is smaller than the second initial time when the second detecting module 12 detects the second device to be tested. The frequency of the pulse is such that the first initial clock of the first detection module 10 is not synchronized with the second initial clock of the second detection module 12.

The clock generation module 14 is configured to generate a preset clock. In practice, the clock generation module 14 is an oscillator, and the oscillator can adjust the period of the output clock according to the actual demand of the automatic test equipment 1, in other words, the preset clock. The period is a variable period.

The processing module 16 is configured to provide a trigger signal to the first detecting module 10 and the second detecting module 12 (such as the time point t1 to the time point t2 in FIG. 2) The trigger signal is used to instruct the first detecting module 10 and the second detecting module 12 to execute a sync procedure. In practice, the processing module 16 can be a central processing unit (CPU) or a micro control unit (MCU), but is not limited thereto. It should be noted that the waveform of the trigger signal can be an arbitrary waveform, and the pulse width of the trigger signal is an integer multiple of the period of the preset clock. In the embodiment of the present invention, the waveform of the trigger signal is a square wave, and the pulse width of the trigger signal is a preset clock of one cycle. In addition, the trigger signal may be generated by an inspector triggering an input module (such as a knob, a button or a touch panel) of the automatic test device 1 or generated by an operating system in the automatic test device 1 according to the setting. This is not limited.

In the actual operation, after the first detection module 10 and the second detection module 12 receive the trigger signal provided by the processing module 16, the first detection module 10 and the second detection module 12 will start executing. Synchronization program. In the synchronization process, the first detecting module 10 resets the clock of the first detecting module 10 in the first time interval T1 (ie, the time interval from the time point t2 to the time point t5 in FIG. 2), and After the first time interval T1 is completed, the clock of the first detecting module 10 is set as the first clock by referring to the preset clock (ie, the clock of the first detecting module 10 in FIG. 2 after the time point t5). Therefore, the first clock of the first detecting module 10 after the time point t5 can be synchronized with the preset clock.

On the other hand, in this synchronization procedure, the second detection module 12 is at the second time interval T2 (ie, the time from the time point t3 to the time point t4 in FIG. 2). In the interval, the clock of the second detecting module 12 is reset, and after the second time interval T2 ends, the clock of the second detecting module 12 is set as the second clock by referring to the preset clock (ie, FIG. 2) The second detection module 12 is in the clock after time point t4, so that the second clock of the second detection module 12 after the time point t4 can be synchronized with the preset clock. Therefore, the first clock of the first detecting module 10 after the time point t5 and the second clock of the second detecting module 12 after the time point t5 are synchronized with the preset clock, so that the automatic test is performed. The first detection module 10 and the second detection module 12 in the device 1 can perform the detection process of the next stage.

It should be noted that, in the embodiment of the present invention, the time interval in which the first detection module 10 and the second detection module 12 receive the trigger signal and start the synchronization process is defined as the synchronization time interval (ie, FIG. 2). The time interval from the time point t2 to the time point t5), the synchronization time interval is continued after the end of the trigger signal, and the length of the synchronization time interval is greater than or equal to the time interval at which the initial clock is slow, which is initially set in this embodiment. The time interval in which the clock is slow is the first time interval T1. In addition, the synchronization time interval may be greater than or equal to the pulse width of the trigger signal, and the synchronization time interval may be arbitrarily increased or decreased according to the actual demand and complexity of the automatic test equipment 1 when detecting the device under test.

It should be noted that the first time interval T1 has at least two cycles of the first initial clock, and the second time interval T2 has at least two periods of the second initial clock. The first detection module 10 is in the first period of the first time interval T1 (ie, the first initial clock occurring in the first time interval T1) and the second detection module. 12 at the second time interval T2 The clock of the first period (ie, the second initial clock that occurs in the second time interval T2) is used to indicate that the first detection module 10 and the second detection module 12 are heavy. Set (reset). The clock of the second period of the first detecting module 10 in the first time interval T1 (that is, the first initial clock occurring in the second time interval T1) and the second detecting module 12 The clock of the second period in the second time interval T2 (ie, the second initial clock occurring in the second time interval T2) is used to indicate the first detection module 10 and the second detection, respectively. The module 12 performs a set.

In more detail, when the first detecting module 10 and the second detecting module 12 are reset, the data of the temporary register in the first detecting module 10 and the temporary in the second detecting module 12 are respectively cleared. The data of the register is set in the first detecting module 10 and the second detecting module 12, and the data of the register in the first detecting module 10 and the register in the second detecting module 12 The data is set to the original initial value. Therefore, during the synchronization time interval, the first detection module 10 and the second detection module 12 respectively operate at the first initial clock and the second initial clock for at least two cycles, and will be first after the operation ends. The initial clock and the second initial clock are set to operate as preset clocks, so that the clock of the first detecting module 10 and the clock of the second detecting module 12 are synchronized with each other after the synchronization time interval.

In the embodiment of the present invention, the first initial clock has two periods in the first time interval T1, and the second initial clock has two periods in the second time interval T2, and the first detecting module 10 is The first initial clock is less than The second initial clock of the second detection module 12, so the first time interval T1 will be greater than the second time interval T2.

[Embodiment of Clock Synchronization Method]

Please refer to FIG. 1 , FIG. 2 and FIG. 3 together. FIG. 3 is a flow chart of the steps of the clock synchronization method according to an embodiment of the present disclosure. As shown in FIG. 3, the pulse synchronization method is applied to the automatic test equipment 1 of FIG. 1 , and the automatic test equipment 1 includes at least a first detection module 10 and a second detection module 12, and the first detection mode. The group 10 and the second detection module 12 respectively operate on the first initial clock and the second initial clock before performing the clock synchronization method. The steps of each step in the clock synchronization method will be described in detail below.

In step S300, the automatic test equipment 1 provides a preset clock. In step S302, the automatic test device 1 generates a trigger signal, wherein the trigger signal is used to instruct the first detection module 10 and the second detection module 12 to perform a synchronization process. In step S304, the first detecting module 10 starts to execute the synchronization process. At this time, the first detecting module 10 resets the clock of the first detecting module 10 in the first time interval T1, and at the first time. After the interval T1 ends, the clock of the first detecting module 10 is set as the first clock by referring to the preset clock. On the other hand, in step S306, the second detecting module 12 also starts to execute the synchronization process. At this time, the second detecting module 12 resets the clock of the second detecting module 12 in the second time interval T2. And after the second time interval T2 ends, the clock of the second detecting module 12 is set as the second clock with reference to the preset clock. Thereby, the first clock and the first detection module 10 after executing the synchronization procedure The second clock after the second detection module 12 executes the synchronization program is synchronized with the preset clock.

It should be noted that the first time interval T1 has at least two cycles of the first initial clock, and the second time interval T2 has at least two periods of the second initial clock. In addition, the clock of the first period of the first detecting module 10 during the first time interval T1 and the clock system of the first period of the second detecting module 12 during the second time interval T2 are respectively used to indicate The first detecting module 10 and the second detecting module 12 are reset; the clock of the second period of the first detecting module 10 in the first time interval T1 and the second detecting module 12 are at the second time interval. The clock of the second period in T2 is used to instruct the first detection module 10 and the second detection module 12 to perform setting.

In addition, the waveform of the trigger signal is an arbitrary waveform, and the pulse width of the trigger signal is an integer multiple of the period of the preset clock. In addition, when the frequency of the first initial clock of the first detecting module 10 is less than the frequency of the second initial clock of the second detecting module 12, the first time interval T1 is greater than the second time interval T2.

In the embodiment of the present invention, the time interval when the first detecting module 10 and the second detecting module 12 execute the synchronization program is defined as a synchronization time interval, and the synchronization time interval is continued after the trigger signal ends, and the synchronization is performed. The length of the time interval is greater than or equal to the time interval at which the initial clock is slower. In addition, the synchronization time interval is greater than or equal to the pulse width of the trigger signal.

[Possible effects of the examples]

In summary, the embodiments of the present invention provide an automatic test device and a clock synchronization method, which provide a stable preset clock, and when multiple detection modules in an automatic test device execute a synchronization program, these The detection module resets the respective clocks in their respective time intervals, and sets the respective initial clocks as preset clocks after the end of the respective time intervals, so that the plurality of times after the execution of the synchronization procedure is performed The clocks of each detection module are synchronized with the preset clock. Therefore, the automatic test equipment and the clock synchronization method of the embodiment of the present invention can perform the next stage of the detection process, and can restart the automatic test equipment in a very short time. The clocks of the plurality of detection modules are synchronized to facilitate the detection personnel to continuously carry out the detection process of the next stage, which is very practical.

Although the present invention has been disclosed above in the above embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

T1‧‧‧ first time interval

T2‧‧‧ second time interval

T1~t5‧‧‧ time point

Claims (8)

A clock synchronization method is applicable to an automatic test device. The automatic test device includes at least a first detection module and a second detection module. The first detection module and the second detection module respectively operate on a The first initial clock and the second initial clock, the synchronization method includes: providing a preset clock; generating a trigger signal, the trigger signal is used to instruct the first detecting module and the second detecting module to execute a synchronization program, in the synchronization process, the first detection module resets the clock of the first detection module in a first time interval, and refers to the preset clock after the first time interval ends. Setting the clock of the first detecting module to be a first clock, the first clock is synchronized with the preset clock; and in the synchronizing program, the second detecting module is in a second time interval Resetting the clock of the second detecting module, and setting the clock of the second detecting module to a second clock according to the preset clock after the second time interval ends, the second clock synchronization At the preset clock. The clock synchronization method of claim 1, wherein the first initial time interval has at least two periods in the first time interval, and the second initial clock period has at least two periods in the second time interval And the clock of the first period of the first detecting module in the first time interval and the clock system of the first period of the second detecting module in the second time interval are respectively used to indicate The first detecting module and the second detecting module are reset, the first The clock of the second period of the detecting module in the first time interval and the clock system of the second period of the second detecting module in the second time interval are respectively used to indicate the first detecting The module is set with the second detection module. The clock synchronization method of claim 1, wherein the first time interval is greater than the second time interval when the frequency of the first initial clock is less than the frequency of the second initial clock. The clock synchronization method of claim 1, wherein the time interval when the first detection module and the second detection module execute the synchronization program is defined as a synchronization time interval, and the synchronization time interval is continued After the trigger signal ends, the length of the synchronization time interval is greater than or equal to the time interval at which the initial clock is slow. An automatic testing device includes: a first detecting module operating on a first initial clock; a second detecting module operating in a second initial clock; and a clock generating module for generating a pre- And a processing module electrically connected to the first detecting module, the second detecting module and the clock generating module, for the first detecting module and the second detecting module Providing a trigger signal for instructing the first detection module and the second detection module to perform a synchronization process; wherein, in the synchronization process, the first detection module is within a first time interval Reset the clock of the first detection module, and during the first time Referring to the preset clock, the clock of the first detecting module is set as a first clock, and the second detecting module resets the clock of the second detecting module in a second time interval. And setting the clock of the second detecting module to a second clock by using the preset clock after the second time interval ends, wherein the first clock and the second clock are synchronized with the preset Clock. The automatic test device of claim 6, wherein the first time interval has at least two cycles of the first initial clock, and the second time interval has at least two cycles of the second initial clock, And the clock of the first period of the first detecting module in the first time interval and the clock system of the first period of the second detecting module in the second time interval are respectively used to indicate the The first detecting module and the second detecting module are reset, and the clock of the second period of the first detecting module in the first time interval and the second time interval of the second detecting module are The clock of the second period is used to indicate that the first detection module and the second detection module are set. The automatic test device of claim 6, wherein the first time interval is greater than the second time interval when the frequency of the first initial clock is less than the frequency of the second initial clock. The automatic test device of claim 6, wherein the time interval between the first detection module and the second detection module when the synchronization program is executed is defined as a synchronization time interval, and the synchronization time interval is followed by Trigger signal After the end, and the length of the synchronization time interval is greater than or equal to the time interval at which the initial clock is slow.