CN107463759B - Simulation verification device and simulation verification method of timer - Google Patents
Simulation verification device and simulation verification method of timer Download PDFInfo
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- CN107463759B CN107463759B CN201710839662.1A CN201710839662A CN107463759B CN 107463759 B CN107463759 B CN 107463759B CN 201710839662 A CN201710839662 A CN 201710839662A CN 107463759 B CN107463759 B CN 107463759B
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Abstract
The embodiment of the invention discloses a simulation verification device and a simulation verification method of a timer. Wherein, this emulation verifying attachment of timer includes: a register configuration component and a predicate verification component; the register configuration component is used for generating configuration data for configuring a first register and/or a second register of the timer module; the assertion verification assembly comprises a register checking module, the register checking module comprises register verification units which are in one-to-one correspondence with the first register and/or the second register, any register verification unit is used for comparing the register data with the data of the corresponding first register or second register, and the correctness of the configuration of the first register or the second register is checked through the comparison result. The technical scheme of the embodiment of the invention can realize the checking of the correctness of the data generated by the intermediate link in the timer module.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a simulation verification device and a simulation verification method of a timer.
Background
A timer is a type of module in an MCU (Microcontroller Unit) that measures time. The MCU can realize the generation and control of a plurality of complex time sequences, and the timer is actually a key module of the generation and control functions of the complex time sequences. On the basis of ordinary timing, the timer can configure an internal control register according to user requirements, generate a plurality of controllable waveforms, or realize control over a plurality of peripherals. The timer has evolved from a simple timing function to a complex waveform generation module, and has become an important function in the practical application of the MCU.
The method comprises the steps of developing a timer with a specific function, generally describing the timer module with the specific function through a hardware description language (verilog or VHD L) to simulate a real timer, verifying the correctness of the timer module through building a verification environment, generally comprising an excitation generating component, an expected data generating component, a receiver component, a data comparison component and a coverage rate collecting component in the normal verification environment, wherein the excitation generating component generates excitation signal data used for testing through a randomization mode, drives the timer module and the expected data generating component, the expected data generating component generates expected values of output data based on parameter configuration according to the excitation signal data, the receiver component receives the final output data of the timer module, and sends the data to the data comparison component after packaging processing.
Disclosure of Invention
The embodiment of the invention provides a simulation verification device and a simulation verification method of a timer, which are used for checking the correctness of data generated by an intermediate link in a timer module, so that the aims of quickly positioning an error position and greatly shortening debugging time are fulfilled.
In a first aspect, an embodiment of the present invention provides a simulation verification apparatus for a timer, wherein,
the timer module comprises a plurality of input capture channels, a plurality of output generation channels and a register submodule;
wherein, the register submodule includes: a plurality of first registers provided corresponding to the respective input capture channels and a plurality of second registers provided corresponding to the respective output generation channels;
any input capturing channel comprises a plurality of first workers, the plurality of first workers carry out data transmission according to a first preset connection mode, and the working mode of the first workers is determined according to data of a first register corresponding to the first workers so as to realize a preset input capturing function;
any output generation channel comprises a plurality of second workers, the plurality of second workers carry out data transmission according to a second preset connection mode, and the working mode of the second workers is determined according to the data of a second register corresponding to the second workers so as to realize a preset output generation function;
the simulation verification device comprises: a register configuration component and a predicate verification component;
a register configuration component for generating configuration data for configuring the first register and/or the second register;
the timer module is used for configuring the data of the first register and/or the second register according to the configuration data;
the assertion verification assembly comprises a register checking module, wherein the register checking module comprises register verification units which are in one-to-one correspondence with the first register and/or the second register, any register verification unit is used for generating register data according to the configuration data generated by the register configuration assembly, the register data is compared with the data of the corresponding first register or second register, if the comparison result is the same, the configuration of the first register or the second register is verified to be correct, and if the comparison result is different, the configuration of the first register or the second register is verified to be wrong.
In a second aspect, an embodiment of the present invention further provides a simulation verification method for a timer, which is implemented based on the simulation verification apparatus for a timer provided in any embodiment of the present invention, and the method includes:
the timer module configures the data of the first register and/or the second register according to the configuration data generated by the register configuration component;
the timer module outputs the data of the first register and/or the second register to the register checking module.
In a third aspect, an embodiment of the present invention further provides a simulation verification method for a timer, which is implemented based on the simulation verification device for a timer provided in any embodiment of the present invention, and the method includes:
any register verification unit generates register data according to the configuration data of the register configuration component;
the assertion verification component introduces data of each first register and/or second register of the timer module;
any register verification unit compares the register data with the data of the corresponding first register or second register;
if the comparison result is the same, verifying that the first register or the second register is correctly configured;
and if the comparison results are different, verifying that the first register or the second register is configured wrongly.
According to the technical scheme of the embodiment of the invention, the configuration data for configuring the first register and the second register is generated through the register configuration component, any register verification unit in the assertion verification component generates register data according to the configuration data generated by the register configuration component, the register data is compared with the data of the first register or the second register of the corresponding timer module, if the comparison result is the same, the configuration of the first register or the second register is verified to be correct, and if the comparison result is different, the configuration of the first register or the second register is verified to be wrong, so that the correctness of the data configured by the first register and the second register in the timer module is checked, the error position can be quickly positioned, and the purpose of greatly shortening the debugging time is realized.
Drawings
Fig. 1 is a schematic structural diagram of a simulation verification apparatus for a timer according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an input capture channel of a timer module according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an output generation channel of a timer module according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a simulation verification apparatus for a timer according to another embodiment of the present invention;
FIG. 5 is a schematic structural diagram of a simulation verification apparatus for a timer according to another embodiment of the present invention;
fig. 6 is a flowchart of a simulation verification method for a timer according to an embodiment of the present invention;
FIG. 7 is a flowchart illustrating a simulation verification method for a timer according to another embodiment of the present invention;
FIG. 8 is a flowchart illustrating a simulation verification method for a timer according to another embodiment of the present invention;
FIG. 9 is a flow chart of a method for simulation verification of a timer performed by an assertion verification component according to an embodiment of the present invention;
FIG. 10 is a flow chart of yet another method for simulation verification of a timer performed by an assertion verification component according to an embodiment of the present invention;
FIG. 11 is a flowchart of yet another method for performing simulation verification of a timer by an assertion verification component according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1 is a schematic structural diagram of a simulation verification apparatus for a timer according to an embodiment of the present invention, where the simulation verification apparatus for a timer is implemented in a software manner, where a timer module may be implemented in a hardware description language, such as VHD L language and verilog language, as shown in fig. 1, the timer module 10 is used to simulate a real timer and has the same behavior as the real timer, and the simulation verification apparatus 20 is used to check correctness of the timer module 10.
As shown in FIG. 1, the timer module 10 includes a plurality of input capture channels 110, a plurality of output generation channels 120 and a register submodule 130.
Among them, the register submodule 130 includes: a plurality of first registers 111 provided corresponding to the respective input capture channels 110, and a plurality of second registers 121 provided corresponding to the respective output generation channels 120.
Any input capture channel 110 includes a plurality of first workers 112, the plurality of first workers 112 perform data transmission according to a first preset connection mode, and determine an operation mode of the first worker 112 according to data of a first register 111 corresponding to the first worker 112 to implement a preset input capture function, that is, if a captured input excitation signal is a preset input excitation signal, a first excitation or a first interrupt is finally output. The preset input excitation signal may be a pulse signal with a preset pulse width, and the duration of the preset pulse width may be an integral multiple of the period of the clock signal.
Any output generation channel 120 includes a plurality of second workers 122, the plurality of second workers 122 perform data transmission according to a second preset connection mode, and determine an operation mode of the second workers 122 according to data of a second register 121 corresponding to the second workers 122, so as to implement a preset output generation function, that is, finally output a second excitation or a second interrupt according to the data of the second register.
It should be noted that the main functions of the timer are input capture and output generation. The input capture is to acquire an external data signal (i.e. external excitation) according to the configuration of the first register, measure the external data signal, and further generate excitation or interruption. Output generation i.e. generating various controllable output signals, such as activation or interruption, depending on the configuration of the second register. The number of the input capturing channels and the number of the output generating channels are not limited in the embodiments of the present invention, and may be one or more. The signal output end of the previous first working device is connected with the signal input end of the next first working device between the adjacent connected first working devices; and between the adjacent second working devices, the signal output end of the previous second working device is connected with the signal input end of the next second working device. Wherein, part of the first working devices further comprise a clock input end for inputting a clock signal. Part of the second operator further comprises a clock input for inputting a clock signal.
Optionally, the first working device includes at least one of: a synchronizer, an edge detector, an edge selector, a path selector, a clock divider, a first master timer, a capture register, and an input divider.
Exemplarily, as shown in fig. 2, fig. 2 is a schematic structural diagram of an input capture channel of a timer module according to an embodiment of the present invention, and for convenience of illustration, fig. 2 exemplarily shows one input capture channel. The signal input of the synchronizer 60 introduces an input stimulus signal and a clock signal to synchronize the input stimulus signal to the internal clock domain; the signal output end of the synchronizer 60 is connected with the signal input end of the filter 61, and the filter 61 is used for filtering out unwanted clutter interference; the signal output end of the filter 61 is connected with the signal input end of the edge detector 62, the signal output end of the edge detector 62 is connected with the signal input end of the edge selector 63, and the edge detector 62 is used for selecting the rising edge and the falling edge of the input excitation signal for the edge selector 63 to select; a signal output terminal of the edge selector 63 is connected to a signal input terminal of the path selector 64, and the edge selector 63 is configured to output a first signal to the path selector 64; the signal output terminal of the path selector 64 is connected to the signal input terminal of the input frequency divider 65, and corresponding signals (such as the second signal and other signals) generated by other input capture channels and/or output generation channels are selected by the path selector 64 and enter the input frequency divider 65 for frequency division processing. The signal output of divider 65 and the resulting divided signal generate a capture interrupt flag and cause capture register 66 to capture the value of main timer 67. The signal input end of the clock frequency divider 68 introduces a clock signal and performs frequency division processing; a signal output of the clock divider 68 is connected to a signal input of the first master timer 67. The capture interrupt flag and capture interrupt enable are passed through an and gate 69 to generate a capture interrupt output signal which is passed through an or gate 70 with other signals to generate the interrupt output for the entire timer block. The clock signal is the working clock of the timer module.
The synchronizer 60 includes a first flip-flop 71 and a second flip-flop 72, a first input D1 of the first flip-flop 71 is connected to a signal input of the synchronizer 60, a second input of the first flip-flop 71 is connected to a clock input of the synchronizer 60, an output Q1 of the first flip-flop 71 is connected to a first input D2 of the second flip-flop 72, a second input of the second flip-flop 72 is connected to the clock input of the synchronizer 60, and an output Q2 of the second flip-flop 72 is connected to a signal output of the synchronizer 60. The edge detector 62 comprises a third flip-flop 73, a first gate circuit 74 and a second gate circuit 75, wherein a first input D3 of the third flip-flop 73, a first input of the first gate circuit 74 and a second input of the second gate circuit 75 are all connected to a signal input of the edge detector 62, a second input of the third flip-flop 73 is connected to a clock input of the edge detector 62, a second input of the first gate circuit 74 and a first input of the second gate circuit 75 are all connected to an output Q3 of the third flip-flop 73, an output of the first gate circuit 74 is connected to a first signal output of the edge detector 62, and an output of the second gate circuit 75 is connected to a second signal output of the edge detector 62, wherein the second input of the first gate circuit 74 is an inverting input, and its input signal can be inverted and input to the first gate circuit 74, the first gate circuit 74 is configured to invert the signal input by the second input terminal, and then output the inverted signal input by the first input terminal and the inverted signal input by the second input terminal; the second gate circuit 75 has a second input terminal that is an inverting input terminal and inputs an inverted input signal, and the second gate circuit 75 is configured to invert the signal input by the second input terminal and output the inverted signal input by the first input terminal and the inverted signal input by the second input terminal.
Optionally, the second working device includes at least one of: the circuit comprises an output comparison register, a second main timer, an output comparator, an output mode controller, an output delay controller and an output polarity selector.
Exemplarily, as shown in fig. 3, fig. 3 is a schematic structural diagram of an output generation channel of a timer module according to an embodiment of the present invention, and for convenience of illustration, fig. 3 exemplarily shows a path of the output generation channel. The output compare register 76 is used for receiving configuration data of a Central Processing Unit (CPU).
And a second main timer 77, a first signal input end of which receives the starting signal and a second signal input end of which receives the zero clearing signal, and is used for starting timing or zero clearing under the condition that a preset configuration mode is met.
An output comparator 78 having a first signal input terminal connected to the signal output terminal of the sum output comparison register 76 and a second signal input terminal connected to the signal output terminal of the second master timer 77 for determining an output mode based on the value CRR of the output comparison register 76 and the value CNT of the second master timer 77, illustratively, when CNT > CCR, the first signal output terminal of the output comparator 78 outputs a high level, and the second signal output terminal and the third signal output terminal both output a low level; when the CNT is equal to CCR, the second signal output terminal of the output comparator 78 outputs a high level, and both the first signal output terminal and the third signal output terminal output a low level; when CNT < CCR, the third signal output terminal of the output comparator 78 outputs a high level, and both the first signal output terminal and the second signal output terminal output a low level.
An output mode controller 79, wherein the first signal input terminal, the second signal input terminal, and the third signal input terminal are respectively connected to the first signal output terminal, the second signal output terminal, and the third signal output terminal of the output comparator 78, and are configured to generate corresponding outputs according to input signals of the first signal input terminal, the second signal input terminal, and the third signal input terminal and an operating mode of the output mode controller 79, for example, if the operating mode of the output mode controller 79 is the first operating mode, when the first signal input terminal of the output mode controller 79 is at a high level or the second signal input terminal is at a high level, the first signal output terminal outputs a high level, and the second signal output terminal outputs a low level; when the third signal input terminal of the output mode controller 79 is at a high level, the second signal output terminal outputs a high level, and the first signal output terminal outputs a low level. If the operating mode of the output mode controller 79 is the second operating mode, when the first signal input terminal of the output mode controller 79 is at a high level or the second signal input terminal is at a high level, the first signal output terminal outputs a low level, and the second signal output terminal outputs a high level; when the third signal input terminal of the output mode controller 79 is at a high level, the second signal output terminal outputs a high level, and the first signal output terminal outputs a low level. If the operation mode of the output mode controller 79 is the third operation mode, it is the stop mode, the first signal output terminal outputs the low level, and the second signal output terminal outputs the low level.
And the first signal input end of the output delay controller 80 is connected with the first signal output end of the output mode controller 79, and the second signal input end of the output delay controller is connected with the second signal output end of the output mode controller 79, and is used for delaying the input signal of the first signal input end and outputting the delayed input signal to the first signal output end, and delaying the input signal of the second signal input end and outputting the delayed input signal to the second signal output end. The operation modes of the output delay controller 80 include: rising edge delay and/or falling edge delay.
And the output polarity selector 81 is connected with the first signal input end of the output delay controller 80, connected with the second signal output end of the output delay controller 80, and used for performing polarity action on the input signal of the first signal input end, outputting corresponding second excitation or second interruption to the first signal output end, performing polarity action on the input signal of the second signal input end, and outputting corresponding second excitation or second interruption to the second signal output end. The operation modes of the output polarity selector 81 include: polarity change or polarity invariance.
It should be noted that the first working device may have a corresponding first register or may not have a corresponding first register, and if the first working device has a corresponding first register, the number of the corresponding first register may be one or more. For example, the synchronizer has no first register corresponding thereto; the edge detector has no corresponding first register; the edge selector is provided with a first register corresponding to the edge selector and is used for determining the working mode of the edge selector according to the data of the corresponding first register, namely selecting a rising edge as a trigger signal or selecting a falling edge as the trigger signal; the channel selector has a first register corresponding thereto. The second working device may have a corresponding second register or may not have a corresponding second register, and if the second working device has a corresponding second register, the number of the corresponding second register may be one or more. The first working devices are connected with the corresponding first registers, and the second working devices are connected with the corresponding second registers.
The simulation verification apparatus 20 includes: a register configuration component 30 and a predicate verification component 40. Wherein the assertion verification component can be implemented in an assertion language.
The register configuration component 30 is configured to generate configuration data for configuring the first register 111 and the second register 121. The timer module 10 is connected to the register configuration component 30, and is configured to introduce the configuration data generated by the register configuration component 30, configure data of the first register 111 and the second register 121 according to the configuration data, and store the configuration data in the corresponding first register 111 or second register 121. The assertion verifying component 40 includes a register checking module 410, wherein the register checking module 410 includes register verifying units 411 in one-to-one correspondence with the first register 111 and the second register 121, any one of the register verifying units 411, is connected to the register configuration component 30, is connected to the corresponding first register 111 or second register 121, for generating register data based on the configuration data, may be storing the configuration data in the corresponding register verification unit 411, comparing the register data with the data of the corresponding first register 111 or second register 121, if the comparison result is the same, then it is verified that the first register 111 or the second register 121 is configured correctly, and if the comparison result is not the same, the configuration error of the first register 111 or the second register 121 is verified and the error reporting process is performed on the currently checked first register 111 or the second register 121.
It should be noted that the register configuration component generates configuration data for configuring the first register 111 and the second register 121, and the configuration data is register data actually used by the real timer. The assertion verification component can check whether the internal signal of the timer module is correct or not in real time. The assertion verification component does not really implement the trivial function of the timer module, but checks whether the method implemented by the timer itself is correct by checking the internal signals of the timer module. All signals of the assertion verification component are input signals, and normal operation of the timer module is not influenced. Assertion-based verification languages can use compact language constructs to build accurate timing expressions. The checking of functional coverage is facilitated by checking whether these expressions occur, and the coverage analysis is for a sequence of events or the entire transmission process spanning multiple timing cycles, and therefore at a higher level of abstraction than conventional coverage driven verification. Assertions can accurately describe the desired behavior of a design. Assertion verification belongs to one type of form verification, the assertion works without a special flow, and the assertion starts to work in the normal working process of a tested module. When the proper condition is captured by the assertion verification component, the checking work is started, and the checking result is generated in real time, wherein the checking result comprises information such as whether the data comparison is correct or not, whether the time sequence relation is correct or not, the number of times of assertion occurrence and the like.
According to the technical scheme of the embodiment, the configuration data for configuring the first register and the second register is generated through the register configuration component, any register verification unit in the assertion verification component generates register data according to the configuration data generated by the register configuration component, the register data is compared with the data of the first register or the second register of the corresponding timer module, if the comparison result is the same, the configuration of the first register or the second register is verified to be correct, and if the comparison result is different, the configuration of the first register or the second register is verified to be wrong, so that the correctness of the data configuration of the first register and the data configuration of the second register in the timer module are checked, the error position can be quickly located, and the debugging time is greatly shortened.
The embodiment of the invention provides a simulation verification device of a timer. Fig. 4 is a schematic structural diagram of a simulation verification apparatus for a timer according to another embodiment of the present invention, and as shown in fig. 4, on the basis of the foregoing embodiment, the simulation verification apparatus 20 further includes: a stimulus generation component 50 for generating preset stimulus data as an input stimulus signal for the input capture channel 110; assertion verification component 40 further includes: the input capture verification module 420.
The input capture verification module 420 includes: the first verifying units 421 correspond to the first workers 112 one by one, and any one of the first verifying units 421 is connected to the signal input end and the signal output end of the corresponding first worker 112, and connected to the corresponding register verifying unit 411, and is configured to determine first verifying output data according to first input data (a signal input by the signal input end) of the first worker 112 and/or corresponding register data, compare the first verifying output data with the first output data (a signal output by the signal output end) of the first worker 112, verify that the first worker 112 is correct in function if the comparison result is the same, and count first assertion times; if the comparison result is different, the functional error of the first working device 112 is verified, and the error reporting processing is performed on the currently checked first working device 112.
And determining whether the first verification unit is executed according to the first assertion times counted by the corresponding first verification unit, and further determining whether the first working device is executed. If the first assertion frequency counted by the corresponding first verification unit is zero, the first verification unit is determined not to be executed, and then the first working device is determined not to be executed, namely the function of the first working device is not covered. If the first assertion frequency counted by the corresponding first verification unit is greater than zero, the first verification unit is determined to be executed, and then the first working device is determined to be executed, namely the function of the first working device is covered.
Illustratively, with continued reference to FIG. 2, a synchronizer is used to synchronize the input stimulus signal to the clock domain, requiring data two beats later in the clock signal in order to avoid metastability. The output signal of the synchronizer must coincide with the data two beats ago from the input stimulus signal. If the synchronizer has a problem and the first output data of the synchronizer is not consistent with the data before the input excitation signal is two beats, the first verification unit corresponding to the synchronizer verifies the functional error of the synchronizer and reports an error. In addition, if the input excitation signal has no driving change, for example, the input excitation signal is always equal to 0, the first verification unit corresponding to the synchronizer will not execute, and the first assertion number counted by the corresponding first verification unit will be zero, so the coverage rate checker will report a warning that the assertion code of the first verification unit corresponding to the synchronizer is not executed (i.e., the function is not covered); and if the first assertion times counted by the corresponding first verification units are greater than zero, the function is covered. Thus, the function of collecting the functional coverage is conveniently implemented. The edge detector is used for detecting the rising edge and the falling edge of the input signal at the signal input end, and the signal output end generates a corresponding single pulse signal (corresponding to first verification output data). If the signal output end of the edge detector does not generate a corresponding single pulse signal after the rising edge of the input signal of the edge detector arrives, and the first output data of the edge detector does not output the single pulse signal at the next moment when the rising edge arrives, the first verification unit corresponding to the edge detector verifies that the function of the edge detector is wrong; if the signal output end of the edge detector generates a corresponding single pulse signal after the rising edge of the input signal of the edge detector arrives, the first verification unit corresponding to the edge detector verifies that the function of the edge detector is correct, namely the timing relation is correct. Each checking module in the assertion verification assembly checks various output data of the timer module in real time, and the whole operation process from the start to the stop of the timer module is carried out.
The technical solution of this embodiment provides yet another simulation verification apparatus for a timer, where in this embodiment, on the basis of the above embodiment, any first verification unit is connected to a signal input terminal and a signal output terminal of a corresponding first working device, and is connected to a corresponding register verification unit, and is used to determine first verification output data according to first input data of the first working device and/or corresponding register data, compare the first verification output data with the first output data of the first working device, verify that a function of the first working device is correct if a comparison result is the same, and count a first assertion number; if the comparison result is different, the function error of the first working device is verified, and the first working device which is currently checked is subjected to error reporting processing, so that the correctness of the input and output relation of the first working device of any input capture channel in the timer module is checked, the error position can be quickly positioned, the function coverage rate is conveniently collected, and the purpose of greatly shortening the debugging time is achieved.
The embodiment of the invention provides a simulation verification device of a timer. Fig. 5 is a schematic structural diagram of a simulation verification apparatus for a timer according to another embodiment of the present invention, and as shown in fig. 5, on the basis of the foregoing embodiment, the assertion verification component 40 further includes: the output generates the verification module 430.
The output generation verification module 430 includes: the second verifying units 431 are in one-to-one correspondence with the second workers 122, and any one of the second verifying units 431 is connected with the signal input end and the signal output end of the corresponding second worker 122, and connected with the corresponding register verifying unit 411, and is configured to determine second verification output data according to second input data (a signal input by the signal input end) of the second worker 122 and/or corresponding register data, compare the second verification output data with the second output data (a signal output by the signal output end) of the second worker 122, verify that the function of the second worker 122 is correct if the comparison result is the same, and count a second assertion number; if the comparison result is different, the functional error of the second working device 122 is verified, and the error reporting processing is performed on the currently checked second working device 122. It should be noted that, for convenience of illustration, fig. 5 exemplarily shows one output generation channel.
And determining whether the second verification unit is executed according to the second assertion times counted by the corresponding second verification unit, and further determining whether the second working device is executed. And if the second assertion frequency counted by the corresponding second verification unit is zero, determining that the second verification unit is not executed, and further determining that the second working device is not executed, namely the function of the second working device is not covered. And if the second assertion frequency counted by the corresponding second verification unit is greater than zero, determining that the second verification unit is executed, and further determining that the second working device is executed, namely the function of the second working device is covered.
The technical solution of this embodiment provides a further simulation verification apparatus for a timer, where in this embodiment, on the basis of the above embodiment, any one of the second verification units is connected to a signal input terminal and a signal output terminal of a corresponding second working device, and is connected to a corresponding register verification unit, and is configured to determine second verification output data according to second input data of the second working device and/or corresponding register data, compare the second verification output data with the second output data of the second working device, verify that a function of the second working device is correct if a comparison result is the same, and count a second assertion number; if the comparison result is different, the function error of the second working device is verified to check the correctness of the input and output relation of the second working device of any output generation channel in the timer module, so that the error position can be quickly positioned, the function coverage rate is conveniently collected, and the purpose of greatly shortening the debugging time is achieved.
Optionally, the assertion verification component can be generated by a script language code, so that the assertion verification component of one input capture channel or one output generation channel is convenient to generate the assertion verification component of multiple input capture channels or multiple output generation channels, and a verification environment is convenient to build quickly.
The embodiment of the invention provides a simulation verification method of a timer. Fig. 6 is a flowchart of a simulation verification method for a timer according to an embodiment of the present invention. The simulation verification method can be realized based on the simulation verification device of the timer provided by any embodiment of the invention. The simulation verification method can be applied to a simulation verification system of the timer, and the simulation verification system comprises a timer module and a simulation verification device of the timer provided by any embodiment of the invention. The simulation verification method is executed by a timer module and specifically comprises the following steps:
step 510, the timer module configures data of the first register and/or the second register according to the configuration data generated by the register configuration component.
Step 520, the timer module outputs the data of the first register and/or the second register to the register checking module.
The simulation verification method for the timer provided by the embodiment of the invention is realized based on the simulation verification device for the timer provided by any embodiment of the invention, so that the simulation verification method for the timer provided by the embodiment of the invention also has the beneficial effects described in the embodiments, and further description is omitted here.
The embodiment of the invention provides a simulation verification method of a timer. Fig. 7 is a flowchart of a simulation verification method for a timer according to another embodiment of the present invention. On the basis of the above embodiment, when the simulation verification apparatus further includes the stimulus generation component and the assertion verification component further includes the input capture verification module, the simulation verification method of the timer includes the following steps:
step 510, the timer module configures data of the first register and/or the second register according to the configuration data generated by the register configuration component.
Step 520, the timer module outputs the data of the first register and/or the second register to the register checking module.
In step 530, any first working device generates corresponding first output data according to the first input data and/or the data of the corresponding first register.
Step 540, the timer module outputs the first input data and the first output data of any first working device to the corresponding first verification unit.
The embodiment of the invention provides a simulation verification method of a timer. Fig. 8 is a flowchart of a simulation verification method for a timer according to another embodiment of the present invention. On the basis of the above embodiment, when the assertion verification component further includes the output generation verification module, the simulation verification method of the timer includes the following steps:
step 510, the timer module configures data of the first register and/or the second register according to the configuration data generated by the register configuration component.
Step 520, the timer module outputs the data of the first register and/or the second register to the register checking module.
And step 550, generating corresponding second output data by any second working device according to the data of the corresponding second register and/or the second input data.
Step 560, the timer module outputs the second input data and the second output data of any second working device to the corresponding second verification unit.
The embodiment of the invention provides a simulation verification method of a timer executed by an assertion verification component. FIG. 9 is a flowchart of a simulation verification method of a timer executed by the assertion verification component according to an embodiment of the present invention. The simulation verification method can be realized based on the simulation verification device of the timer provided by any embodiment of the invention. The simulation verification method of the timer can be applied to a simulation verification system of the timer, and the simulation verification system comprises a timer module and a simulation verification device of the timer provided by any embodiment of the invention. The simulation verification method is executed by an assertion verification component, and specifically comprises the following steps:
step 610, any register verification unit generates register data according to the configuration data of the register configuration component.
At step 620, the assertion verification component introduces data for each of the first and/or second registers of the timer module.
Step 630, any register verification unit compares the register data with the data of the corresponding first register or second register.
If the comparison results are the same, it is verified that the corresponding first register or second register is configured correctly, i.e., step 640 is performed, and if the comparison results are not the same, it is verified that the corresponding first register or second register is configured incorrectly, i.e., step 650 is performed.
And step 640, verifying that the corresponding first register or second register is configured correctly.
The simulation verification method of the timer executed by the assertion verification component according to the embodiment of the present invention is implemented based on the simulation verification apparatus of the timer according to any embodiment of the present invention, and therefore the simulation verification method executed by the assertion verification component according to the embodiment of the present invention also has the beneficial effects described in the above embodiments, and details thereof are not described herein.
The embodiment of the invention provides a simulation verification method of a timer executed by an assertion verification component. FIG. 10 is a flowchart of yet another method for performing simulation verification of a timer by an assertion verification component according to an embodiment of the present invention. On the basis of the above embodiment, when the assertion verifying component further includes the input capture verifying module, and when the simulation verifying apparatus further includes the stimulus generating component, the simulation verifying method includes the following steps:
step 610, any register verification unit generates register data according to the configuration data of the register configuration component.
At step 620, the assertion verification component introduces data for each of the first and/or second registers of the timer module.
Step 630, any register verification unit compares the register data with the data of the corresponding first register or second register.
And step 640, verifying that the corresponding first register or second register is configured correctly.
Step 660, the assertion verification component imports first input data and first output data for each first worker of the timer module.
After verifying that the first register is configured correctly, step 660 to step 700 are performed.
Step 670, any first verification unit determines first verification output data according to the corresponding first input data of the first working device and/or the corresponding register data.
Step 680, compare the first validation output data to the first output data of the first worker.
If the comparison results are the same, verifying that the function of the corresponding first working device is correct, and counting the first assertion times, namely executing step 690; if the comparison result is not the same, the corresponding first working device is verified to have a functional error, and step 700 is executed.
And 690, verifying that the function of the corresponding first working device is correct, and counting the number of times of the first assertion.
And 700, verifying the function error of the corresponding first working device.
The embodiment of the invention provides a simulation verification method of a timer executed by an assertion verification component. FIG. 11 is a flowchart of yet another method for performing simulation verification of a timer by an assertion verification component according to an embodiment of the present invention. On the basis of the above embodiment, when the assertion verification component includes the output generation verification module, the simulation verification method includes the following steps:
step 610, any register verification unit generates register data according to the configuration data of the register configuration component.
At step 620, the assertion verification component introduces data for each of the first and/or second registers of the timer module.
Step 630, any register verification unit compares the register data with the data of the corresponding first register or second register.
And step 640, verifying that the corresponding first register or second register is configured correctly.
Step 710, the assertion verification component imports second input data and second output data of each second worker of the timer module.
After all the second registers are correctly configured, steps 710 to 750 are performed.
Step 720, any second verification unit determines second verification output data according to the second input data of the corresponding second working device and/or the corresponding register data.
Step 730, comparing the second verification output data with the second output data of the second worker.
If the comparison results are the same, verifying that the function of the corresponding second working device is correct, and counting the second assertion times, namely executing step 740; if the comparison result is not the same, the corresponding second working device is verified to have a functional error, i.e., step 750 is executed.
And 740, verifying that the function of the corresponding second working device is correct, and counting the second assertion times.
And step 750, verifying the function error of the corresponding second working device.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (9)
1. A simulation verification device for a timer is characterized in that,
the timer module comprises a plurality of input capture channels, a plurality of output generation channels and a register submodule;
wherein the register submodule comprises: a plurality of first registers provided corresponding to the respective input capture channels and a plurality of second registers provided corresponding to the respective output generation channels;
any input capturing channel comprises a plurality of first workers, the first workers carry out data transmission according to a first preset connection mode, and the working mode of the first workers is determined according to data of a first register corresponding to the first workers so as to realize a preset input capturing function;
the first working device includes at least one of: a synchronizer, an edge detector, an edge selector, a path selector, a clock divider, a first master timer, a capture register, and an input divider;
any output generation channel comprises a plurality of second workers, the second workers carry out data transmission according to a second preset connection mode, and the working mode of the second workers is determined according to data of a second register corresponding to the second workers so as to realize a preset output generation function;
the second working device includes at least one of: the output comparison register, the second main timer, the output comparator, the output mode controller, the output delay controller and the output polarity selector;
the simulation verification device comprises: a register configuration component and a predicate verification component;
the register configuration component is used for generating configuration data for configuring the first register and/or the second register;
the timer module is used for configuring the data of the first register and/or the second register according to the configuration data;
the assertion verification component comprises a register checking module, wherein the register checking module comprises register verification units which are in one-to-one correspondence with the first register and/or the second register, any register verification unit is used for generating register data according to the configuration data generated by the register configuration component, comparing the register data with the data of the corresponding first register or second register, if the comparison result is the same, verifying that the configuration of the first register or the second register is correct, and if the comparison result is different, verifying that the configuration of the first register or the second register is wrong.
2. The apparatus for verifying simulation of a timepiece according to claim 1, further comprising: the excitation generation component is used for generating preset excitation data as an input excitation signal of the input capture channel;
the assertion verification component further comprises: an input capture verification module;
the input capture verification module includes: the first verification units are in one-to-one correspondence with the first workers, and any one of the first verification units is used for determining first verification output data according to first input data of the corresponding first worker and/or corresponding register data, comparing the first verification output data with the first output data of the first worker, verifying that the function of the first worker is correct if the comparison result is the same, and counting first assertion times; and if the comparison results are different, verifying that the first working device has a function error, wherein the first input data is an input signal of a signal input end of the first working device, and the first output data is an output signal of a signal output end of the first working device.
3. The apparatus for simulation verification of a timepiece according to claim 1 or 2, wherein the assertion verification component further includes: the output is generated into a verification module which,
the output generation verification module includes: the second verification units are in one-to-one correspondence with the second workers, any one of the second verification units is used for determining second verification output data according to second input data of the corresponding second worker and/or corresponding register data, comparing the second verification output data with the second output data of the second worker, if the comparison result is the same, verifying that the function of the second worker is correct, and counting second assertion times; and if the comparison results are different, verifying that the second working device has a function error, wherein the second input data is an input signal of a signal input end of the second working device, and the second output data is an output signal of a signal output end of the second working device.
4. A simulation verification method for a timepiece, which is implemented based on a simulation verification apparatus for a timepiece according to any one of claims 1 to 3, comprising:
the timer module configures the data of the first register and/or the second register according to the configuration data generated by the register configuration component;
the timer module outputs the data of the first register and/or the second register to a register checking module.
5. The method of claim 4, wherein when the apparatus further comprises a stimulus generation component and the assertion verification component further comprises an input capture verification module, the method further comprises:
any first working device generates corresponding first output data according to the first input data and/or the data of the corresponding first register;
the timer module outputs first input data and first output data of any one of the first working devices to a corresponding first verification unit.
6. The method of claim 4 or 5, wherein when the assertion verification component further comprises an output generation verification module, the method further comprises:
any second working device generates corresponding second output data according to the data of the corresponding second register and/or the second input data;
and the timer module outputs second input data and second output data of any second working device to a corresponding second verification unit.
7. A simulation verification method for a timepiece, which is implemented based on a simulation verification apparatus for a timepiece according to any one of claims 1 to 3, comprising:
any register verification unit generates register data according to the configuration data of the register configuration component;
the assertion verification component introduces data of each first register and/or second register of the timer module;
the any register verification unit compares the register data with the data of the corresponding first register or second register;
if the comparison result is the same, verifying that the first register or the second register is correctly configured;
and if the comparison results are different, verifying that the first register or the second register is configured wrongly.
8. The method of claim 7, wherein when the apparatus further comprises a stimulus generation component and the assertion verification component further comprises an input capture verification module, the method further comprises:
the assertion verification component introduces first input data and first output data of each first worker of the timer module;
any first verification unit determines first verification output data according to the first input data of the corresponding first working device and/or the corresponding register data;
comparing the first validation output data with the first output data of the first worker;
if the comparison results are the same, verifying that the function of the first working device is correct, and counting the first assertion times;
and if the comparison results are different, verifying that the function of the first working device is wrong.
9. The method for the simulation verification of a timepiece according to claim 7 or 8, wherein when the assertion verification component further includes an output generation verification module, the method for the simulation verification of a timepiece further includes:
the assertion verification component introduces second input data and second output data of each second worker of the timer module;
any second verification unit determines second verification output data according to second input data of the corresponding second working device and/or the corresponding register data;
comparing the second validation output data to second output data of the second worker;
if the comparison results are the same, verifying that the function of the second working device is correct, and counting the second assertion times;
and if the comparison results are different, verifying that the function of the second working device is wrong.
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