CN112750893A - 低导通压降的载流子存储型fs-igbt及制作方法 - Google Patents

低导通压降的载流子存储型fs-igbt及制作方法 Download PDF

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CN112750893A
CN112750893A CN202110019615.9A CN202110019615A CN112750893A CN 112750893 A CN112750893 A CN 112750893A CN 202110019615 A CN202110019615 A CN 202110019615A CN 112750893 A CN112750893 A CN 112750893A
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史志扬
张海涛
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Ziguang Tongxin Microelectronics Co Ltd
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Abstract

本发明涉及一种低导通压降的载流子存储型FS‑IGBT,在N‑型衬底上开设沟槽,在沟槽内设置屏蔽栅氧化层、屏蔽栅多晶硅、栅极氧化层与栅极导电多晶硅;在N‑型衬底的正面形成N+型载流子存储层,在N+型载流子存储层的正面形成P‑型体区,在P‑型体区的正面形成N+型发射极,在N+型发射极的正面设置绝缘介质层,在绝缘介质层的正面设置发射极金属;在N‑型衬底的背面设置N+型缓冲层,在N+型缓冲层的背面设置P+型集电极。本发明降低了导通压降,同时降低了反馈电容,改善了器件工作时的导通损耗,最终在一定程度上降低了开关损耗。

Description

低导通压降的载流子存储型FS-IGBT及制作方法
技术领域
本发明属于微电子技术领域,具体地说是一种低导通压降的载流子存储型FS-IGBT及制作方法。
背景技术
相比于MOSFET,IGBT器件的衬底的电导调制效应可以大大地降低正向导通压降,静态功率损耗较小,电压越高表现越加显著。因而,IGBT 在中高压应用中占据了很大的市场份额。IGBT主要有穿通型PT-IGBT、非穿通型NPT- IGBT和场截止型FS-IGBT三种结构,三者之间的主要差异是不同的衬底PN结结构和不同的衬底厚度。相对PT-IGBT和NPT-IGBT来讲,FS-IGBT具有最薄的厚度,其正向导通压降得到明显的下降,该结构在IGBT产品中得到了广泛的应用。随着半导体晶圆尺寸的不断提高,成本、工艺复杂、碎片率等限制了IGBT(特别是低压IGBT)性能的不断提升。
目前的IGBT器件结构如图1所示,它包括P+型集电极1、N+型缓冲层2、N-型衬底3、P-型体区5、N+型发射极6、绝缘介质层7、发射极金属8、栅极氧化层11与栅极导电多晶硅12;
在N-型衬底3的正面向下开设沟槽,在沟槽的侧面以及底面设置栅极氧化层11,在栅极氧化层11内设置栅极导电多晶硅12;在N-型衬底3的正面经过高浓度P型杂质离子注入与推结,形成P-型体区5,在P-型体区5的正面经过高浓度N型杂质离子注入与推结,形成N+型发射极6,在N+型发射极6的正面设置绝缘介质层7,在绝缘介质层7的正面设置发射极金属8,发射极金属8通过接触孔与P-型体区5以及N+型发射极6欧姆接触;在N-型衬底3的背面设置N+型缓冲层2,在N+型缓冲层2的背面设置P+型集电极1。
发明内容
本发明的目的是克服现有技术中存在的不足,提供一种能改善器件工作时的导通损耗并能最终在一定程度上降低开关损耗的低导通压降的载流子存储型IGBT及制作方法。
按照本发明提供的技术方案,所述低导通压降的载流子存储型FS-IGBT,它包括P+型集电极、N+型缓冲层、N-型衬底、N+型载流子存储层、P-型体区、N+型发射极、绝缘介质层、发射极金属、屏蔽栅氧化层、屏蔽栅多晶硅、栅极氧化层与栅极导电多晶硅;
在N-型衬底的正面向下开设沟槽,在沟槽的下段侧面以及底面设置屏蔽栅氧化层,在屏蔽栅氧化层内设置屏蔽栅多晶硅,在沟槽的上段侧面以及屏蔽栅多晶硅上设置栅极氧化层,在栅极氧化层内设置栅极导电多晶硅;
在N-型衬底的正面经过高浓度N型杂质离子注入与推结,形成N+型载流子存储层,在N+型载流子存储层的正面经过高浓度P型杂质离子注入与推结,形成P-型体区,在P-型体区的正面经过高浓度N型杂质离子注入与推结,形成N+型发射极,在N+型发射极的正面设置绝缘介质层,在绝缘介质层的正面设置发射极金属,发射极金属通过接触孔与P-型体区以及N+型发射极欧姆接触;
在N-型衬底的背面设置N+型缓冲层,在N+型缓冲层的背面设置P+型集电极。
上述低导通压降的载流子存储型FS-IGBT的制作方法包括以下步骤:
步骤一、在轻掺杂N型FZ单晶硅片形成N-型衬底的正面进行环光刻注入与环推结;
步骤二、在N-型衬底的正面经槽光刻、刻蚀,形成沟槽;
步骤三、先在沟槽的侧面以及底面生长一层二氧化硅再进行多晶硅淀积与刻蚀,形成屏蔽栅氧化层与屏蔽栅多晶硅;
步骤四、先在沟槽的侧面生长一层二氧化硅再进行多晶硅淀积与刻蚀,形成栅极氧化层与栅极导电多晶硅;
步骤五、在N-型衬底的正面经高浓度N型杂质离子注入与推结,形成N+型载流子存储层;
步骤六、在N+型载流子存储层的正面经过高浓度P型杂质离子注入与推结,形成P-型体区;
步骤七、在P-型体区的正面经过高浓度N型杂质离子注入与推结,形成N+型发射极;
步骤八、在N+型发射极的正面经淀积回流,形成绝缘介质层;
步骤九、先经接触孔光刻刻蚀,再经正面金属化淀积,最后经正面金属光刻刻蚀,形成发射极金属;
步骤十、先在N-型衬底的背面进行减薄,再进行高浓度N型杂质离子注入,形成N+型缓冲层;
步骤十一、在N+型缓冲层的背面经过高浓度P型杂质离子注入,形成P+型集电极。
本发明降低了导通压降,同时降低了反馈电容,改善了器件工作时的导通损耗,最终在一定程度上降低了开关损耗。
附图说明
图1是现有技术中常规FS-IGBT器件的结构图。
图2是本发明FS-IGBT器件的结构图。
具体实施方式
下面结合具体实施例对本发明作进一步说明。
一种低导通压降的载流子存储型FS-IGBT,它包括P+型集电极1、N+型缓冲层2、N-型衬底3、N+型载流子存储层4、P-型体区5、N+型发射极6、绝缘介质层7、发射极金属8、屏蔽栅氧化层9、屏蔽栅多晶硅10、栅极氧化层11与栅极导电多晶硅12;
在N-型衬底3的正面向下开设沟槽,在沟槽的下段侧面以及底面设置屏蔽栅氧化层9,在屏蔽栅氧化层9内设置屏蔽栅多晶硅10,在沟槽的上段侧面以及屏蔽栅多晶硅10上设置栅极氧化层11,在栅极氧化层11内设置栅极导电多晶硅12;
在N-型衬底3的正面经过高浓度N型杂质离子注入与推结,形成N+型载流子存储层4,在N+型载流子存储层4的正面经过高浓度P型杂质离子注入与推结,形成P-型体区5,在P-型体区5的正面经过高浓度N型杂质离子注入与推结,形成N+型发射极6,在N+型发射极6的正面设置绝缘介质层7,在绝缘介质层7的正面设置发射极金属8,发射极金属8通过接触孔与P+型体区5以及N+型发射极6欧姆接触;
在N-型衬底3的背面设置N+型缓冲层2,在N+型缓冲层2的背面设置P+型集电极1。
上述低导通压降的载流子存储型FS-IGBT的制作方法包括以下步骤:
步骤一、在轻掺杂N型FZ单晶硅片形成N-型衬底3的正面进行环光刻注入与环推结;
步骤二、在N-型衬底3的正面经槽光刻、刻蚀,形成沟槽;
步骤三、先在沟槽的侧面以及底面生长一层二氧化硅再进行多晶硅淀积与刻蚀,形成屏蔽栅氧化层9与屏蔽栅多晶硅10;
步骤四、先在沟槽的侧面生长一层二氧化硅再进行多晶硅淀积与刻蚀,形成栅极氧化层11与栅极导电多晶硅12;
步骤五、在N-型衬底3的正面经高浓度N型杂质离子注入与推结,形成N+型载流子存储层4;
步骤六、在N+型载流子存储层4的正面经过高浓度P型杂质离子注入与推结,形成P-型体区5;
步骤七、在P-型体区5的正面经过高浓度N型杂质离子注入与推结,形成N+型发射极6;
步骤八、在N+型发射极6的正面经淀积回流,形成绝缘介质层7;
步骤九、先经接触孔光刻刻蚀,再经正面金属化淀积,最后经正面金属光刻刻蚀,形成发射极金属8;
步骤十、先在N-型衬底3的背面进行减薄,再进行高浓度N型杂质离子注入,形成N+型缓冲层2;
步骤十一、在N+型缓冲层2的背面经过高浓度P型杂质离子注入,形成P+型集电极1。
本发明在常规FS-IGBT器件的结构基础上,增加了N+型载流子存储层4,由于N+型载流子存储层4的载流子浓度高于N-型衬底3的载流子浓度。N+型载流子存储层4与P-型体区5的电位差大于没有N+型载流子存储层4的N-型衬底3与P-型体区5之间的电位差。N+型载流子存储层4增加的电势存储了P-型体区5送来的空穴,增加了载流子密度。
在屏蔽栅氧化层9和屏蔽栅多晶硅10的底部形成积累,导致N+型发射极6的电子注入增强,进一步降低了导通压降Vce(on)。在沟槽光刻刻蚀后先进行一次屏蔽栅氧化层9与屏蔽栅多晶硅10淀积,屏蔽栅多晶硅10刻蚀后再进行一次栅极氧化层11与栅极导电多晶硅12淀积。沟槽底部的屏蔽栅氧化层9和屏蔽栅多晶硅10的存在间接增加了隔离层的厚度,从而导致反馈电容Crss减小。因此适当调整屏蔽栅多晶硅10的刻蚀厚度、保证阈值电压Vth、集电极-发射极击穿电压BV不变的情况下,本发明可以进一步降低沟槽型FS-IGBT器件的导通压降Vce(on),同时一定程度上减小了反馈电容Crss,改善了器件工作时的导通损耗,最终在一定程度上降低了器件的开关损耗。
本发明在常规FS-IGBT器件的结构基础上,由于增加了N+型载流子存储层4,进一步优化了器件在导通状态下体内少数载流子的分布,进一步增强了电导调制效应、降低了器件正向导通压降,同时降低了反馈电容Crss,从而提高了FS-IGBT的整体性能。

Claims (2)

1.一种低导通压降的载流子存储型FS-IGBT,其特征是:它包括P+型集电极(1)、N+型缓冲层(2)、N-型衬底(3)、N+型载流子存储层(4)、P-型体区(5)、N+型发射极(6)、绝缘介质层(7)、发射极金属(8)、屏蔽栅氧化层(9)、屏蔽栅多晶硅(10)、栅极氧化层(11)与栅极导电多晶硅(12);
在N-型衬底(3)的正面向下开设沟槽,在沟槽的下段侧面以及底面设置屏蔽栅氧化层(9),在屏蔽栅氧化层(9)内设置屏蔽栅多晶硅(10),在沟槽的上段侧面以及屏蔽栅多晶硅(10)上设置栅极氧化层(11),在栅极氧化层(11)内设置栅极导电多晶硅(12);
在N-型衬底(3)的正面经过高浓度N型杂质离子注入与推结,形成N型+载流子存储层(4),在N+型载流子存储层(4)的正面经过高浓度P型杂质离子注入与推结,形成P-型体区(5),在P-型体区(5)的正面经过高浓度N型杂质离子注入与推结,形成N+型发射极(6),在N+型发射极(6)的正面设置绝缘介质层(7),在绝缘介质层(7)的正面设置发射极金属(8),发射极金属(8)通过接触孔与P-型体区(5)以及N+型发射极(6)欧姆接触;
在N-型衬底(3)的背面设置N+型缓冲层(2),在N+型缓冲层(2)的背面设置P+型集电极(1)。
2.一种低导通压降的载流子存储型FS-IGBT的制作方法包括以下步骤:
步骤一、在轻掺杂N型FZ单晶硅片形成的N-型衬底(3)的正面进行环光刻注入与环推结;
步骤二、在N-型衬底(3)的正面经槽光刻、刻蚀,形成沟槽;
步骤三、先在沟槽的侧面以及底面生长一层二氧化硅再进行多晶硅淀积与刻蚀,形成屏蔽栅氧化层(9)与屏蔽栅多晶硅(10);
步骤四、先在沟槽的侧面生长一层二氧化硅再进行多晶硅淀积与刻蚀,形成栅极氧化层(11)与栅极导电多晶硅(12);
步骤五、在N-型衬底(3)的正面经高浓度N型杂质离子注入与推结,形成N+型载流子存储层(4);
步骤六、在N+型载流子存储层(4)的正面经过高浓度P型杂质离子注入与推结,形成P-型体区(5);
步骤七、在P-型体区(5)的正面经过高浓度N型杂质离子注入与推结,形成N+型发射极(6);
步骤八、在N+型发射极(6)的正面经淀积回流,形成绝缘介质层(7);
步骤九、先经接触孔光刻刻蚀,再经正面金属化淀积,最后经正面金属光刻刻蚀,形成发射极金属(8);
步骤十、先在N-型衬底(3)的背面进行减薄,再进行高浓度N型杂质离子注入,形成N+型缓冲层(2);
步骤十一、在N+型缓冲层(2)的背面经过高浓度P型杂质离子注入,形成P+型集电极(1)。
CN202110019615.9A 2021-01-07 2021-01-07 低导通压降的载流子存储型fs-igbt及制作方法 Pending CN112750893A (zh)

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