CN112736032A - 用于不具有钛衬垫的mol互连的装置 - Google Patents

用于不具有钛衬垫的mol互连的装置 Download PDF

Info

Publication number
CN112736032A
CN112736032A CN202110096317.XA CN202110096317A CN112736032A CN 112736032 A CN112736032 A CN 112736032A CN 202110096317 A CN202110096317 A CN 202110096317A CN 112736032 A CN112736032 A CN 112736032A
Authority
CN
China
Prior art keywords
metal element
semiconductor device
oxide layer
semiconductor substrate
tungsten
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202110096317.XA
Other languages
English (en)
Other versions
CN112736032B (zh
Inventor
V·卡米内尼
M·V·雷蒙德
P·阿迪休米尔利
牛成玉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
GlobalFoundries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GlobalFoundries Inc filed Critical GlobalFoundries Inc
Priority to CN202110096317.XA priority Critical patent/CN112736032B/zh
Publication of CN112736032A publication Critical patent/CN112736032A/zh
Application granted granted Critical
Publication of CN112736032B publication Critical patent/CN112736032B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

本发明涉及用于不具有钛衬垫的MOL互连的装置。揭示了数种方法、设备及系统用于制造半导体装置，其包含半导体基板；在该半导体基板上方的氧化物层；设置于该氧化物层内的含钨的第一金属组件；在该氧化物层上方的层间电介质(ILD)，其中，该层间电介质包含沟槽，以及该沟槽的底部包含该第一金属组件的顶部的至少一部分；设置于该沟槽的侧壁及底部上的阻障材料；以及设置于该沟槽中的第二金属组件。

Description

用于不具有钛衬垫的MOL互连的装置
本申请是申请号为201611020045.0、申请日为2016年11月18日、发明名称为“用于不具有钛衬垫的MOL互连的方法及系统”的中国专利申请的分案申请。
技术领域
本发明内容大体有关于精密半导体装置的制造，且更特别的是，有关于用于在半导体装置中制备不具有钛衬垫的MOL互连的各种方法、结构及系统。
背景技术
半导体装置的制造需要许多离散的制程步骤以便从半导体原料生产出已封装好的半导体装置。从初始成长半导体材料、把半导体晶体切成个别的晶圆、经过数种制造阶段(蚀刻、掺杂、离子植入、或其类似者)、一直到已完成装置的封装与最终测试，有各种不同的专用制程，以致于该等制程要在各有不同控制方案的不同制造场所中执行。
一般而言，使用半导体制造工具，例如曝光工具或步进器(stepper)，对一群(有时被称为一批)的半导体晶圆执行一组加工步骤。例如，可对半导体晶圆执行蚀刻制程以形塑半导体晶圆上的物件，例如各自用作晶体管的栅极的多晶硅线路。作为另一实施例，可形成用作使半导体晶圆上的传导区互相连接的传导线路的多条金属线路，例如，铝或铜。以此方式，可制成集成电路芯片。
用于制造当今半导体装置的已知技术是于第一金属组件上设置元素钛层。如图1(现有技术)所示，在沉积阻障材料162及第二金属组件160于钛层上时，该钛层经受会形成氧化钛152的吸氧作用(oxygen gettering)。
可惜，第一金属组件150与第二金属组件160之间存在氧化钛152产生许多不合意结果。其一是，氧化钛152增加第一金属组件150/氧化钛152/第二金属组件160结构的接触电阻。另一是，钛的吸氧作用由于钛金属悬空而导致第二金属组件160中形成空隙166。这两个结果损及半导体装置100的效能。
因此，亟须一种方法用于形成包含第一金属组件及第二金属组件的半导体装置，相对于如图1所示的现有技术装置，它有较低的电阻及减少的空隙形成物。
本发明内容可应付及/或至少减少与上述一或多个现有技术问题及/或提供以上所列的一或多个合意特征。
发明内容
为供基本理解本发明的一些方面，提出以下简化的总结。此总结并非本发明的穷举式总览。它不是想要识别本发明的关键或重要元件或者是描绘本发明的范畴。唯一的目的是要以简要的形式提出一些概念作为以下更详细的说明的前言。
大体上，本发明内容针对一种半导体装置，其包含半导体基板；在该半导体基板上方的氧化物层；设置于该氧化物层内的含钨的第一金属组件；在该氧化物层上方的层间电介质(ILD)，其中，该层间电介质包含沟槽，以及该沟槽的底部包含该第一金属组件的顶部(top)的至少一部分；设置于该沟槽的侧壁及底部上的阻障材料；以及设置于该沟槽中的第二金属组件。本发明内容也针对用于制造此一半导体装置的各种方法、设备及系统。
附图说明
参考以下结合附图的说明可明白本发明内容，其中类似的元件是以相同的附图标记表示。
图1的非写实横截面图图示现有技术所熟知的半导体装置；
图2A的非写实横截面图根据本文具体实施例图示第一加工阶段之后的半导体装置；
图2B的非写实横截面图根据本文具体实施例图示第二加工阶段之后的图2A的半导体装置；
图2C的非写实横截面图根据本文具体实施例图示第三加工阶段之后的图2A至图2B的半导体装置；
图2D的非写实横截面图根据本文具体实施例图示第四加工阶段之后的图2A至图2C的半导体装置；
图2E的非写实横截面图根据本文具体实施例图示第五加工阶段之后的图2A至图2D的半导体装置；
图3A的非写实横截面图根据本文具体实施例图示第一加工阶段之后的半导体装置；
图3B的非写实横截面图根据本文具体实施例图示第二加工阶段之后的图3A的半导体装置；
图3C的非写实横截面图根据本文具体实施例图示第三加工阶段之后的图3A至图3B的半导体装置；
图3D的非写实横截面图根据本文具体实施例图示第四加工阶段之后的图3A至图3C的半导体装置；
图3E的非写实横截面图根据本文具体实施例图示第五加工阶段之后的图3A至图3D的半导体装置；
图4的非写实横截面图根据本文具体实施例图示半导体装置；
图5根据本文具体实施例图示用于制造装置的半导体装置制造系统；以及
图6图示一种根据本文具体实施例的方法的流程图。
尽管本发明容易做成各种修改及替代形式，本文仍以附图为例图示几个本发明的特定具体实施例且详述其中的细节。不过，应了解本文所描述的特定具体实施例不是想要把本发明限定成本文所揭示的特定形式，反而是，本发明是要涵盖落在如随附权利要求书所界定的本发明精神及范畴内的所有修改、等价及替代性陈述。
附图标记说明：
100 半导体装置
150 第一金属组件、结构
152 氧化钛、结构
160 第二金属组件、金属组件、结构
162 阻障材料、结构
166 空隙
200 半导体装置、物品
210 半导体基板、基板
220 氧化物层
230 ILD
232 沟槽
240 栅极
242 钨层
244 WFM
246 高K材料
248 氮化物层
250 第一金属组件、第一接触
252 源极/漏极结构
254 硅化物区
256 磊晶硅区
258 电阻性钨基材料
260 第二金属组件
264 阻障材料
300 半导体装置
310 半导体基板、基板
320 氧化物层
330 ILD
332 沟槽
340 栅极
342 钨层
344 WFM
346 高K材料
348 氮化物层
358 电阻性钨基材料
360 第二金属组件
364 阻障材料
400 半导体装置
410 半导体基板
430 ILD
440 栅极
442 钨层
444 WFM
446 高K材料
448 氮化物层
450 第一金属组件、结构
452 源极/漏极结构
454 硅化物区
456 磊晶硅区
460 第二金属组件、结构
462 阻障材料、结构
500 系统
510 半导体装置制造系统
520 制程控制器
550 运送机构
600 方法
610 步骤
620 步骤
630 步骤
640 步骤
650 步骤
660 步骤。
具体实施方式
以下描述本发明的各种示意具体实施例。为了清楚说明，本发明说明书没有描述实际具体实作的所有特征。当然，应了解，在开发任一此类的实际具体实施例时，必需做许多与具体实作有关的决策以达成开发人员的特定目标，例如遵循与系统相关及商务有关的限制，这些都会随着每一个具体实作而有所不同。此外，应了解，此类开发即复杂又花时间，决不是本领域技术人员在阅读本发明内容后即可实作的例行工作。
此时以参照附图来描述本发明。示意图示于附图的各种结构、系统及装置仅供解释以及避免本领域技术人员所熟知的细节混淆本发明。尽管如此，仍纳入附图用来描述及解释本发明内容的示意实施例。应使用与本领域技术人员所熟悉的意思一致的方式理解及解释用于本文的字汇及片语。本文没有特别定义的术语或片语(也就是，与本领域技术人员所理解的普通惯用意思不同的定义)是想要用术语或片语的一致用法来暗示。在这个意义上，希望术语或片语具有特定的意思时(也就是，不同于本领域技术人员所理解的意思)，则会在本专利说明书中以直接明白地提供特定定义的方式清楚地陈述用于该术语或片语的特定定义。
本文的具体实施例提供经制作成在第一、第二金属组件之间不具有钛层的半导体装置。相对于经制作成在第一、第二金属组件之间具有钛层的现有技术半导体装置，此类装置有较低的电阻与减少的空隙。
根据本文具体实施例的半导体装置可包含半导体基板；在该半导体基板上方的氧化物层；设置于该氧化物层内的含钨的第一金属组件；在该氧化物层上方的层间电介质(ILD)，其中该ILD包含沟槽，以及该沟槽的底部包含该第一金属组件的顶部的至少一部分；设置于该沟槽的侧壁及底部上的阻障材料；以及设置于该沟槽中的第二金属组件。
该半导体基板可包含本领域技术人员熟知在半导体装置中有利于用作半导体基板的任何材料。在一具体实施例中，该半导体基板可包含硅、硅-锗、或绝缘体上覆硅(SOI)，其他本领域所熟知者。该半导体基板可用本领域技术人员所熟知的任何技术制成。
该氧化物层可包含本领域技术人员熟知在半导体装置中有利于用作氧化物层的任何材料。在一具体实施例中，该氧化物层可包含氧化硅。该氧化物层可用本领域技术人员所熟知的任何技术制成。
该第一金属组件可为半导体装置内的任何传导组件。在一具体实施例中，该第一金属组件可为半导体装置的晶体管的栅极结构的组件，例如此一栅极的最上面组件。在一具体实施例中，该栅极可形成于该半导体基板上。在一具体实施例中，该第一金属组件可为接触，例如半导体装置的晶体管的源极/漏极区的接触，例如紧邻栅极地设置于半导体基板中的源极/漏极区。该第一金属组件可包含本领域技术人员熟知的有传导性的任何材料。在一具体实施例中，该第一金属组件可包含钨。该第一金属组件，以及第一金属组件为组件时其中的晶体管或其他结构，可用本领域技术人员所熟知的任何技术制成。
该ILD可包含本领域技术人员熟知在半导体装置中有利于用作层间电介质的任何材料。在一具体实施例中，该ILD可包含氮化硅。该ILD可用本领域技术人员所熟知的任何技术(例如，原子层沉积(ALD)、化学气相沉积(CVD)、物理气相沉积(PVD)等等)制成。此外，该ILD内的沟槽可用本领域技术人员所熟知的任何技术制成。若需要，该沟槽也可伸入该氧化物层。不论该沟槽如何形成，该沟槽的底部包含该第一金属组件的顶部的至少一部分。
设置于沟槽的侧壁及底部上的阻障材料可包含本领域技术人员熟知在半导体装置中有利于用作阻障材料的任何材料。在一具体实施例中，除了其他本领域熟知的阻障材料之外，该阻障材料还可包含氮化钨、氮化钛、碳化钨或氮化钽。可用本领域技术人员所熟知的任何技术(ALD，CVD、等等)沉积该阻障材料于该沟槽的侧壁及底部上。
类似第一金属组件，该第二金属组件可为半导体装置内的任何传导组件。在一具体实施例中，该第二金属组件可为接触，例如垂直穿过ILD的通孔。该第二金属组件可包含本领域技术人员熟知有传导性的任何材料。该第二金属组件可用本领域技术人员所熟知的任何技术制成。
在一具体实施例中，该半导体装置可包含在半导体基板上及氧化物层下的氮化物层。在半导体装置包含栅极的具体实施例中，该氮化物层也可设置于栅极上。该氮化物层可包含本领域技术人员熟知在半导体装置中有利于用作氮化物层的任何材料。在一具体实施例中，该氮化物层可包含硅及氮。该氮化物层可用本领域技术人员所熟知的任何技术制成。
图2A至图2E图示根据本文具体实施例的半导体装置的形成。翻到提供半导体装置200的非写实图画(stylized depiction)的图2A，其包含半导体基板210、氧化物层220及ILD 230。半导体装置200也包含含有钨层242、WFM 244及高K材料246的栅极240。紧邻栅极240的是含有磊晶(epitaxy)硅区256及硅化物区254的源极/漏极结构252。设置于源极/漏极结构252上的是含有钨的第一金属组件250。氮化物层248设置于栅极240及基板210上面。
图2B为半导体装置200在执行反应性离子蚀刻(RIE)之后的非写实图画。(为求简洁，省略光学微影、图案化及遮罩ILD 230的例行步骤)。该RIE在ILD 230中形成沟槽232以及与第一金属组件250的最上面部分的钨相互作用以形成电阻性钨基材料258。电阻性钨基材料258在第一接触250暴露于空气后立即形成，由此钨与空气中的氧反应而形成钨氧化物(WOx)。通过钨与可包含氧基、氮基、氟基及碳基气体中之一或更多的RIE化学的相互作用，更多Wox及其他电阻性钨化合物可形成于电阻性钨基材料258中。此外，在RIE之后，如果装置在后续加工步骤之前暴露于空气或其他含氧气氛，可形成更多钨氧化物及其他电阻性钨化合物，它可包含钨与碳、氟等的化合物。
图2C为半导体装置200在执行化学蚀刻之后的非写实图画。该化学蚀刻对于ILD230有选择性且移除至少一些电阻性钨基材料258，从而暴露第一金属组件250。在一具体实施例中，该化学蚀刻包含三氟化氮等离子(NF3 plasma)。
图2D为半导体装置200在原位化学蚀刻后已沉积阻障材料264于沟槽232的侧壁及底部后的非写实图画。在化学蚀刻与阻障沉积之间最好不允许空气泄露；换言之，沉积阻障材料的执行最好使得在执行对于该ILD有选择性的该化学蚀刻步骤之后，空气或含氧气氛不会接触该第一金属组件的该正面(top surface)。阻障材料264与第一金属组件250接触。
图2E为半导体装置200在第二金属组件260已沉积于沟槽232中之后的非写实图画。若需要，第二金属组件260可经受相对于ILD 230的顶部的平坦化。相对于图1现有技术半导体装置100的金属组件160，第二金属组件260大体没有空隙。
图3A至图3E图示根据本文具体实施例的另一半导体装置的形成。翻到提供半导体装置300的非写实图画的图3A，其包含半导体基板310、氧化物层320及ILD 330。半导体装置300也包含含有钨层342、WFM 344及高K材料346的栅极340。半导体装置300也可包含紧邻栅极340的源极/漏极结构(为求简洁而省略)。氮化物层348设置于栅极340及基板310上面。
图3B为半导体装置300在执行反应性离子蚀刻(RIE)之后的非写实图画。该RIE在ILD 330、氧化物层320及氮化物层348中形成沟槽332，以及与钨层342的最上面部分的钨相互作用以形成电阻性钨基材料358。电阻性钨基材料358的形成机制与常在电阻性钨基材料358中发现的钨化合物类型是如同以上在图2A至图2E背景下说明电阻性钨基材料258时所述者。
图3C为半导体装置300在执行化学蚀刻之后的非写实图画。该化学蚀刻对于ILD330、氧化物层320及氮化物层348有选择性且移除至少一些电阻性钨基材料358，从而暴露钨层342。在一具体实施例中，该化学蚀刻包含三氟化氮等离子。
图3D为半导体装置300在阻障材料364已沉积于沟槽332的侧壁及底部上之后的非写实图画。在化学蚀刻与阻障沉积之间最好不允许空气泄露。阻障材料364与钨层342接触。
图3E为半导体装置300在第二金属组件360已沉积于沟槽332中且经由化学机械平坦化研磨之后的非写实图画。相对于图1所示的现有技术半导体装置100的金属组件160，第二金属组件360大体没有空隙。
图4为根据本文具体实施例的半导体装置400的非写实图画。半导体装置400包含半导体基板410、氧化物层420、氮化物层448、以及ILD 430。半导体装置400也包含含有钨层442、WFM 444及高K材料446的栅极440。紧邻栅极440的是包含磊晶硅区456及硅化物区454的源极/漏极结构452。设置于源极/漏极结构452上的是含有钨的第一金属组件450。设置于ILD 430内的是阻障材料462与第二金属组件460。相对于图1所示的现有技术半导体装置100的金属组件160，第二金属组件460没有空隙。再者，在7纳米制程中，通过结构450、462及460的电阻比通过图1所示的现有技术半导体装置的结构150、152、162及160的电阻小约10％。
此时翻到图5的非写实图画，其根据本文具体实施例图示用于制造半导体装置100的系统。图5的系统500可包含半导体装置制造系统510与制程控制器(processcontroller)520。该半导体装置制造系统510可基于由制程控制器520提供的一或更多指令集来制造半导体装置。在一具体实施例中，其中该指令集可包含数个指令以：提供装置堆叠，其包含半导体基板；在该半导体基板上方的氧化物层；在该氧化物层上方的层间电介质(ILD)；设置于该氧化物层内的含钨的第一金属组件；执行反应性离子蚀刻以在至少该ILD中形成至少一沟槽，由此将该第一金属组件的正面的至少一部分转换成电阻性钨基材料；执行对于该ILD有选择性的化学蚀刻以移除该电阻性钨基材料的至少一部分以及暴露该第一金属组件的该正面的至少一部分；沉积阻障材料于该沟槽的侧壁及底部上；以及沉积第二金属于该沟槽中。
该装置堆叠更可包含：在该半导体基板上的栅极以及紧邻该栅极而设置于该半导体基板中的源极/漏极区，以及该第一金属组件在该源极/漏极区上。替换地或另外，该装置堆叠更可包含：在该半导体基板上的栅极，其中该第一金属组件为该栅极的最上面金属层。在任何具体实施例中，该装置堆叠更可包含：在该半导体基板上、在该氧化物层下、以及在该栅极(若有的话)上的氮化物层。
在一具体实施例中，半导体装置制造系统510可经组配成通过执行等离子三氟化氮蚀刻来完成该化学蚀刻。半导体装置制造系统510也可经组配成可平坦化该第二金属。
半导体装置制造系统510可包含各种加工站，例如蚀刻加工站、微影加工站、CMP加工站等等。可用制程控制器520控制由半导体装置制造系统510执行的一或多个该等加工步骤。制程控制器520可为含有一或更多软体产品的工作站电脑、桌上电脑、膝上电脑、平板电脑、或任何其他类型的运算装置，该一或更多软体产品能够控制制程、接收制程反馈、接收测试结果数据、执行学习循环调整、执行制程调整等等。
半导体装置制造系统510可在媒体(例如，硅晶圆)上产生半导体装置200(例如，集成电路)。半导体装置制造系统510可提供在运送机构550上的已加工半导体装置200，例如输送带系统。在一些具体实施例中，该输送带系统可为能够运送半导体晶圆的精密无尘室运送系统。在一具体实施例中，半导体装置制造系统510可包含多个加工步骤，例如，第一制程步骤、第二制程步骤等等。
在一些具体实施例中，标示“200”的物品可为个别晶圆，而在其他具体实施例中，物品200可为一群半导体晶圆，例如，一“批”半导体晶圆。半导体装置200可包含晶体管、电容器、电阻器、记忆格、处理器及/或类似者中之一或更多。在一具体实施例中，半导体装置200包含中段制程(MOL)堆叠。
系统500能够制造涉及各种技术的各种产品。例如，系统500可生产CMOS技术、Flash技术、BiCMOS技术、电源装置、记忆体装置(例如，DRAM装置)、NAND记忆体装置、及/或各种其他半导体技术的装置。
翻到根据本文具体实施例图示方法600的流程图的图6。方法600包括：在步骤610，提供装置堆叠，其包含半导体基板；在该半导体基板上方的氧化物层；在该氧化物层上方的层间电介质(ILD)；以及设置于该氧化物层内的含钨的第一金属组件。
在一具体实施例中，该装置堆叠更包含在该半导体基板上的栅极以及紧邻该栅极而设置于该半导体基板中的源极/漏极区，以及该第一金属组件在该源极/漏极区上。该装置堆叠更可包含：在该半导体基板上、在该栅极上和在该氧化物层下的氮化物层。
在一具体实施例中，该装置堆叠更包含在该半导体基板上的栅极，以及该第一金属组件为该栅极的最上面金属层。该装置堆叠更可包含：更包含在该半导体基板上、在该栅极上和在该氧化物层下的氮化物层。
方法600也包含：在步骤620，执行反应性离子蚀刻以在至少该ILD中形成至少一沟槽，由此将该第一金属组件的正面的至少一部分转换成电阻性钨基材料。方法600也包含：在步骤630，执行对于该ILD有选择性的化学蚀刻以移除该电阻性钨基材料的至少一部分以及暴露该第一金属组件的该正面的至少一部分。在一具体实施例中，该化学蚀刻包含等离子三氟化氮蚀刻。
方法600也包含：在步骤640，沉积阻障材料于该沟槽的侧壁及底部上。方法600也包含：在步骤650，沉积第二金属于该沟槽中。
在一具体实施例中，方法600更可包含：在步骤660，平坦化该第二金属。
上述方法可用非暂态电脑可读取储存媒体中所储存以及由例如由运算装置的处理器执行的指令来加以管制。描述本文的每个操作可对应至非暂态电脑记忆体或电脑可读取储存媒体中所储存的指令。在各种具体实施例中，该非暂态电脑可读取储存媒体包括磁性或光碟储存装置，固态储存装置，例如快闪记忆体、或其他非挥发性记忆体装置或数个装置。储存在非暂态电脑可读取储存媒体上的电脑可读指令可为源码、组合语言码、目的码、或可由一或更多处理器解释及/或执行的其他指令格式。
以上所揭示的特定具体实施例均仅供图解说明，因为本领域技术人员在受益于本文的教导后显然可以不同但等价的方式来修改及实施本发明。例如，可用不同的顺序完成以上所提出的制程步骤。此外，除非在权利要求书有提及，不希望本发明受限于本文所示的构造或设计的细节。因此，显然可改变或修改以上所揭示的特定具体实施例而所有此类变体都被认为仍然是在本发明的范畴与精神内。因此，本文提出随附的权利要求书寻求保护。

Claims (7)

1.一种半导体装置，包含：
半导体基板；
氧化物层，在该半导体基板上方；
第一金属组件，包含钨，设置于该氧化物层内，其中，该第一金属组件的顶部的至少一部分没有电阻性钨基材料；
在该半导体基板上的栅极以及紧邻该栅极而设置于该半导体基板中的源极/漏极区，其中，该第一金属组件在该源极/漏极区上；
层间电介质(ILD)，在该氧化物层上方，其中，该层间电介质包含沟槽，以及该沟槽的底部包含该第一金属组件的该顶部的至少该部分；
阻障材料，沉积于该沟槽的侧壁及该底部上；
第二金属组件，设置于该沟槽中；以及
电阻性钨基材料，在该第一金属组件上，并且邻接该阻障材料和该氧化物层。
2.根据权利要求1所述的半导体装置，更包含在该半导体基板上、在该栅极上和在该氧化物层下的氮化物层。
3.根据权利要求1所述的半导体装置，更包含在该半导体基板上的栅极，其中，该第一金属组件为该栅极的最上面金属层。
4.一种半导体装置，包含：
半导体基板；
氧化物层，在该半导体基板上方；
栅极，在该半导体基板上；
源极/漏极区，紧邻该栅极而设置于该半导体基板中；
第一金属组件，包含钨，设置于该氧化物层内以及该源极/漏极区上，其中，该第一金属组件的顶部的至少一部分没有电阻性钨基材料；
层间电介质(ILD)，在该氧化物层上方，其中，该层间电介质包含沟槽，以及该沟槽的底部包含该第一金属组件的该顶部的至少一部分；
阻障材料，设置于该沟槽的侧壁及该底部上；
第二金属组件，设置于该沟槽中；以及
电阻性钨基材料，在该第一金属组件上，并且邻接该阻障材料和该氧化物层。
5.根据权利要求4所述的半导体装置，更包含在该半导体基板上、在该栅极上和在该氧化物层下的氮化物层。
6.根据权利要求4所述的半导体装置，更包含在该第一金属组件上并且邻接该阻障材料和该氧化物层的电阻性钨基材料。
7.根据权利要求4所述的半导体装置，更包含设置在该源极/漏极区与该第一金属组件之间的硅化物区。
CN202110096317.XA 2015-11-20 2016-11-18 用于不具有钛衬垫的mol互连的装置 Active CN112736032B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110096317.XA CN112736032B (zh) 2015-11-20 2016-11-18 用于不具有钛衬垫的mol互连的装置

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US14/948,214 US9679807B1 (en) 2015-11-20 2015-11-20 Method, apparatus, and system for MOL interconnects without titanium liner
US14/948,214 2015-11-20
CN201611020045.0A CN107046000B (zh) 2015-11-20 2016-11-18 用于不具有钛衬垫的mol互连的方法及系统
CN202110096317.XA CN112736032B (zh) 2015-11-20 2016-11-18 用于不具有钛衬垫的mol互连的装置

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN201611020045.0A Division CN107046000B (zh) 2015-11-20 2016-11-18 用于不具有钛衬垫的mol互连的方法及系统

Publications (2)

Publication Number Publication Date
CN112736032A true CN112736032A (zh) 2021-04-30
CN112736032B CN112736032B (zh) 2024-05-24

Family

ID=58693908

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201611020045.0A Active CN107046000B (zh) 2015-11-20 2016-11-18 用于不具有钛衬垫的mol互连的方法及系统
CN202110096317.XA Active CN112736032B (zh) 2015-11-20 2016-11-18 用于不具有钛衬垫的mol互连的装置

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201611020045.0A Active CN107046000B (zh) 2015-11-20 2016-11-18 用于不具有钛衬垫的mol互连的方法及系统

Country Status (4)

Country Link
US (2) US9679807B1 (zh)
CN (2) CN107046000B (zh)
DE (1) DE102016222390A1 (zh)
TW (1) TWI590382B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10153351B2 (en) 2016-01-29 2018-12-11 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and a method for fabricating the same
JP2020043163A (ja) * 2018-09-07 2020-03-19 キオクシア株式会社 半導体装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1601742A (zh) * 2003-09-22 2005-03-30 台湾积体电路制造股份有限公司 金属联机结构及其制造方法
US20080173931A1 (en) * 2007-01-19 2008-07-24 Macronix International Co., Ltd. Multilevel-Cell Memory Structures Employing Multi-Memory Layers with Tungsten Oxides and Manufacturing Method
CN102969233A (zh) * 2011-08-31 2013-03-13 台湾积体电路制造股份有限公司 半导体器件及其形成方法
US20140167181A1 (en) * 2012-12-13 2014-06-19 Samsung Electronics Co., Ltd. Semiconductor devices including a resistor structure and methods of forming the same
US20150325432A1 (en) * 2014-05-07 2015-11-12 Tokyo Electron Limited Film forming method, film forming apparatus and recording medium
TW201543618A (zh) * 2014-05-15 2015-11-16 Macronix Int Co Ltd 半導體結構、電阻式記憶單元結構及半導體結構之製造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020137356A1 (en) * 2001-03-20 2002-09-26 Huang Chi Tung Metallization process of in-situ forming titanium nitride and tungsten nitride in tungsten plug
US20050245074A1 (en) * 2004-04-29 2005-11-03 Ping Jiang In-situ etch-stop etch and ashing in association with damascene processing in forming semiconductor interconnect structures
JP2006054251A (ja) * 2004-08-10 2006-02-23 Toshiba Corp 半導体装置の製造方法
US7323410B2 (en) * 2005-08-08 2008-01-29 International Business Machines Corporation Dry etchback of interconnect contacts
US7670497B2 (en) * 2007-07-06 2010-03-02 International Business Machines Corporation Oxidant and passivant composition and method for use in treating a microelectronic structure
US8101456B2 (en) * 2008-10-01 2012-01-24 International Business Machines Corporation Method to reduce a via area in a phase change memory cell
JP2010171081A (ja) * 2009-01-20 2010-08-05 Toshiba Corp 半導体装置及びその製造方法
DE102010063780A1 (de) * 2010-12-21 2012-06-21 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Halbleiterbauelement mit einer Kontaktstruktur mit geringerer parasitärer Kapazität
TWI490862B (zh) 2011-01-19 2015-07-01 Macronix Int Co Ltd 改良位元線電容單一性之３ｄ陣列記憶體結構
TWI579928B (zh) 2013-01-14 2017-04-21 聯華電子股份有限公司 形成層間介電層的方法
US9040421B2 (en) * 2013-05-03 2015-05-26 GlobalFoundries, Inc. Methods for fabricating integrated circuits with improved contact structures
US9269714B2 (en) 2013-06-10 2016-02-23 Globalfoundries Inc. Device including a transistor having a stressed channel region and method for the formation thereof
US8951429B1 (en) * 2013-10-29 2015-02-10 Applied Materials, Inc. Tungsten oxide processing
US9269585B2 (en) * 2014-01-10 2016-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method for cleaning metal gate surface
JP2016072537A (ja) * 2014-09-30 2016-05-09 株式会社東芝 半導体記憶装置及びその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1601742A (zh) * 2003-09-22 2005-03-30 台湾积体电路制造股份有限公司 金属联机结构及其制造方法
US20080173931A1 (en) * 2007-01-19 2008-07-24 Macronix International Co., Ltd. Multilevel-Cell Memory Structures Employing Multi-Memory Layers with Tungsten Oxides and Manufacturing Method
CN102969233A (zh) * 2011-08-31 2013-03-13 台湾积体电路制造股份有限公司 半导体器件及其形成方法
US20140167181A1 (en) * 2012-12-13 2014-06-19 Samsung Electronics Co., Ltd. Semiconductor devices including a resistor structure and methods of forming the same
US20150325432A1 (en) * 2014-05-07 2015-11-12 Tokyo Electron Limited Film forming method, film forming apparatus and recording medium
TW201543618A (zh) * 2014-05-15 2015-11-16 Macronix Int Co Ltd 半導體結構、電阻式記憶單元結構及半導體結構之製造方法

Also Published As

Publication number Publication date
TW201719811A (zh) 2017-06-01
US9679807B1 (en) 2017-06-13
DE102016222390A1 (de) 2017-05-24
US10026693B2 (en) 2018-07-17
TWI590382B (zh) 2017-07-01
US20170148669A1 (en) 2017-05-25
CN112736032B (zh) 2024-05-24
US20170243823A1 (en) 2017-08-24
CN107046000B (zh) 2021-02-05
CN107046000A (zh) 2017-08-15

Similar Documents

Publication Publication Date Title
US11688631B2 (en) Semiconductor structure with air gap and method sealing the air gap
KR102195673B1 (ko) 원자층 증착 방법들 및 그것의 구조물들
CN107017252B (zh) 带有固相扩散的集成电路结构和方法
US10176995B1 (en) Methods, apparatus and system for gate cut process using a stress material in a finFET device
TWI596650B (zh) 具有矽鍺量子井之高遷移率ｐｍｏｓ及ｎｍｏｓ裝置
TW201807746A (zh) 在凹陷蝕刻製程期間使用氧化處理凹陷閘極結構之方法
US9847252B2 (en) Methods for forming 2-dimensional self-aligned vias
TWI739065B (zh) 減少半導體裝置閘極切割挖除及/或閘極高度損失之方法、機器及系統
US9437479B2 (en) Methods for forming an interconnect pattern on a substrate
CN107046000B (zh) 用于不具有钛衬垫的mol互连的方法及系统
US10854515B2 (en) Methods, apparatus, and system for protecting cobalt formations from oxidation during semiconductor device formation
US10062612B2 (en) Method and system for constructing FINFET devices having a super steep retrograde well
TW202238674A (zh) 半導體裝置、半導體裝置的製造方法及實行蝕刻製程的方法
US20170309623A1 (en) Method, apparatus, and system for increasing drive current of finfet device
US10204797B1 (en) Methods, apparatus, and system for reducing step height difference in semiconductor devices
US20170338325A1 (en) Method, apparatus and system for providing nitride cap layer in replacement metal gate structure
US20120302025A1 (en) Method for Manufacturing a Semiconductor Structure
TWI783302B (zh) 半導體裝置及其形成方法
US11658074B2 (en) Structure and method for FinFET device with source/drain modulation

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant