TWI739065B - 減少半導體裝置閘極切割挖除及/或閘極高度損失之方法、機器及系統 - Google Patents

減少半導體裝置閘極切割挖除及/或閘極高度損失之方法、機器及系統 Download PDF

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TWI739065B
TWI739065B TW108104622A TW108104622A TWI739065B TW I739065 B TWI739065 B TW I739065B TW 108104622 A TW108104622 A TW 108104622A TW 108104622 A TW108104622 A TW 108104622A TW I739065 B TWI739065 B TW I739065B
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height
fin
semiconductor device
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TW201939588A (zh
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高金晟
丹尼爾 傑格
麥克 阿基利諾
派翠克 卡彭特
旭昇 吳
海苟 黃
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美商格芯（美國）集成電路科技有限公司
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Abstract

數種方法，其包含：提供半導體基板；設置在該半導體基板上的鰭片；設置在該鰭片上面的虛擬閘極，其中，該虛擬閘極在該基板上面的第一高度有頂部；以及設置在該鰭片上面且毗鄰該虛擬閘極的層間電介質(ILD)，其中，該ILD在該基板上面的第二高度有頂部，其中，該第二高度低於該第一高度；以及用電介質帽蓋覆蓋該ILD，其中，該電介質帽蓋在該第一高度有頂部。數種系統，其經組配為實施該等方法。用該等方法生產的數種半導體裝置。

Description

減少半導體裝置閘極切割挖除及/或閘極高度損失之方法、機器及系統
本揭示內容大體有關於精密半導體裝置的製造，且更特別的是，有關於減少半導體裝置閘極切割挖除及/或閘極高度損失之各種方法及系統。
製造工業的技術劇變已導致許多新穎創新的製程。當今的製程，特別是半導體製程，需要大量的重要步驟。這些製程步驟常需要大體微調的許多輸入以維持恰當的製造控制。
半導體裝置的製程需要許多離散製程步驟以從未加工半導體材料做成封裝好的半導體裝置。大體上，使用例如曝光工具或步進機的半導體製造工具對有時被稱為批次的半導體晶圓群組執行一套加工步驟。例如，對該等半導體晶圓可執行蝕刻製程以在半導體晶圓上塑造各自可用作電晶體之閘極的物件，例如多晶矽線路。作為另一實施例，可形成例如鋁或銅的複數條金屬線路作為使半導 體晶圓上之一區域連接至另一個的傳導線路。以此方式，可製成積體電路晶片。
如果毗鄰閘極的層間電介質(ILD)在製程步驟期間保持高度及頂面平面性的話，則可改善想要用於製造FinFET半導體裝置的許多製程步驟，其中FET的通道是在設置於基板上的鰭片中且FET的閘極設置在鰭片上面。不過，其他製程步驟可能減少高度及/或挖除ILD的頂面(形成凹坑)。
本揭示內容可應付及/或至少減少上述問題中之一或多個。
以下提出本揭示內容的簡化概要以提供本揭示內容之一些方面的基本理解。此概要並非本揭示內容的窮舉式總覽。它不是旨在確認本揭示內容的關鍵或重要元件或者是描繪本揭示內容的範疇。唯一的目的是要以簡要的形式提出一些概念作為以下更詳細之說明的前言。
本揭示內容大體針對一種方法，其包含：提供半導體基板；設置在該半導體基板上的鰭片；設置在該鰭片上面的虛擬閘極，其中，該虛擬閘極在該基板上面的第一高度有頂部；以及設置在該鰭片上面且毗鄰該虛擬閘極的層間電介質(ILD)，其中，該ILD在該基板上面的第二高度有頂部，其中，該第二高度低於該第一高度；以及用電介質帽蓋覆蓋該ILD，其中，該電介質帽蓋在適合有頂部。
本揭示內容也包括一種半導體裝置，其包含：半導體基板；設置在該半導體基板上的鰭片；設置在該鰭片上面的閘極堆疊，其中，該閘極堆疊有頂部與數個側壁；毗鄰該閘極之該等側壁中之一者的層間電介質(ILD)，其中，該ILD有頂部；以及設置在該ILD之該頂部上的電介質帽蓋，其中，該電介質帽蓋有頂部，且該電介質帽蓋之該頂部與該閘極之該頂部實質共面。
本揭示內容也包括一種半導體裝置製造系統，其適配實施該方法中之一或多個步驟。
本揭示內容可減少毗鄰FinFET半導體裝置閘極之ILD的高度損失及/或頂面挖除。
100‧‧‧半導體結構
105‧‧‧半導體基板
110‧‧‧鰭片
115‧‧‧虛擬閘極
120‧‧‧層間電介質(ILD)層
125‧‧‧間隔件
220‧‧‧ILD
325‧‧‧介電層
330‧‧‧氧化物層
425‧‧‧電介質帽蓋
515‧‧‧金屬閘極
535‧‧‧氮化物帽蓋
640‧‧‧抗蝕層
745‧‧‧溝槽
845‧‧‧金屬
900‧‧‧方法
910-954‧‧‧區塊
1000‧‧‧系統
1010‧‧‧半導體裝置加工系統
1015‧‧‧已加工積體電路/裝置
1020‧‧‧加工控制器
1050‧‧‧搬運機構
參考以下結合附圖的說明可明白本揭示內容，其中類似的元件以相同的元件符號表示，且其中：第1圖根據本文數個具體實施例圖示半導體結構的非寫實描繪；第2圖根據本文數個具體實施例圖示半導體結構在凹陷層間電介質(ILD)之後的非寫實描繪；第3圖根據本文數個具體實施例圖示半導體結構在沉積介電層及氧化物層之後的非寫實描繪；第4圖根據本文數個具體實施例圖示半導體結構在化學機械研磨(CMP)且移除氧化物層之後的非寫實描繪；第5圖根據本文數個具體實施例圖示半導體 結構在取代金屬閘極(RMG)製程之後的非寫實描繪；第6圖根據本文數個具體實施例圖示半導體結構在形成抗蝕層(resist)之後的非寫實描繪；第7圖根據本文數個具體實施例圖示在移除ILD及電介質帽蓋之後的半導體結構；第8圖根據本文數個具體實施例圖示在沉積金屬接觸之後的半導體結構；第9圖根據本文數個具體實施例圖示一種方法的流程圖；以及第10圖根據本文數個具體實施例圖示用於製造半導體裝置之系統的非寫實描繪。
儘管揭露於本文的專利標的容易做成各種修改及替代形式，然而本文仍以附圖為例圖示本發明的幾個特定具體實施例且詳述於本文。不過，應瞭解本文所描述的特定具體實施例並非旨在把本揭示內容限定為本文所揭示的特定形式，反而是，本發明應涵蓋落在如隨附申請專利範圍所界定之本揭示內容精神及範疇內的所有修改、等效及替代性陳述。
以下描述本揭示內容的各種示範具體實施例。為了清楚說明，本專利說明書並未描述實際具體實作的所有特徵。當然，應瞭解，在開發任一此類的實際具體實施例時，必需做許多與具體實作有關的決策以達成開發人員的特定目標，例如遵循與系統相關及商務有關的限制，這 些都會隨著每一個具體實作而有所不同。此外，應瞭解，此類開發即複雜又花時間，決不是本技藝一般技術人員在閱讀本揭示內容後即可承擔的例行工作。
此時以參照附圖來描述本發明。示意圖示於附圖的各種結構、系統及裝置係僅供解釋以及避免熟諳此藝者所習知的細節混淆本發明。儘管如此，仍納入附圖以描述及解釋本揭示內容的示範實施例。應使用與相關技藝技術人員所熟悉之意思一致的方式理解及解釋用於本文的字彙及片語。本文沒有特別定義的術語或片語(亦即，與熟諳此藝者所理解之普通慣用意思不同的定義)旨在用術語或片語的一致用法來說明。如果術語或片語旨在具有特定的意思時(亦即，不同於熟諳此藝者所理解的意思)，則會在本專利說明書中以直接明白地提供特定定義的方式清楚地陳述用於該術語或片語的特定定義。
本文的具體實施例針對數種方法用以在此類裝置之製造期間減少半導體結構中的階差(step height difference)，以及適配實施該等方法中之一或多個部份的數種製造系統。本文的具體實施例提供減少半導體結構中相鄰區域之間的階差，這使得在半導體結構之製造期間有可能執行需要平面或平坦表面的製程步驟(例如，挖槽)。本文的具體實施例提供一種可提供以下優點的方法：減少或排除毗鄰FinFET半導體裝置閘極之ILD的高度損失及/或挖除。
翻到第1圖的非寫實橫截面圖，其圖示可用 作揭露於此之一或多個方法之起始點的半導體結構100。半導體結構100包含半導體基板105，鰭片110係形成於其上。半導體基板105可由塊矽、絕緣體上覆矽(SOI)、或本技藝一般技術人員所習知的其他材料形成。
鰭片110可包含矽、矽-鍺、或其他適當材料。為求方便使用用語“鰭片”；在未圖示於第1圖的其他具體實施例中，鰭片110可為奈米片結構、奈米線結構或其類似者。鰭片110可包含一或多個摻雜物。另外或替換地，鰭片110可包含在鰭片110頂部及/或側邊之部份或全部上的磊晶材料，例如磊晶矽或磊晶矽-鍺。如本技藝一般技術人員所習知的，鰭片110可用作FinFET(場效電晶體)結構的通道。
鰭片110大體有長水平尺寸及與長水平尺寸垂直的短水平尺寸。橫截面是從第1圖沿著鰭片的長水平尺寸繪出。
第1圖也圖示複數個虛擬閘極115。虛擬閘極115可包含本技藝一般技術人員所習知的多晶矽或其他合適虛擬閘極材料。虛擬閘極115大體有長水平尺寸及與長水平尺寸垂直的短水平尺寸。虛擬閘極115的長水平尺寸與鰭片110的長水平尺寸垂直。
毗鄰複數個虛擬閘極中之各個虛擬閘極115的是層間電介質(ILD)層120。ILD 120可由本技藝一般技術人員所習知的任何合適ILD材料形成。
在各虛擬閘極115與各ILD 120之間的是間 隔件125。間隔件125可由氮化矽或習知使用於虛擬閘極製程的其他材料形成。
如圖示，虛擬閘極115、ILD 120及間隔件125的頂部全都可實質共面。總之，圖示於第1圖之半導體結構100的形成可藉由圖案化、蝕刻、沉積、化學機械研磨(CMP)以及本技藝一般技術人員所習知的其他技術。
第2圖根據本文數個具體實施例圖示半導體結構100在使ILD 120凹陷之後的非寫實橫截面圖。使ILD 120凹陷可用本技藝一般技術人員所習知的任何技術。在一具體實施例中，可用電漿輔助乾蝕刻製程使ILD 120凹陷，例如涉及用H2、NF3及NH3電漿副產品曝光ILD 120的製程，例如，SiConiTM蝕刻製程。蝕刻的結果是凹陷ILD 220。
不管如何使ILD 120凹陷，凹陷ILD 220的頂部都會在基板105上面的第二高度處(如點線所示)。虛擬閘極115的頂部與間隔件125的頂部仍在基板105上面的第一高度處(如點線所示)，其中，該第一高度大於(也稱為高於)該第二高度。
第3圖根據本文數個具體實施例圖示半導體結構100在沉積介電層及氧化物層之後的非寫實橫截面圖。介電層325可包含任何適當電介質材料且可用任何適當技術沉積。在具體實施例中，介電層325包含氧化矽碳(SiOC)。本技藝一般技術人員明白，SiOC可稱為“SPARC”。如圖示，介電層325係沉積於半導體結構100上面到虛擬閘極115 及間隔件125的第一高度上面。
隨後沉積氧化物層330於介電層325上面。氧化物層330可包含任何習知氧化物材料。在具體實施例中，氧化物層330包含正矽酸乙酯(TEOS)。用於沉積包括TEOS之氧化物材料的技術為本技藝一般技術人員所習知且不需進一步描述。
第4圖根據本文數個具體實施例圖示半導體結構100在化學機械研磨(CMP)且移除氧化物層之後的非寫實橫截面圖。CMP可實質移除氧化物層330且實質移除高於第一高度的介電層325。用於CMP移除氧化物及電介質材料的製程參數為本技藝一般技術人員所習知。
儘管CMP預期實質移除整個氧化物層330與介電層325在第一高度以上的部份，但有些殘留氧化物仍可能挺過CMP。因此，在一些具體實施例中，可執行非選擇性蝕刻以移除殘留氧化物。可根據由受益於本揭示內容之本技藝一般技術人員判定的製程參數按常規來執行該非選擇性蝕刻。
以及，在一些具體實施例中，CMP非選擇性蝕刻產生設置在ILD 220上的電介質帽蓋425。電介質帽蓋425的頂部實質在高於基板的第一高度，亦即，與虛擬閘極115及間隔件125的頂部實質共面。
第5圖根據本文數個具體實施例圖示半導體結構100在取代金屬閘極(RMG)製程之後的非寫實橫截面圖。大體上，虛擬閘極115被移除且就地形成包含金屬閘 極515及氮化物帽蓋535的閘極堆疊。在具體實施例中，金屬閘極515包含高k金屬。
RMG製程大體為眾所周知。例如，在虛擬閘極115包含多晶矽的具體實施例中，可執行接著是“多晶矽拉扯(poly pull)”製程的反應性離子蝕刻(RIE)閘極切割以移除虛擬閘極115。然後，可執行各種製程以功能化在鰭片110或其他結構中的通道。然後，可使用習知技術來形成金屬閘極515與氮化物帽蓋535。金屬閘極515與氮化物帽蓋535在此可稱為“閘極堆疊”。
儘管不受理論束縛，但電介質帽蓋425在ILD 220上的存在據信至少部份保護包含ILD 220的堆疊在RMG製程的RIE閘極切割期間免於高度損失。在具體實施例中，電介質帽蓋425的頂部比氮化物帽蓋535的頂部低約5奈米。“低於約5奈米”涵蓋電介質帽蓋425之頂部高於氮化物帽蓋535之頂部的具體實施例(未圖示)，亦即，電介質帽蓋425之頂部比氮化物帽蓋535之頂部低約0奈米的具體實施例。
圖示具體實施例與可能有缺乏有可接受高度之電介質帽蓋之特性的先前技術半導體裝置成對比。亦即，本文的具體實施例可提供以下優點：ILD不會遭受高度損失，例如，ILD的最高點實質不低於間隔件及氮化物帽蓋的頂部。
大體上，電介質帽蓋425的頂部實質在基板105上面的第一高度，亦即，與間隔件125的頂部實質共 面。儘管再度不受理論束縛，電介質帽蓋425在ILD 220上的存在據信至少部份最小化包含ILD 220之堆疊的挖除。這與ILD可能缺乏電介質帽蓋的許多先前技術半導體裝置成對比。因此，在許多先前技術裝置中，ILD常被挖除，例如，ILD的頂部中心低於ILD之頂部的側邊。
第6圖根據本文數個具體實施例圖示半導體結構100在形成抗蝕層之後的非寫實橫截面圖。可形成抗蝕層材料640以遮罩未設置在鰭片110上面的電介質帽蓋425。抗蝕層640可包含任何習知抗蝕層材料且可用本技藝一般技術人員所習知的技術來形成及圖案化。
第7圖根據本文數個具體實施例圖示半導體結構100在移除無遮罩ILD 220及無遮罩電介質帽蓋425之後的非寫實橫截面圖。可用對抗蝕層640、氮化物帽蓋535及間隔件125有選擇性(亦即，不蝕刻)的蝕刻技術來執行無遮罩ILD 220及無遮罩電介質帽蓋425的移除。在具體實施例中，無遮罩ILD 220及無遮罩電介質帽蓋425的移除可包含反應性離子蝕刻(RIE)。無遮罩ILD 220及無遮罩電介質帽蓋425的移除產生溝槽745。
第8圖根據本文數個具體實施例圖示半導體結構100在沉積金屬接觸之後的非寫實橫截面圖。溝槽745可用習知技術填滿金屬845。金屬845可在鰭片110、金屬化層及/或將會在後續加工步驟形成的其他導電結構之間形成接觸以產生最終半導體裝置。金屬845可包含習知用於形成接觸的任何金屬，且可由受益於本揭示內容的本技 藝一般技術人員按常規來選定。在具體實施例中，金屬845可為鎢、銅或鈷。
第9圖根據本文數個具體實施例圖示方法900的流程圖。方法900包含：提供(在步驟910)包含半導體基板的半導體結構，設置在該半導體基板上的鰭片；設置在該鰭片上面的虛擬閘極，其中，該虛擬閘極在該基板上面的第一高度有頂部，以及設置在該鰭片上面且毗鄰該虛擬閘極的層間電介質(ILD)；其中，該ILD在該基板上面的第二高度有頂部，其中，該第二高度低於該第一高度。
在具體實施例中，提供步驟(在步驟910)可包含形成(在步驟912)ILD以在第一高度有頂部以及使ILD的頂部凹陷到第二高度(在步驟914)。
方法900也包含：用電介質帽蓋覆蓋(在步驟920)ILD，其中，該電介質帽蓋在該第一高度有頂部。在具體實施例中，該電介質帽蓋可包含氧化矽碳(SiOC)。
在具體實施例中，覆蓋步驟(在步驟920)可包含沉積(在步驟922)例如SiOC的電介質於半導體結構上面，沉積(在步驟924)氧化物於電介質上面，化學機械研磨(CMP)(在步驟926)氧化物及電介質到第一高度，且執行非選擇性蝕刻(在步驟928)以移除氧化物。
在具體實施例中，方法900可復包含：用包含金屬閘極及氮化物帽蓋的閘極堆疊取代(在步驟930)虛擬閘極。在具體實施例中，在取代(在步驟930)後，電介質帽蓋的頂部可比氮化物帽蓋的頂部低5奈米。
方法900可另外包含：移除(在步驟940)電介質帽蓋及ILD以產生溝槽。方法900可額外包含：用接觸金屬填滿(在步驟950)溝槽。
在具體實施例中，該接觸金屬可選自由下列各物組成的群組：鎢與鈷。另外或替換地，在具體實施例中，填滿的步驟(在步驟950)可包含用接觸金屬過填(在步驟952)溝槽且執行CMP(在步驟954)以使接觸金屬的頂部減少到第一高度。
此時翻到第10圖，其根據本文數個具體實施例圖示用於製造半導體裝置之系統的非寫實描繪，其中，第一區域與第二區域之間有階差。系統1000能夠使用上述製程步驟來製造半導體裝置。
半導體裝置加工系統1010可包含各種加工工作站，例如蝕刻加工工作站、微影加工工作站、CMP加工工作站等等。由加工系統1010執行的加工步驟中之一或多個可由加工控制器1020控制。加工控制器1020可為工作站電腦、桌上型電腦、膝上型電腦、平板電腦、或任何其他類型的運算裝置，其包含能夠控制製程、接收製程回饋、接收測試結果數據、執行學習循環調整、執行製程調整等等的一或多個軟體產品。
半導體裝置加工系統1010可製造積體電路於媒體上，例如矽晶圓。加工系統1010可提供已加工積體電路/裝置1015於搬運機構1050上，例如輸送帶系統。在一些具體實施例中，該輸送帶系統可為能夠搬運半導體晶 圓的精密無塵室搬運系統。在具體實施例中，半導體裝置加工系統1010可執行一或多個加工步驟，例如，以上描述及圖示於第9圖的步驟中之一或多個。
在一些具體實施例中，以“1015”標示的物品可為個別晶圓，且在其他具體實施例中，物品1015可為半導體晶圓的群組，例如，一“批次”的半導體晶圓。積體電路或裝置1015可包含電晶體、電容器、電阻器、記憶格、處理器、及/或類似者。在具體實施例中，裝置1015包括複數個電晶體。
系統1000能夠執行涉及各種技術之各種產品的分析及製造。例如，系統1000可使用用於製造CMOS技術、Flash技術、BiCMOS技術、功率裝置、記憶體裝置(例如，DRAM裝置)、NAND記憶體裝置及/或各種其他半導體技術之裝置的設計及生產資料。
半導體裝置加工系統1010可適配以執行下列步驟中之一或多個：提供半導體基板；設置在該半導體基板上的鰭片；設置在該鰭片上面的虛擬閘極，其中，該虛擬閘極在該基板上面的第一高度有頂部；以及設置在該鰭片上面且毗鄰該虛擬閘極的層間電介質(ILD)，其中，該ILD在該基板上面的第二高度有頂部，其中，該第二高度低於該第一高度；以及用電介質帽蓋覆蓋該ILD，其中，該電介質帽蓋在該第一高度有頂部。
半導體裝置加工系統1010可適配以藉由形成該ILD以在該第一高度有該頂部且使該ILD的該頂部凹陷到該第二高度來提供該半導體結構。
半導體裝置加工系統1010可適配以從氧化矽碳(SiOC)來形成該電介質帽蓋。
半導體裝置加工系統1010可適配以藉由沉積電介質(例如，SiOC)於該半導體結構上面，沉積氧化物於該電介質上面，化學機械研磨(CMP)該氧化物及該電介質到該第一高度，且執行非選擇性蝕刻以移除氧化物，來覆蓋該ILD。
半導體裝置加工系統1010可進一步適配：用包含金屬閘極及氮化物帽蓋的閘極堆疊取代該虛擬閘極；移除該電介質帽蓋及該ILD以產生溝槽；以及用接觸金屬填滿該溝槽。
半導體裝置加工系統1010可適配以用鎢或鈷來填滿該溝槽。
半導體裝置加工系統1010可適配以藉由用該接觸金屬過填該溝槽且執行CMP以使該接觸金屬的頂部減少到該第一高度來填滿該溝槽。
半導體裝置加工系統1010可適配，以在用閘極堆疊取代虛擬閘極後，使該電介質帽蓋的頂部比該氮化物帽蓋的頂部低5奈米。
上述方法可用存入非暫時性電腦可讀儲存媒體且由例如運算裝置之處理器執行的指令管控。描述於本文的每個運作可對應至存入非暫時性電腦記憶體或電腦可讀儲存媒體的指令。在各種具體實施例中，該非暫時性電腦可讀儲存媒體包括磁性或光盤儲存裝置，固態儲存裝置，例如快閃記憶體，或其他非揮發性記憶體裝置或數個裝置。存在非暫時性電腦可讀儲存媒體上的電腦可讀指令可為源碼、組合語言碼、目的碼、或可由一或多個處理器解譯及/或執行的其他指令格式。
以上所揭露的特定具體實施例均僅供圖解說明，因為熟諳此藝者在受益於本文的教導後顯然可以不同但等效的方式來修改及實施本揭示內容。例如，可用不同的順序完成以上所提出的製程步驟。此外，除非在以下申請專利範圍中有提及，不希望本發明受限於本文所示之構造或設計的細節。因此，顯然可改變或修改以上所揭露的特定具體實施例而所有此類變體都被認為仍然是在本揭示內容的範疇與精神內。因此，本文提出以下的申請專利範圍尋求保護。
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Claims (16)

  1. 一種製造半導體裝置的方法，該方法包含：形成設置在半導體基板上的鰭片；形成設置在該鰭片上面的虛擬閘極，其中，該虛擬閘極在該半導體基板上面的第一高度有頂部；形成設置在該鰭片上面並與該鰭片接觸且毗鄰該虛擬閘極的層間電介質(ILD)特徵，其中，該ILD在該半導體基板上面的第二高度有頂部，且其中，該第二高度低於該第一高度；用電介質帽蓋覆蓋該ILD，其中，該電介質帽蓋在該第一高度有頂部；用包含金屬閘極及氮化物帽蓋的閘極堆疊取代該虛擬閘極；移除該電介質帽蓋及該ILD以產生溝槽；以及用接觸金屬填滿該溝槽，其中，用該接觸金屬填滿該溝槽包含：用該接觸金屬過填該溝槽且執行CMP以使該接觸金屬的頂部減少到該第一高度。
  2. 如申請專利範圍第1項所述之方法，其中，形成該ILD特徵包含：形成該ILD以在該第一高度有該頂部且使該ILD的該頂部凹陷到該第二高度。
  3. 如申請專利範圍第1項所述之方法，其中，用電介質帽蓋覆蓋該ILD包含：用包含氧化矽碳(SiOC)的電介質帽蓋覆蓋該ILD。
  4. 如申請專利範圍第3項所述之方法，其中，覆蓋該 ILD包含：沉積SiOC於該鰭片、該虛擬閘極及該ILD上面，沉積氧化物於該SiOC上面，化學機械研磨(CMP)該氧化物及該SiOC到該第一高度，且執行非選擇性蝕刻以移除氧化物。
  5. 如申請專利範圍第1項所述之方法，其中，該接觸金屬選自由下列各物組成的群組：鎢、銅及鈷。
  6. 如申請專利範圍第1項所述之方法，其中，用該閘極堆疊取代該虛擬閘極包含：形成該閘極堆疊致使該電介質帽蓋的該頂部比該氮化物帽蓋的該頂部低5奈米。
  7. 一種半導體裝置，其包含：半導體基板；設置在該半導體基板上的鰭片；設置在該鰭片上面的閘極堆疊，其中，該閘極堆疊有頂部與數個側壁；設置在該鰭片上面並與該鰭片接觸且毗鄰該閘極之該等側壁中之一者的層間電介質(ILD)，其中，該ILD有頂部；設置在該ILD之該頂部上的電介質帽蓋，其中，該電介質帽蓋有頂部，且該電介質帽蓋之該頂部與該閘極之該頂部實質共面；以及填滿溝槽的接觸金屬，其中，藉由移除該電介質帽蓋及該ILD來產生該溝槽，且將該接觸金屬的頂部減少到第一高度，該第一高度是該閘極堆疊之該 頂部的高度。
  8. 如申請專利範圍第7項所述之半導體裝置，其中，該電介質帽蓋的該頂部比該閘極堆疊的該頂部低5奈米。
  9. 如申請專利範圍第7項所述之半導體裝置，其中，該半導體裝置用一方法形成，該方法包含：提供半導體基板；設置在該半導體基板上的鰭片；設置在該鰭片上面的虛擬閘極，其中，該虛擬閘極在該半導體基板上面的第一高度有頂部；以及設置在該鰭片上面且毗鄰該虛擬閘極的層間電介質(ILD)，其中，該ILD在該半導體基板上面的第二高度有頂部，其中，該第二高度低於該第一高度；以及用電介質帽蓋覆蓋該ILD，其中，該電介質帽蓋在該第一高度有頂部。
  10. 如申請專利範圍第9項所述之半導體裝置，其中，該電介質帽蓋包含氧化矽碳(SiOC)。
  11. 一種製造半導體裝置的系統，該系統包含：用以製造該半導體裝置的半導體裝置加工系統；以及可操作地耦合至該半導體裝置加工系統的加工控制器，該加工控制器經組配為控制該半導體裝置加工系統的運作；其中，該半導體裝置加工系統適配：提供半導體基板；設置在該半導體基板上的鰭 片；設置在該鰭片上面的虛擬閘極，其中，該虛擬閘極在該半導體基板上面的第一高度有頂部；以及設置在該鰭片上面並與該鰭片接觸且毗鄰該虛擬閘極的層間電介質(ILD)，其中，該ILD在該半導體基板上面的第二高度有頂部，其中，該第二高度低於該第一高度；用電介質帽蓋覆蓋該ILD，其中，該電介質帽蓋在該第一高度有頂部；用包含金屬閘極及氮化物帽蓋的閘極堆疊取代該虛擬閘極；移除該電介質帽蓋及該ILD以產生溝槽；以及用接觸金屬填滿該溝槽，其中，該半導體裝置加工系統適配藉由用該接觸金屬過填該溝槽且執行CMP以使該接觸金屬的頂部減少到該第一高度，來用該接觸金屬填滿該溝槽。
  12. 如申請專利範圍第11項所述之系統，其中，該半導體裝置加工系統適配以形成該ILD以在該第一高度有該頂部且使該ILD的該頂部凹陷到該第二高度。
  13. 如申請專利範圍第11項所述之系統，其中，該半導體裝置加工系統適配從氧化矽碳(SiOC)來形成該電介質帽蓋。
  14. 如申請專利範圍第13項所述之系統，其中，該半導體裝置加工系統適配藉由沉積SiOC於該鰭片、該虛擬閘極及該ILD上面，沉積氧化物於該SiOC上面，化 學機械研磨(CMP)該氧化物及該SiOC到該第一高度，且執行非選擇性蝕刻以移除氧化物，來覆蓋該ILD。
  15. 如申請專利範圍第11項所述之系統，其中，該半導體裝置加工系統適配從鎢或鈷來形成該接觸金屬。
  16. 如申請專利範圍第11項所述之系統，其中，在該半導體裝置加工系統用該閘極堆疊取代該虛擬閘極之後，該電介質帽蓋的該頂部比該氮化物帽蓋的該頂部低5奈米。
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