CN1127149C - 绝缘体上硅传输门干扰的解决方法 - Google Patents
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Abstract
N型MOSFET的SOI传输门干扰的解决方法，在FET的栅与体之间连接电阻器以消除干扰状态。此FET制造在衬底中，具有源、漏和栅，场效应晶体管的体是电浮置的，且基本上与衬底电隔离。提供了将FET的电浮置体耦合到栅的高阻通路，致使当栅处于低位时，在能够出现明显的热充电之前，体向低态放电，从而防止了当晶体管处于关断时电荷在体上的积累。高阻通路的电阻最好约为1010Ωμm除以传输门的宽度。
Description
技术领域
本发明一般涉及到绝缘体上硅(SOI)传输门干扰的解决方法，更确切地说是涉及到N型金属氧化物半导体场效应晶体管(MOSFET)的SOI传输门干扰的解决方法，以及这样的场效应晶体管及其制造方法。
背景技术
N型MOSFET被用作互补金属氧化物半导体(CMOS)电路中的传输门，以提高密度和改进性能。在SOI中，FET的体即衬底是电浮置的。当源电极和漏电极在比发热时间长的时间内保持高位而栅保持低位时，这一浮置导致干扰问题，随之引起输入(通常是源)引起的从高位到低位的跃迁。跃迁之前在体中产生的空穴，在跃迁过程中被低电位拉入源中。以源作为发射极、体作为基极、漏作为收集极的双极增益，在传输门的输出(通常是漏)处导致由NPN的β乘以体放电电流公式(Cgate×Vdd/Tfall)给出的电流脉冲。此电流脉冲能够引起待要用传输门隔离的电路错误地发生向低态的跃迁。
目前解决这一问题的方法是提高被传输门隔离的电路的噪声容限和/或增加工艺步骤以降低NPN寄生双极增益。
提高称为闭锁电路的隔离电路的抗电流脉冲性，由于要求从传输门得到更多的电流以完成所希望的向低态的跃迁，故损害了性能。降低NPN增益则要求引入额外的工艺步骤，这涉及到损害漏电性能和制造工艺热循环。
发明内容
因此，本发明的主要目的是提供一种SOI传输门干扰的解决方法。
本发明的另一目的是提供一种N型MOSFET的SOI传输门干扰的解决方法，其中在MOSFET的栅与体之间连接一个电阻器以消除干扰状态。
借助于在传输门的栅与体之间加入电阻器，本发明消除了干扰状态，此电阻器的电阻值约为1010Ωμm除以传输门的宽度。在这一电阻值下，当栅处于低位时，在出现明显的热充电之前，体总是向低态放电，从而在传输门关断时防止体电荷的积累或建立。电阻器的电阻值足够高，致使当栅处于高位而源和漏处于低位时，从栅到体的电流比之MOSFET的亚阈值电流可忽略不计。此电路由于低的栅电位使体接地，还明显减小了SOI MOSFET中待机电流的增大，并阻止了由漏的雪崩电流对体的充电所造成的阈值电压(Vt)的下降。
根据此处所述，本发明提供了一种具有源、漏和栅的场效应晶体管以及在衬底中制造的方法，其中场效应晶体管的体是电浮置的，且晶体管基本上与衬底电隔离。根据本发明，提供了高阻通路，用来将场效应晶体管的电浮置体耦合到场效应晶体管的栅。在运行过程中，当栅处于低位时，在能够出现明显的热充电之前，高阻通路使体向低态放电，从而在晶体管处于关断时防止电荷在体上积累。
更详细地说，高阻通路的电阻值约为1010Ωμm除以传输门的宽度。高阻通路足够高，致使当栅处于高位而源和漏处于低位时，从栅到体的电流比之亚阈值电流可忽略不计。
晶体管最好制造成SOI MOSFET，且此电路由于得到的低的栅电位使体接地而明显减小SOI MOSFET中待机电流的增大，并阻止由漏电流的雪崩倍增对体的充电所造成的阈值电压(Vt)的下降。
附图说明
结合附图，参照本发明最佳实施例的下列详细描述，本技术领域熟练人员可以更容易地理解本发明的SOI传输门干扰的解决方法的上述目的和优点，在这些附图中，用完全相同的参考号来表示相同的元件，其中：
图1是用作CMOS电路传输门的典型现有技术N型MOSFET的示意图。
图2是根据本发明的N-MOSFET传输门电路的示范性实施例的示意图，其中在晶体管的栅和体即衬底之间加入了一个电阻器。
图3是FET的原理图，其中的体即衬底电浮置。
图4是制作示范性实施例的晶体管的步骤a)到f)的顺序，此实施例在晶体管的栅和体之间连接有电阻器。
图5是在图4的步骤中制作的晶体管的俯视图。
具体实施方式
详细参照附图，图1示出了用作CMOS电路中的传输门的典型N型MOSFET SOI电路10。此N型MOSFET SOI电路10包含具有第一源/漏11和第二源/漏12的MOSFET 30，并受栅60控制。在此类电路中，如图3所示，FET的体即衬底电浮置，当源和漏电极11和12在比100微秒的热发生时间更长的时间内处于高位亦即1.8V，而栅60处于低位亦即0V时，导致干扰问题，随之由输入源11引起从高位到低位的跃迁。跃迁之前体40中产生的空穴，在跃迁过程中被低电位拉入源11中。以源11作为发射极、体40作为基极、漏12作为收集极，空穴的这一运动在漏12处引起电流脉冲，传输门的输出由NPN的β乘以表示为(Cgate×Vdd/Tfall)的体40的放电电流给出。此电流脉冲能够引起被传输门隔离的锁存电路50在上述条件下错误地发生向低态例如0V的跃迁。
图2示出了根据本发明的N型MOSFET传输门电路20的示范性实施例，其中电阻器70连接在晶体管30的栅60和体40之间，以消除干扰状态。此电阻器70通常由轻度掺杂的例如约为10000Ωcm的、窄的例如约为0.25微米的多晶硅线条组成。
图5示出了在栅60与体40之间连接有电阻器70的晶体管30的俯视图。图4(a)-(f)示出了沿剖面500(图5)制作此器件的6个阶段。
图4(a)示出了制作在包含衬底硅层101、底部二氧化硅层102和顶部硅层103的绝缘体上硅晶片顶部的大约20nm的二氧化硅层104。然后在层104的顶部制作大约40nm的氮化硅层105。再借助于形成光刻胶层106并腐蚀氮化硅层105、二氧化硅104和顶部硅层103，最终停止于底部二氧化硅层102，而对二个隔离区107(图4(b))进行图形化。
如图4(b)所示，剥离留下的光刻胶106(图4(a))，然后用二氧化硅填充槽107，并借助于在衬垫二氧化硅层104停止的深腐蚀和/或化学机械抛光而进行整平。NFET体区108制作在二个隔离区107之间。在制作之后，对区域108进行光掩蔽和P型掺杂。在形成MOSFET阈值电压注入和衬垫二氧化硅104被剥离之后，在区域108上生长大约2.5-7.0nm的栅氧化层109。
图4(c)示出了制作在沟槽107和区域109上的本征多晶硅层110。在淀积并图形化光刻胶层之后，对多晶硅111进行腐蚀，此腐蚀停止于沟槽107和区域109的栅氧化物处。淀积例如Si3N4的间隔材料并对其进行方向性腐蚀。安置N+注入剂源/漏掩模，并将例如砷的n型掺杂剂注入到N-源/漏211和212(图5)区和栅112中。将成为体接触区113的区域和多晶硅栅114的相邻末端被阻挡于N型注入剂，且随后用P+源/漏掩模213(图5)和例如硼的掺杂剂进行P+掺杂。
如图4(d)所示，在整个结构100上淀积诸如钛或钴的金属层115之后，对其进行退火，以便在金属物理上接触硅或多晶硅的区域中形成硅化物。间隔127和氧化物区107上的其余金属被选择性地腐蚀掉。在整个结构100上共形淀积大约50nm的氮化硅118。在氮化硅中光掩蔽并腐蚀接触区116和117。
如图4(e)所示，在整个结构100上淀积大约20nm的轻度掺杂的大约100kΩcm的N型多晶硅119，并进行图形化和腐蚀，以便在栅与体接触区116和117之间留下电阻条119。最后，如图4(f)所示，用化学机械抛光和/或深腐蚀方法，淀积并整平诸如二氧化硅或氮化硅构成的钝化层120。执行另外一些常规工艺步骤以完成图2所示的根据本发明的N型MOSFET传输门电路20的示范性实施例。上述的方法仅仅是以举例的方式公开的，而不是对本发明的限制。
电阻器70的电阻值约为1010Ωμm除以传输门的宽度。在这一电阻值下，当栅60处于低位时，在能够出现明显的热充电之前，体40总是向低态例如0V放电，从而防止体电荷在传输门处于关断时的积累或建立。电阻器70的电阻值足够高，致使当栅处于高位例如1.8V而源11和漏12处于低位例如0V时，从栅60到体40的电流与MOSFET的约为2nA/μ m的亚阈值电流相比可忽略不计，例如大约为0.2nA/μm。此电路明显地减小SOI MOSFET中的待机电流的增大。这一较小的增大是由使体40接地的低的栅60电位造成的，并由于任何这种漏12到体40的漏电都被栅60到体40的电阻器70耗散而阻止了由漏12电流的雪崩倍增对体40的充电所造成的阈值电压(Vt)的下降。
所述的实施例是N型MOSFET30。然而本发明也包含P型MOSFET，其中电路将反映倒转过来的实施例。
虽然此处详细描述了本发明的SOI传输门干扰解决方法的最佳实施例和变例，但显然，对于本技术领域熟练人员来说，本发明的公开和说明可以提出许多不同的设计。
Claims (10)
1.制造于衬底中的具有源、漏和栅的场效应晶体管，其中场效应晶体管的体是电浮置的，且晶体管基本上与衬底电隔离，其特征在于包含：将场效应晶体管的电浮置体耦合到场效应晶体管的栅的高阻通路，致使当栅处于低位时，在能够出现明显的热充电之前，体向低态放电，从而防止当晶体管处于关断时电荷在体上的积累。
2.权利要求1的场效应晶体管，其中的高阻通路的电阻为1010Ωμm除以传输门的宽度。
3.权利要求1的场效应晶体管，其中的高阻通路的电阻值足够高，致使当栅处于高位而源和漏处于低位时，从栅到体的电流与亚阈值电流相比可忽略不计。
4.权利要求1的场效应晶体管，其中的晶体管制造成SOIMOSFET。
5.权利要求4的场效应晶体管，其中的电路由于低的栅电位使体接地而明显地减小SOI MOSFET中待机电流的增大，防止由漏电流的雪崩倍增对体的充电所造成的阈值电压Vt的下降。
6.一种场效应晶体管的制造方法，它包含在衬底中制造具有源、漏和栅的场效应晶体管，其中场效应晶体管的体是电浮置的，且此晶体管基本上与衬底电隔离，并提供将场效应晶体管的电浮置体耦合到场效应晶体管的栅的高阻通路，以便当栅处于低位时，在能够出现明显的热充电之前，使体向低态放电，从而防止当晶体管处于关断时电荷在体上的积累。
7.权利要求6的场效应晶体管的制造方法，还包含提供等于1010Ωμm除以传输门的宽度的高阻通路的电阻。
8.权利要求6的场效应晶体管的制造方法，还包含提供高阻通路足够高的电阻值，使当栅处于高位而源和漏处于低位时，从栅到体的电流与MOSFET的亚阈值电流相比可忽略不计。
9.权利要求6的场效应晶体管的制造方法，包括将晶体管制造成SOI MOSFET。
10.权利要求9的场效应晶体管的制造方法，还包含由于低的栅电位使体接地而减小SOI MOSFET中待机电流的增大，并防止由漏电流雪崩倍增对体的充电所造成的阈值电压Vt的下降。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/163,950 US6100564A (en) | 1998-09-30 | 1998-09-30 | SOI pass-gate disturb solution |
| US09/163,950 | 1998-09-30 |
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| Publication Number | Publication Date |
|---|---|
| CN1249539A CN1249539A (zh) | 2000-04-05 |
| CN1127149C true CN1127149C (zh) | 2003-11-05 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN99118748A Expired - Fee Related CN1127149C (zh) | 1998-09-30 | 1999-09-16 | 绝缘体上硅传输门干扰的解决方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (2) | US6100564A (zh) |
| KR (1) | KR100394752B1 (zh) |
| CN (1) | CN1127149C (zh) |
| MY (1) | MY124337A (zh) |
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| CN102725850A (zh) * | 2010-01-05 | 2012-10-10 | 国际商业机器公司 | 具有减小的寄生电容的体接触晶体管 |
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-
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- 1999-08-12 KR KR10-1999-0033085A patent/KR100394752B1/ko not_active IP Right Cessation
- 1999-08-27 MY MYPI99003693A patent/MY124337A/en unknown
- 1999-09-16 CN CN99118748A patent/CN1127149C/zh not_active Expired - Fee Related
-
2000
- 2000-05-24 US US09/577,549 patent/US6498058B1/en not_active Expired - Fee Related
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| CN102725850A (zh) * | 2010-01-05 | 2012-10-10 | 国际商业机器公司 | 具有减小的寄生电容的体接触晶体管 |
| CN102725850B (zh) * | 2010-01-05 | 2014-12-24 | 国际商业机器公司 | 具有减小的寄生电容的体接触晶体管 |
| US9269783B2 (en) | 2010-01-05 | 2016-02-23 | International Business Machines Corporation | Body contacted transistor with reduced parasitic capacitance |
Also Published As
| Publication number | Publication date |
|---|---|
| MY124337A (en) | 2006-06-30 |
| KR100394752B1 (ko) | 2003-08-14 |
| US6498058B1 (en) | 2002-12-24 |
| CN1249539A (zh) | 2000-04-05 |
| US6100564A (en) | 2000-08-08 |
| KR20000022701A (ko) | 2000-04-25 |
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