CN112635319A - 肖特基二极管 - Google Patents

肖特基二极管 Download PDF

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CN112635319A
CN112635319A CN202011017839.8A CN202011017839A CN112635319A CN 112635319 A CN112635319 A CN 112635319A CN 202011017839 A CN202011017839 A CN 202011017839A CN 112635319 A CN112635319 A CN 112635319A
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semiconductor substrate
polysilicon
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马诺耶·梅赫罗特拉
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Texas Instruments Inc
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Abstract

本申请案的实施例涉及肖特基二极管。一种方法包含在半导体衬底(110)中形成第一沟槽和第二沟槽(112、122)。所述方法另外包含用多晶硅(116、126)填充所述第一沟槽和所述第二沟槽。所述多晶硅(116、126)与所述半导体衬底(110)相反地经掺杂。肖特基触点(142)形成于所述半导体衬底(110)上所述第一沟槽和所述第二沟槽(112、122)之间。所述方法还包含形成用于所述肖特基触点(142)的阳极电极(150)。所述阳极电极(150)耦合到所述第一沟槽和所述第二沟槽(112、122)中的多晶硅(116、126)。

Description

肖特基二极管
技术领域
本申请案的实施例涉及半导体技术，且更特定来说，涉及肖特基二极管。
背景技术
肖特基二极管是由半导体和金属的结形成的半导体二极管。金属-半导体结产生肖特基“势垒”。金属形成二极管的阳极，且半导体形成二极管的阴极。因而，正向电流(当二极管被正向加偏压时)是从金属/阳极到半导体/阴极。与半导体-半导体(p-n)结相比，肖特基势垒产生相对快速切换和低的正向电压降。肖特基势垒的正向电压降可以在例如150mV到450mV的范围内。肖特基势垒的反向恢复时间(当二极管从导电切换到不导电状态时)显著低于p-n结的情况。由于肖特基二极管的相对低的正向电压和快速切换速度，肖特基二极管通常用于例如以下的应用中：电压钳、晶体管饱和防止、防止例如电池在夜间通过太阳能面板放电的电源系统、开关电压调节器中的整流器、采样保持电路，以及其它应用。
由于肖特基二极管的低正向电压，肖特基二极管还表征为与p-n结相比较高的反向泄漏电流。反向泄漏电流是当肖特基二极管被反向加偏压时流过肖特基二极管的电流。肖特基二极管的金属-半导体界面周围的电场归因于肖特基触点的锐边缘而相对较高，且反向泄漏电流与电场成比例。因而，较高电场意味着相对于p-n结，肖特基二极管的较高反向泄漏电流。
发明内容
在一个实例中，一种方法包含在半导体衬底中形成第一沟槽和第二沟槽。所述方法另外包含用多晶硅填充所述第一沟槽和所述第二沟槽。多晶硅与半导体衬底相反地经掺杂。通过在半导体衬底上在所述第一沟槽和所述第二沟槽之间形成肖特基触点来产生肖特基二极管。所述方法还包含形成肖特基二极管的阳极电极。阳极电极形成于肖特基触点上并且耦合到所述第一沟槽和所述第二沟槽中的多晶硅。
附图说明
为了详细描述各种示例，现将参考附图，在附图中：
图1说明根据一个实例的肖特基二极管。
图2说明根据另一实例的肖特基二极管。
图3说明根据又一实例的肖特基二极管。
图4说明肖特基二极管的另一实例。
图5说明根据另一实例的肖特基二极管。
图6说明根据另一实例的肖特基二极管。
图7说明根据另一实例的肖特基二极管。
图8说明肖特基二极管的另一实例。
图9说明肖特基二极管的另一实例。
具体实施方式
图1示出实例肖特基二极管100。在此实例中，肖特基二极管100包含硅衬底110(例如，N型)。已在硅衬底中蚀刻了沟槽112和122。用氮氧化物(或其它合适的介电材料)层114为沟槽112加衬。接着用多晶型硅(polycrystalline silicon)116(“多晶硅(polysilicon)”)填充沟槽112。在一个实例中，硅衬底110经N掺杂且多晶硅116经P掺杂。类似地，用氮氧化物层124为沟槽122加衬，并且接着填充多晶硅126。可在相同的工艺步骤期间形成沟槽112中的氮氧化物114所述沟槽122中的氮氧化物124。类似地，也可在相同的工艺步骤期间形成沟槽112中的多晶硅116和沟槽122中的多晶硅126。
仍参考图1，接触插塞130、132、134、136、138和140形成于硅衬底110上方。用钛/氮化钛(Ti/TiN)势垒131为每一接触插塞130、132、134、136、138和140加衬并且接着填充例如钨135。在一个实例中，牺牲性氧化物层137形成于硅衬底110上方，且在氧化物层137中蚀刻用于接触插塞的腔。Ti/TiN层131沉积于腔内，并且接着用钨135填充所述腔。接着移除牺牲性氧化物层137。肖特基二极管100另外包含与接触插塞130-138接触的阳极电极150和与接触插塞140接触的阴极电极152。阳极电极150借助于接触插塞130和138分别耦合到沟槽112、122中的多晶硅116、126。插塞140的Ti/TiN层131接触金属层139(例如，硅化物，例如硅化钴、硅化镍等)而非半导体衬底110以便形成欧姆接触而非肖特基势垒。接触插塞130与沟槽112的多晶硅116接触。接触插塞138与沟槽122的多晶硅126接触。在此实例中，展示两个接触插塞134与硅衬底110接触。一般来说，取决于其中将使用肖特基二极管100的应用的电流需要，可形成与硅衬底110接触的任何数目个接触插塞134(一或多个)。
用于接触插塞134的Ti/TiN层131与硅衬底110接触并且因此形成如所示的区142中的肖特基接触。多晶硅116(例如，P掺杂)、氮氧化物114和硅衬底110(例如，N掺杂)的组合形成第一栅控二极管区。类似地，多晶硅126(例如，P掺杂)、氮氧化物124和硅衬底110的组合形成第二栅控二极管区。当肖特基二极管100被反向加偏压时，多晶硅116、126充当控制衬底110内的电场的栅极。当肖特基二极管110被反向加偏压(即，相对于阴极电极152将负电压置于阳极电极150上)时，多晶硅116/126上的电压低于衬底110上的电压。因而，肖特基接触的区142中的电场归因于电荷共享效应或场板效应而减小。由于区142中的电场的减小，因此还有利地减小反向泄漏电流(即，当肖特基二极管被反向加偏压时在阳极电极150和阴极电极152之间的电流)且当被正向加偏压时不增加正向电压。
图1的实例还说明p掺杂区170和172，其形成相对于n掺杂硅衬底110的p-n结。当肖特基二极管110被反向加偏压时，形成于p掺杂区170和n掺杂衬底110之间以及p掺杂区172和衬底110之间的p-n结也被反向加偏压，这有助于进一步减小电场笔钱因此进一步减小反向泄漏电流。
图2示出与图1的但具有一个较大插塞210而非沟槽112和122之间的多个较小插塞132、134和136的肖特基二极管200的实例。在此实例中，单个较大插塞210包括薄Ti/TiN层并且填充钨，这与针对图1的插塞132、134和136的情况是一样的。单个肖特基触点220形成于Ti-TiN层131与半导体衬底110之间。因为图2中的插塞210具有与硅衬底110接触的较大表面积，所以图2的肖特基二极管200能够提供高于图1的电流电平，前提是其它所有条件都相等。
图3说明与图2的类似但具有在y方向上形成于相邻的填充钨的插塞210之间的P掺杂区310的肖特基二极管300的实例。因此，图3中示出的结构包括在y方向上通过P掺杂区310隔开的交替肖特基触点220。P掺杂区310有助于进一步减小每一肖特基触点220周围的区中的电场。
图4示出与图2的类似但具有形成于Ti/TiN层131与用于插塞210的半导体衬底110之间以及插塞130(和138)与多晶硅116(和126)之间的硅化物410的肖特基二极管400的实例。可使用具有大到足以形成肖特基触点220的势垒高度的硅化物。在一个实例中，硅化物包括硅化钯或硅化铂。
在图1和2的实例中，肖特基二极管100和200包含半导体衬底110的顶表面附近和肖特基接触区142附近的相对小的经掺杂半导体区170和172。图5示出与图2的类似但具有两个沟槽512和522且每一沟槽具有环绕沟槽延伸的掺杂区的实例肖特基二极管500。即，沟槽512具有环绕沟槽的掺杂区570(例如，p掺杂)，且沟槽522具有环绕沟槽的掺杂区572(例如，p掺杂)。对于沟槽112和122，沟槽512和522填充有多晶硅516、526，且介电层514、524(例如，氮氧化物)安置于沟槽的多晶硅与外部掺杂区之间。在蚀刻沟槽512、522之后，掺杂区570、572形成为植入体。在植入掺杂区之后，形成介电层514、524并且接着用多晶硅填充沟槽。
p掺杂区570、572和n掺杂衬底110形成p-n结，其当被反向加偏压时减少其中形成肖特基接触的区542中的电场，进而与例如图2的肖特基二极管200相比产生较低反向泄漏电流，前提是其它所有条件都相等。然而，因为掺杂区570、572大于图1和2的实例中的掺杂区，所以形成于插塞210与掺杂区570、572之间的寄生电容大于针对肖特基二极管100和200的情况。较大电容造成肖特基二极管500与肖特基二极管100、200相比较慢的切换速度，但肖特基二极管500与肖特基二极管100、200相比将具有较小反向泄漏电流。
图6示出与图5的肖特基二极管500类似但包含插塞130与多晶硅516之间和插塞138与多晶硅526之间的硅化物610的肖特基二极管600的实例。在一个实例中，硅化物包括硅化钯或硅化铂。
图7示出与图2的肖特基二极管200类似但半导体衬底710包含不同掺杂浓度的多个区的肖特基二极管700的实例。在图7的实例中，衬底710包含区710和720。区730形成于插塞210与区720之间。在一个实例中，区720和730均经N掺杂但区730中的掺杂浓度大于区720中的掺杂浓度。沟槽112、122的底部附近的区715中的电场最强，且与使用较高经掺杂半导体衬底的情况相比，较低掺杂区720有助于进一步减小区715中的电场。
图8示出与图2的肖特基二极管200类似但具有跨沟槽112和122两者形成的硅化物810(例如，硅化钯、硅化铂等)而非如图4和6的实例中的单独硅化物区的肖特基二极管800的实例。较大硅化物区域有助于改进插塞130、210和138的Ti/TiN层131与对应多晶硅116、衬底110和多晶硅126之间的接触电阻。
图9示出与图5的肖特基二极管200类似但在沟槽912和922的底部906处或周围具有植入区910的肖特基二极管800的实例。植入区910与衬底110相反地经掺杂。举例来说，衬底110经N掺杂且植入区910经P掺杂。形成于经P掺杂植入区910与经N掺杂衬底之间的p-n结有助于相对于例如肖特基二极管200增加肖特基二极管900的反向击穿电压。然而，植入区910不会像针对图5的实例肖特基二极管500的情况一样沿沟槽912、924的侧部向上延伸到肖特基接触的区942。

Claims (20)

1.一种方法，其包括：
在半导体衬底中形成第一沟槽；
在所述半导体衬底中形成第二沟槽；
用多晶硅填充所述第一沟槽和所述第二沟槽，所述多晶硅与所述半导体衬底相反地经掺杂；
在所述半导体衬底上在所述第一沟槽和所述第二沟槽之间形成肖特基触点；和
在所述肖特基触点上形成阳极电极，所述阳极电极耦合到所述第一沟槽和所述第二沟槽中的所述多晶硅。
2.根据权利要求1所述的方法，其中所述半导体衬底经n掺杂且所述第一沟槽和所述第二沟槽中的所述多晶硅经p掺杂。
3.根据权利要求1所述的方法，其另外包括在所述第一沟槽中的所述多晶硅与所述半导体衬底之间和所述第二沟槽中的所述多晶硅与所述半导体衬底之间形成介电层。
4.根据权利要求3所述的方法，其另外包括在所述半导体衬底中在所述第一沟槽的所述介电层与所述肖特基触点之间和所述第二沟槽的所述介电层与所述肖特基触点之间形成掺杂区。
5.根据权利要求4所述的方法，其中所述掺杂区与所述半导体衬底相反地经掺杂。
6.根据权利要求1所述的方法，其另外包括在所述半导体衬底中在所述第一沟槽的所述多晶硅与所述肖特基触点之间和所述第二沟槽的所述多晶硅与所述肖特基触点之间形成掺杂区。
7.根据权利要求6所述的方法，其中所述掺杂区为所述第一沟槽和所述第二沟槽加衬。
8.根据权利要求1所述的方法，其中在所述半导体衬底上在所述第一沟槽和所述第二沟槽之间形成肖特基触点包括在所述半导体衬底上在所述第一沟槽和所述第二沟槽之间形成第一肖特基触点和第二肖特基触点。
9.根据权利要求1所述的方法，其中所述阳极电极在所述第一沟槽和所述第二沟槽之间耦合到所述半导体衬底的第一表面，且所述方法另外包括形成耦合到所述半导体衬底的所述第一表面内的金属层的阴极电极。
10.一种结构，其包括：
第一沟槽，其处于半导体衬底中，所述第一沟槽包含多晶硅；
第二沟槽，其处于所述半导体衬底中，所述第二沟槽包含多晶硅，所述多晶硅与所述半导体衬底相反地经掺杂；
肖特基触点，其在所述半导体衬底上处于所述第一沟槽和所述第二沟槽之间；和
阳极电极，其处于所述肖特基触点上，所述阳极电极耦合到所述第一沟槽和所述第二沟槽中的所述多晶硅。
11.根据权利要求10所述的结构，其中所述半导体衬底经n掺杂且所述第一沟槽和所述第二沟槽中的所述多晶硅经p掺杂。
12.根据权利要求10所述的结构，其另外包括处于所述第一沟槽中的所述多晶硅与所述半导体衬底之间和所述第二沟槽中的所述多晶硅与所述半导体衬底之间的介电层。
13.根据权利要求12所述的结构，一掺杂区在所述半导体衬底中处于所述第一沟槽的所述介电层与所述肖特基触点之间和所述第二沟槽的所述介电层与所述肖特基触点之间。
14.根据权利要求13所述的结构，其中所述掺杂区与所述半导体衬底相反地经掺杂。
15.根据权利要求10所述的结构，一掺杂区在所述半导体衬底中处于所述第一沟槽的所述多晶硅与所述肖特基触点之间和所述第二沟槽的所述多晶硅与所述肖特基触点之间。
16.根据权利要求15所述的结构，其中所述掺杂区为所述第一沟槽和所述第二沟槽加衬。
17.根据权利要求10所述的结构，其中所述阳极电极耦合到所述半导体衬底的第一表面，且所述结构另外包括耦合到所述半导体衬底的所述第一表面内的金属层的阴极电极。
18.一种方法，其包括：
在半导体衬底中形成第一沟槽；
在所述半导体衬底中形成第二沟槽；
用多晶硅填充所述第一沟槽和所述第二沟槽，所述多晶硅与所述半导体衬底相反地经掺杂；
在所述半导体衬底上在所述第一沟槽和所述第二沟槽之间形成肖特基触点；
在所述半导体衬底上在所述第二沟槽的与所述肖特基触点相对的侧上形成阴极触点；
在所述半导体衬底中在所述第一沟槽与所述肖特基触点之间和所述第二沟槽与所述肖特基触点之间形成掺杂区，所述掺杂区与所述半导体衬底相反地经掺杂；
在所述肖特基触点上形成阳极电极，所述阳极电极耦合到所述第一沟槽和所述第二沟槽中的所述多晶硅；和
在所述阴极触点上形成阴极电极。
19.根据权利要求18所述的方法，其另外包括在所述第一沟槽中的所述多晶硅与所述半导体衬底之间和所述第二沟槽中的所述多晶硅与所述半导体衬底之间形成介电层。
20.根据权利要求19所述的方法，其另外包括在所述半导体衬底中在所述第一沟槽的所述介电层与所述肖特基触点之间和所述第二沟槽的所述介电层与所述肖特基触点之间形成掺杂区。
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