CN112599488A - 包括厚金属层的半导体器件 - Google Patents

包括厚金属层的半导体器件 Download PDF

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Publication number
CN112599488A
CN112599488A CN202010704750.2A CN202010704750A CN112599488A CN 112599488 A CN112599488 A CN 112599488A CN 202010704750 A CN202010704750 A CN 202010704750A CN 112599488 A CN112599488 A CN 112599488A
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Prior art keywords
insulating layer
disposed
thickness
layer
semiconductor device
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CN202010704750.2A
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Inventor
李周益
慎重垣
张志熏
韩正勋
李俊雨
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN112599488A publication Critical patent/CN112599488A/zh
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Abstract

提供了一种半导体器件,所述半导体器件包括设置在层间绝缘层中并且设置在基底上的多个中间互连件和多个中间插塞。上绝缘层设置在层间绝缘层上。第一上插塞、第一上互连件、第二上插塞和第二上互连件设置在上绝缘层中。所述多个中间互连件中的每个具有第一厚度。第一上互连件具有大于第一厚度的第二厚度。第二上互连件具有大于第一厚度的第三厚度。第三厚度是第一厚度的2倍至100倍。第二上互连件包括与第二上插塞的材料不同的材料。

Description

包括厚金属层的半导体器件
本申请要求于2019年10月2日在韩国知识产权局(KIPO)提交的第10-2019-0122357号韩国专利申请的优先权和权益，所述韩国专利申请的公开内容通过引用全部包含于此。
技术领域
与示例实施例一致的器件和方法涉及具有厚金属层的半导体器件和形成该半导体器件的方法。
背景技术
半导体器件具有各种互连件。当减小互连件的截面积以增大集成密度时，引起诸如互连电阻增加和信号传输速率降低的问题。用于互连件的材料和形成互连件的方法显著地影响半导体器件的批量生产效率和可靠性。
发明内容
发明构思的示例实施例旨在提供具有改善的电流驱动能力和高信号传输速率的半导体器件以及形成该半导体器件的方法。
根据示例实施例，公开涉及一种半导体器件，所述半导体器件包括：层间绝缘层，设置在基底上；多个中间互连件，设置在层间绝缘层中；多个中间插塞，设置在层间绝缘层中并且设置在所述多个中间互连件之间；上绝缘层，设置在层间绝缘层上；第一上插塞，设置在上绝缘层中并且连接到多个中间互连件中的一个中间互连件，所述一个中间互连件具有第一厚度；第一上互连件，在第一上插塞上设置在上绝缘层中并且具有第二厚度，其中，第二厚度大于第一厚度；第二上插塞，在第一上互连件上设置在上绝缘层中；第二上互连件，在第二上插塞上设置在上绝缘层中并且具有第三厚度，其中，第三厚度大于第一厚度；以及开口，被构造为穿过上绝缘层以使第二上互连件的部分暴露，其中，第三厚度在第一厚度的2倍至100倍的范围内，并且其中，第二上互连件包括与第二上插塞的材料不同的材料。
根据示例实施例，公开涉及一种半导体器件，所述半导体器件包括顺序地堆叠在印刷电路板(PCB)上的多个半导体芯片，其中，多个半导体芯片中的至少一个包括：下绝缘层，设置在基底上；存储器单元，设置在下绝缘层中；层间绝缘层，设置在下绝缘层上；多个中间互连件，设置在层间绝缘层中；多个中间插塞，设置在层间绝缘层中并且设置在多个中间互连件之间；上绝缘层，设置在层间绝缘层上；第一上插塞，设置在上绝缘层中并且连接到多个中间互连件中的一个中间互连件，所述一个中间互连件具有第一厚度；第一上互连件，在第一上插塞上设置在上绝缘层中并且具有第二厚度，其中，第二厚度大于第一厚度；第二上插塞，设置在上绝缘层中并且设置在第一上互连件上；第二上互连件，在第二上插塞上设置在上绝缘层中并且具有第三厚度，其中，第三厚度大于第一厚度；凸块，设置在上绝缘层上，凸块延伸到上绝缘层中并且接触第二上互连件；以及贯穿电极，延伸到基底中并且连接到多个中间互连件，其中，第三厚度在第一厚度的2倍至100倍的范围内，并且其中，第二上互连件包括与第二上插塞的材料不同的材料。
根据示例实施例，公开涉及一种半导体器件，所述半导体器件包括：中继基底；微处理器，设置在中继基底上；缓冲芯片，设置在中继基底上；以及多个半导体芯片，顺序地堆叠在缓冲芯片上，其中，多个半导体芯片中的至少一个包括：下绝缘层，设置在基底上；存储器单元，设置在下绝缘层中；层间绝缘层，设置在下绝缘层上；多个中间互连件，设置在层间绝缘层中；多个中间插塞，设置在层间绝缘层中并且设置在多个中间互连件之间；上绝缘层，设置在层间绝缘层上；第一上插塞，设置在上绝缘层中并且连接到多个中间互连件中的一个中间互连件，所述一个中间互连件具有第一厚度；第一上互连件，在第一上插塞上设置在上绝缘层中并且具有第二厚度，其中，第二厚度大于第一厚度；第二上插塞，设置在上绝缘层中并且设置在第一上互连件上；第二上互连件，在第二上插塞上设置在上绝缘层中并且具有第三厚度，其中，第三厚度大于第一厚度；凸块，设置在上绝缘层上，凸块延伸到上绝缘层中并且接触第二上互连件；以及贯穿电极，延伸到基底中并且连接到多个中间互连件，其中，第三厚度在第一厚度的2倍至100倍的范围内，并且其中，第二上互连件包括与第二上插塞的材料不同的材料。
附图说明
图1是示出根据发明构思的示例实施例的半导体器件的剖视图。
图2至图4是示出图1的部分的放大视图。
图5至图8是示出根据发明构思的示例实施例的半导体器件的剖视图。
图9和图10是示出图5的一部分的放大视图。
图11至图13是示出根据发明构思的示例实施例的半导体器件的剖视图。
图14和图15是示出根据发明构思的示例实施例的半导体器件的剖视图。
图16是示出图14和图15的部分的放大视图。
图17至图21是用于示出形成根据发明构思的示例实施例的半导体器件的方法的剖视图。
具体实施方式
现在将在下文中参照附图更充分地描述本公开，在附图中示出了各种实施例。在附图中，同样的附图标记始终指同样的元件。
图1是示出根据发明构思的示例实施例的半导体器件的剖视图。图2和图3是示出图1的部分II的放大视图，图4是示出图1的部分MC的放大视图。根据发明构思的实施例的半导体器件可以包括厚顶部金属(TTM)。
参照图1、根据发明构思的实施例的半导体器件可以包括基底21、下绝缘层30、存储器单元MC、接触间隔件38、贯穿电极39、层间绝缘层40、多个中间互连件45、多个中间插塞47、上绝缘层50、多个第一上插塞61、多个第一上互连件65、多个第二上插塞71、多个第二上互连件75、开口55W、基底绝缘层91和突出电极93。上绝缘层50可以包括第一组53和第二组55。
在示例实施例中，多个第二上互连件75可以是厚顶部金属(TTM)。存储器单元MC可以包括动态随机存取存储器(DRAM)单元、静态RAM(SRAM)单元、闪存单元、磁阻RAM(MRAM)单元、相变RAM(PRAM)单元、铁电RAM(FeRAM)单元、电阻RAM(RRAM)单元或它们的组合。例如，存储器单元MC可以包括DRAM单元。
基底21可以包括诸如单晶硅晶圆的半导体基底。下绝缘层30可以覆盖基底21的一个表面。例如，下绝缘层30的下表面可以接触基底21的上表面。基底绝缘层91可以设置在基底21的另一表面上。例如，基底绝缘层91的上表面可以接触基底21的下表面。基底21可以设置在下绝缘层30与基底绝缘层91之间。存储器单元MC可以设置在下绝缘层30中。存储器单元MC可以电连接到多个中间互连件45中的至少对应的一个。
层间绝缘层40可以设置在下绝缘层30上。多个中间互连件45和多个中间插塞47可以设置在层间绝缘层40中。多个中间插塞47可以设置在多个中间互连件45之间，电连接多个中间互连件45。贯穿电极39可以延伸到基底21、下绝缘层30和基底绝缘层91中。例如，贯穿电极39的上表面可以与下绝缘层30的上表面共面，并且贯穿电极39的下表面可以与基底绝缘层91的下表面共面。突出电极93可以设置在基底绝缘层91上。例如，突出电极93的上表面可以接触基底绝缘层91的下表面。贯穿电极39可以穿过基底21、下绝缘层30和基底绝缘层91，并且可以与多个中间互连件45中选择的一个以及突出电极93接触。贯穿电极39可以电连接到多个中间互连件45。接触间隔件38可以设置在贯穿电极39与基底21之间。接触间隔件38的上表面可以与下绝缘层30的上表面共面，并且接触间隔件38的下表面可以与基底21的下表面共面。贯穿电极39的直径可以在约1μm至约20μm的范围内。
贯穿电极39、多个中间互连件45、多个中间插塞47和突出电极93中的每个可以包括金属、金属氮化物、金属氧化物、金属硅化物、导电碳或它们的组合。贯穿电极39、多个中间互连件45、多个中间插塞47和突出电极93中的每个可以包括铜(Cu)、钨(W)、铝(Al)、镍(Ni)、锡(Sn)、钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)、氮化钨(WN)或它们的组合。例如，贯穿电极39、多个中间互连件45和多个中间插塞47中的每个可以包括Cu层。
上绝缘层50的第一组53可以设置在层间绝缘层40上。多个第一上插塞61、多个第一上互连件65和多个第二上插塞71可以设置在第一组53中。多个第一上插塞61可以与多个中间互连件45中的对应的一个接触。多个第一上互连件65可以设置在多个第一上插塞61上。例如，多个第一上互连件65的下表面可以接触多个第一上插塞61的上表面。多个第二上插塞71可以设置在多个第一上互连件65上。例如，多个第二上插塞71的下表面可以接触多个第一上互连件65的上表面。第二组55可以设置在上绝缘层50的第一组53上。例如，第二组55的下表面可以接触第一组53的上表面。多个第二上互连件75可以设置在第二组55中。多个第二上互连件75可以与多个第二上插塞71接触。开口55W可以穿过上绝缘层50的第二组55。多个第二上互连件75中的至少一些可以在开口55W的底部处被暴露。
多个第一上插塞61、多个第一上互连件65、多个第二上插塞71和多个第二上互连件75中的每个可以包括金属、金属氮化物、金属氧化物、金属硅化物、导电碳或它们的组合。多个第一上插塞61、多个第一上互连件65、多个第二上插塞71和多个第二上互连件75中的每个可以包括W、Al、Ni、Sn、Ti、TiN、Ta、TaN、WN、Cu或它们的组合。
在示例实施例中，多个第一上互连件65和多个第二上互连件75中的每个可以包括与多个中间互连件45和多个中间插塞47的材料不同的材料。多个第一上互连件65和多个第二上互连件75中的每个可以包括与多个第一上插塞61和多个第二上插塞71的材料不同的材料。例如，多个第一上互连件65和多个第二上互连件75中的每个可以包括Al层，多个第一上插塞61和多个第二上插塞71中的每个可以包括W层。
下绝缘层30、接触间隔件38、层间绝缘层40、上绝缘层50和基底绝缘层91中的每个可以包括氧化硅、氮化硅、氮氧化硅、低k电介质、高k电介质或它们的组合。下绝缘层30、接触间隔件38、层间绝缘层40、上绝缘层50和基底绝缘层91中的每个可以包括单层或多层结构。
参照图1和图2，多个中间互连件45可以包括第一中间互连件45A、多个第二中间互连件45B、多个第三中间互连件45C和多个第四中间互连件45D。多个中间插塞47可以包括多个第一中间插塞47A、多个第二中间插塞47B和多个第三中间插塞47C。
上绝缘层50可以包括第一上绝缘层53A、第二上绝缘层53B、第三上绝缘层53C、第四上绝缘层53D、第五上绝缘层53E、第六上绝缘层55A和第七上绝缘层55B。第一组53可以包括第一上绝缘层53A、第二上绝缘层53B、第三上绝缘层53C、第四上绝缘层53D和第五上绝缘层53E。第二组55可以包括第六上绝缘层55A和第七上绝缘层55B。
多个第一上插塞61中的每个可以包括第一阻挡层61A和第一导电层61B。多个第一上互连件65中的每个可以包括第二阻挡层65A、第二导电层65B和第三阻挡层65C。多个第二上插塞71中的每个可以包括第四阻挡层71A和第三导电层71B。多个第二上互连件75中的每个可以包括第五阻挡层75A、第四导电层75B和第六阻挡层75C。
多个第二中间互连件45B可以设置在第一中间互连件45A上。第一中间互连件45A可以与贯穿电极39直接接触。多个第一中间插塞47A可以设置在多个第二中间互连件45B与第一中间互连件45A之间。多个第一中间插塞47A可以与多个第二中间互连件45B和第一中间互连件45A接触。多个第三中间互连件45C可以设置在多个第二中间互连件45B上。多个第二中间插塞47B可以设置在多个第三中间互连件45C与多个第二中间互连件45B之间。多个第二中间插塞47B可以与多个第三中间互连件45C和多个第二中间互连件45B接触。多个第四中间互连件45D可以设置在多个第三中间互连件45C上。多个第三中间插塞47C可以设置在多个第四中间互连件45D与多个第三中间互连件45C之间。多个第三中间插塞47C可以与多个第四中间互连件45D和多个第三中间互连件45C接触。
在示例实施例中，第一中间互连件45A可以对应于多个中间互连件45中的最下面的层。多个第四中间互连件45D可以对应于多个中间互连件45中的最上面的层。多个第四中间互连件45D中的每个可以具有第一厚度T1。第一中间互连件45A、多个第二中间互连件45B中的每个和多个第三中间互连件45C中的每个可以具有与多个第四中间互连件45D中的每个的厚度基本相同的厚度。如这里使用的，术语“厚度”和“高度”可以指在垂直于基底21的顶表面的方向上测量的厚度或高度。当提及取向、布局、位置、形状、尺寸、量或其它度量时，如这里使用的诸如“相同”、“相等”、“平面”或“共面”的术语不必需意味完全相同的取向、布局、位置、形状、尺寸、量或其它度量，而是意图包括在例如由于制造工艺而可能发生的可接受变化内的几乎相同的取向、布局、位置、形状、尺寸、量或其它度量。除非上下文或其它陈述另外指出，否则这里可以使用术语“基本(基本上)”来强调该含义。例如，描述为“基本相同”、“基本相等”或“基本平面”的术语可以是完全相同、完全相等或完全平面，或者可以是在例如由于制造工艺而可能发生的可接受的变化内的相同、相等或平面。
在示例实施例中，多个第一中间插塞47A可以对应于多个中间插塞47中的最下面的层。多个第三中间插塞47C可以对应于多个中间插塞47中的最上面的层。多个第三中间插塞47C中的每个可以具有第一高度H1。第一高度H1可以基本等于多个第三中间互连件45C与多个第四中间互连件45D之间的间隙。多个第一中间插塞47A和多个第二中间插塞47B中的每个可以具有与多个第三中间插塞47C中的每个的高度基本相同的高度。
第四上绝缘层53D和第五上绝缘层53E可以顺序地堆叠在层间绝缘层40上。在示例实施例中，第四上绝缘层53D可以对应于蚀刻停止层。第四上绝缘层53D可以包括相对于第五上绝缘层53E具有蚀刻选择性的材料。第五上绝缘层53E可以包括氧化硅或低k电介质，第四上绝缘层53D可以包括氮化硅、氮氧化硅、硼氮化硅(SiBN)或碳氮化硅(SiCN)。
多个第一上插塞61中的每个可以延伸到第五上绝缘层53E和第四上绝缘层53D中。例如，多个第一上插塞61的上表面可以与第五上绝缘层53E的上表面共面，并且多个第一上插塞61的下表面可以与第四上绝缘层53D的下表面共面。多个第一上互连件65可以设置在第五上绝缘层53E上。例如，多个第一上互连件65的下表面可以接触第五上绝缘层53E的上表面。多个第一上插塞61中的每个可以穿过第五上绝缘层53E和第四上绝缘层53D，并且与多个第四中间互连件45D中的对应的一个和多个第一上互连件65中的对应的一个接触。
在示例实施例中，第一阻挡层61A可以围绕第一导电层61B的侧表面和底部。第一导电层61B可以包括W层。第一阻挡层61A可以包括WN层。第二导电层65B可以设置在第二阻挡层65A上。例如，第二导电层65B的下表面可以接触第二阻挡层65A的上表面。第三阻挡层65C可以设置在第二导电层65B上。例如，第三阻挡层65C的下表面可以接触第二导电层65B的上表面。第二导电层65B可以设置在第二阻挡层65A与第三阻挡层65C之间。第二导电层65B可以包括与多个中间互连件45、多个中间插塞47和第一导电层61B的材料不同的材料。第二导电层65B可以包括Al层。第二阻挡层65A和第三阻挡层65C中的每个可以包括Ti、TiN、Ta、TaN、WN或它们的组合。可以省略第二阻挡层65A和第三阻挡层65C中的一个或全部。
在示例实施例中，多个第一上互连件65中的每个可以具有第二厚度T2。第二厚度T2可以大于第一厚度T1。多个第一上插塞61中的每个可以具有第二高度H2。第二高度H2可以大于第一高度H1。第二高度H2可以基本等于多个第四中间互连件45D与多个第一上互连件65之间的间隙。
第一上绝缘层53A可以设置在第五上绝缘层53E上。例如，第一上绝缘层53A的下表面可以接触第五上绝缘层53E的上表面。第一上绝缘层53A可以覆盖多个第一上互连件65的上表面和侧表面。第二上绝缘层53B可以设置在第一上绝缘层53A上。例如，第二上绝缘层53B的下表面可以接触第一上绝缘层53A的上表面。第二上绝缘层53B可以对应于覆盖层。第二上绝缘层53B可以在退火工艺期间控制下层的除气(outgassing)。第三上绝缘层53C可以设置在第二上绝缘层53B上。例如，第三上绝缘层53C的下表面可以接触第二上绝缘层53B的上表面。
在示例实施例中，第一上绝缘层53A可以包括诸如高密度等离子体(HDP)氧化物的氧化物层。第二上绝缘层53B可以包括与第一上绝缘层53A的材料不同的材料。第二上绝缘层53B可以包括诸如氮化硅的氮化物层。第三上绝缘层53C可以包括与第二上绝缘层53B的材料不同的材料。第三上绝缘层53C可以包括使用正硅酸四乙酯(TEOS)或氟化正硅酸四乙酯(FTEOS)形成的氧化物层。
多个第二上插塞71中的每个可以延伸到第三上绝缘层53C、第二上绝缘层53B和第一上绝缘层53A中。多个第二上互连件75中的每个可以设置在第三上绝缘层53C上。例如，多个第二上互连件75的下表面可以接触第三上绝缘层53C的上表面。多个第二上插塞71中的每个可以穿过第三上绝缘层53C、第二上绝缘层53B和第一上绝缘层53A，并且与多个第一上互连件65中的对应的一个和多个第二上互连件75中的对应的一个接触。
在示例实施例中，第四阻挡层71A可以围绕第三导电层71B的侧表面和底部。第三导电层71B可以包括W层。第四阻挡层71A可以包括WN层。第四导电层75B可以设置在第五阻挡层75A上。例如，第四导电层75B的下表面可以接触第五阻挡层75A的上表面。第六阻挡层75C可以设置在第四导电层75B上。例如，第六阻挡层75C的下表面可以接触第四导电层75B的上表面。第四导电层75B可以设置在第五阻挡层75A与第六阻挡层75C之间。第四导电层75B可以包括与多个中间互连件45、多个中间插塞47和第三导电层71B的材料不同的材料。第四导电层75B可以包括Al层。第五阻挡层75A和第六阻挡层75C中的每个可以包括Ti、TiN、Ta、TaN、WN或它们的组合。可以省略第五阻挡层75A和第六阻挡层75C中的一个或全部。例如，可以省略第五阻挡层75A。在这样的实施例中，第四导电层75B的下表面可以接触第三上绝缘层53C的上表面。
在示例实施例中，多个第二上互连件75中的每个可以具有第三厚度T3。第三厚度T3可以大于第一厚度T1。第三厚度T3可以在第一厚度T1的2倍至100倍的范围内。第三厚度T3可以大于或等于第二厚度T2。第三厚度T3可以在约2μm至约10μm的范围内。例如，第三厚度T3可以是约2.5μm。
在示例实施例中，多个第二上插塞71中的每个可以具有第三高度H3。第三高度H3可以基本等于多个第一上互连件65与多个第二上互连件75之间的间隙。第三高度H3可以大于第一高度H1。第三高度H3可以大于或等于第二高度H2。第三高度H3可以在约0.5μm至约5μm的范围内。例如，第三高度H3可以是约1.7μm。
第六上绝缘层55A可以设置在第三上绝缘层53C上。例如，第六上绝缘层55A的下表面可以接触第三上绝缘层53C的上表面。第六上绝缘层55A可以覆盖多个第二上互连件75的侧表面和上表面。第七上绝缘层55B可以设置在第六上绝缘层55A上。开口55W可以穿过第七上绝缘层55B和第六上绝缘层55A。多个第二上互连件75的部分可以在开口55W的底部处被暴露。第七上绝缘层55B可以包括与第六上绝缘层55A的材料不同的材料。例如，第七上绝缘层55B可以包括诸如氮化硅的氮化物，第六上绝缘层55A可以包括诸如氧化硅的氧化物。
在示例性实施例中，第六上绝缘层55A可以包括诸如HDP氧化物的氧化物层。第七上绝缘层55B可以包括使用TEOS或FTEOS形成的氧化物层。在示例性实施例中，第六上绝缘层55A可以包括使用TEOS或FTEOS形成的氧化物层。第七上绝缘层55B可以包括诸如HDP氧化物的氧化物层。
互连电阻可以由于多个第一上插塞61、多个第一上互连件65、多个第二上插塞71和多个第二上互连件75的构造而减小。第一上绝缘层53A、第二上绝缘层53B和第三上绝缘层53C的构造可以改善层间绝缘特性。第二上绝缘层53B可以改善设置在下绝缘层30和/或层间绝缘层40中的多个有源/无源元件的电特性和可靠性。
参照图1和图3，第二上互连件75可以包括第四导电层75B和第六阻挡层75C。第四导电层75B可以与多个第二上插塞71接触。例如，第四导电层75B的下表面可以接触多个第二上插塞71的上表面。
参照图1和图4，在示例实施例中，存储器单元MC可以包括DRAM单元。存储器单元MC可以包括基底21、第一下绝缘层30A、第二下绝缘层30B、器件隔离层23、栅极介电层24、多个栅电极25、栅极覆盖层26、多个源区/漏区27、位插塞28、位线29、多个掩埋接触插塞32、多个接合垫33、多个第一电极35、电容器介电层36以及第二电极37。下绝缘层30可以包括第一下绝缘层30A和第二下绝缘层30B。
器件隔离层23可以使用浅沟槽隔离(STI)技术形成在基底21中。器件隔离层23的上表面可以与基底21的上表面共面。多个栅电极25中的每个可以设置在比基底21的上端低的水平处。例如，多个栅电极25的上表面可以处于比基底21的上表面低的水平。栅极介电层24可以围绕多个栅电极25的侧表面和底部。栅极介电层24可以置于多个栅电极25与基底21之间。栅极覆盖层26可以设置在多个栅电极25上。多个源区/漏区27可以与多个栅电极25相邻地设置在基底21中。
栅极介电层24、多个栅电极25和多个源区/漏区27可以构成多个单元晶体管。多个单元晶体管中的每个可以对应于凹陷沟道晶体管。在示例实施例中，多个单元晶体管中的每个可以包括鳍式场效应晶体管(finFET)、多桥沟道(MBC)晶体管、纳米线晶体管、垂直晶体管、凹陷沟道晶体管、三维(3D)晶体管、平面晶体管或它们的组合。
第一下绝缘层30A可以覆盖器件隔离层23、栅极覆盖层26和多个源区/漏区27。位插塞28和位线29可以设置在第一下绝缘层30A中。位线29可以设置在位插塞28上。位插塞28可以穿过第一下绝缘层30A并且与多个源区/漏区27中的对应的一个接触。多个掩埋接触插塞32和多个接合垫33可以设置在第一下绝缘层30A中。多个接合垫33中的每个可以与多个掩埋接触插塞32中的对应的一个的上表面接触。多个接合垫33的上表面可以与第一下绝缘层30A的上表面共面。多个掩埋接触插塞32中的每个可以与多个源区/漏区27中的对应的一个接触。
多个第一电极35可以设置在多个接合垫33上。例如，多个第一电极35的下表面可以接触多个接合垫33的上表面。电容器介电层36可以设置在多个第一电极35上。第二电极37可以设置在电容器介电层36上。多个第一电极35、电容器介电层36和第二电极37可以构成多个单元电容器。多个第一电极35中的每个可以对应于单元电容器的下电极。多个第一电极35中的每个可以被称为存储电极。第二电极37可以对应于单元电容器的上电极。第二电极37可以被称为板电极。第二下绝缘层30B可以覆盖第二电极37。
多个单元电容器中的每个可以包括各种3D电容器。例如，多个第一电极35中的每个可以包括柱结构、圆柱结构(例如，单柱存储(OCS)结构)或它们的组合。
栅极介电层24和电容器介电层36中的每个可以包括氧化硅、氮化硅、氮氧化硅、高k电介质或它们的组合。多个栅电极25、位插塞28、位线29、多个掩埋接触插塞32、多个接合垫33、多个第一电极35以及第二电极37中的每个可以包括金属、金属氮化物、金属氧化物、金属硅化物、导电碳、多晶硅或它们的组合。器件隔离层23、栅极覆盖层26、第一下绝缘层30A和第二下绝缘层30B中的每个可以包括氧化硅、氮化硅、氮氧化硅、低k电介质、高k电介质或它们的组合。
图5至图8是用于描述根据发明构思的实施例的半导体器件的剖视图。图9和图10是示出图5的一部分的放大视图。
参照图5、根据发明构思的示例实施例的半导体器件可以包括基底21、下绝缘层30、层间绝缘层40、多个中间互连件45、多个中间插塞47、上绝缘层50、第一上插塞61、第一上互连件65、第二上插塞71、第二上互连件75和开口55W。
在示例实施例中，多个中间互连件45和多个中间插塞47中的每个可以使用镶嵌工艺形成。多个中间互连件45和多个中间插塞47中的每个可以呈现上横向宽度大于其下横向宽度的倒梯形形状。第一上互连件65和第二上互连件75中的每个可以使用图案化工艺形成。第一上互连件65和第二上互连件75中的每个可以呈现上横向宽度小于其下横向宽度的梯形形状。第一上插塞61和第二上插塞71中的每个可以呈现上横向宽度大于其下横向宽度的倒梯形形状。
参照图6，测试开口155W可以包括第一开口155W1和第二开口155W2。第二开口155W2可以与第一开口155W1的底部连通。第一上互连件65可以在第二开口155W2的底部处被暴露。第一开口155W1可以穿过第七上绝缘层55B和第六上绝缘层55A。第二开口155W2可以穿过第三上绝缘层53C、第二上绝缘层53B和第一上绝缘层53A。
参照图7，第一上绝缘层53A、第二上绝缘层53B、第三上绝缘层53C、第六上绝缘层55A和第七上绝缘层55B可以顺序地堆叠在第一上互连件65上。第一上绝缘层53A、第二上绝缘层53B、第三上绝缘层53C、第六上绝缘层55A和第七上绝缘层55B可以完全覆盖第一上互连件65。
参照图8，第六上绝缘层55A和第七上绝缘层55B可以顺序地堆叠在第二上互连件75上。第六上绝缘层55A和第七上绝缘层55B可以完全覆盖第二上互连件75。
参照图9，第三中间插塞47C可以包括第七阻挡层BM1和第五导电层CM1。第七阻挡层BM1可以围绕第五导电层CM1的侧表面和底部。第四中间互连件45D可以包括第八阻挡层BM2和第六导电层CM2。第八阻挡层BM2可以围绕第六导电层CM2的侧表面和底部。第八阻挡层BM2可以置于第五导电层CM1与第六导电层CM2之间。例如，第八阻挡层BM2的上表面可以接触第六导电层CM2的下表面，并且第八阻挡层BM2的下表面可以接触第五导电层CM1的上表面。第五导电层CM1和第六导电层CM2中的每个可以包括Cu层。第七阻挡层BM1和第八阻挡层BM2中的每个可以包括Ti、TiN、Ta、TaN或它们的组合。第一中间插塞47A和第二中间插塞47B中的每个可以呈现与第三中间插塞47C的构造类似的构造。例如，第一中间插塞47A和第二中间插塞47B中的每个可以包括导电层以及围绕导电层的侧表面和底表面的阻挡层。第一中间互连件45A、第二中间互连件45B和第三中间互连件45C中的每个可以呈现与第四中间互连件45D的构造类似的构造。例如，第一中间互连件45A、第二中间互连件45B和第三中间互连件45C中的每个可以包括导电层以及围绕导电层的侧表面和底表面的阻挡层。
参照图10，第三中间插塞47C可以包括第九阻挡层BM和第五导电层CM1。第四中间互连件45D可以包括第九阻挡层BM和第六导电层CM2。第五导电层CM1可以与第六导电层CM2一体地形成。第六导电层CM2与第五导电层CM1在材料上可以是连续的。第五导电层CM1和第六导电层CM2中的每个可以包括Cu层。第九阻挡层BM可以围绕第五导电层CM1和第六导电层CM2的底表面和侧表面。第九阻挡层BM可以包括Ti、TiN、Ta、TaN或它们的组合。第一中间插塞47A和第二中间插塞47B中的每个可以呈现与第三中间插塞47C的构造类似的构造。例如，第一中间插塞47A和第二中间插塞47B中的每个可以包括导电层以及围绕导电层的底表面和侧表面的阻挡层。第一中间互连件45A、第二中间互连件45B和第三中间互连件45C中的每个可以呈现与第四中间互连件45D的构造类似的构造。例如，第二中间互连件45B和第三中间互连件45C中的每个可以包括分别与第一中间插塞47A和第二中间插塞47B的导电层在材料上连续的导电层以及围绕导电层的底表面和侧表面的阻挡层。第一中间互连件45A可以包括导电层以及围绕导电层的底表面和侧表面的阻挡层。
图11至图13是用于描述根据发明构思的示例实施例的半导体器件的剖视图。
参照图11，根据发明构思的示例实施例的半导体器件可以包括基底21、下绝缘层30、存储器单元MC、接触间隔件38、贯穿电极39、层间绝缘层40、多个中间互连件45、多个中间插塞47、上绝缘层50、多个第一上插塞61、多个第一上互连件65、多个第二上插塞71、多个第二上互连件75、开口55W、第一凸块89、基底绝缘层91以及突出电极93。第一凸块89可以包括柱结构85和焊料87。柱结构85可以包括阻挡层81、种子层82和柱83。
第一凸块89可以具有约1μm至约50μm的直径。第一凸块89可以具有约1μm至约70μm的高度。在实施例中，第一凸块89可以具有约10μm至约50μm的直径。在实施例中，第一凸块89可以具有约1μm至约40μm的直径。在实施例中，第一凸块89可以具有约10μm至约70μm的高度。在实施例中，第一凸块89可以具有约1μm至约60μm的高度。
柱结构85可以设置在上绝缘层50上。例如，柱结构85的底表面可以接触上绝缘层50的上表面。柱结构85可以延伸到上绝缘层50的第二组55中。例如，柱结构85可以在第二组55的上表面下方延伸。柱结构85可以穿过第二组55并且可以与多个第二上互连件75中的对应的一个的上表面接触。阻挡层81可以包括Ti、TiN、Ta、TaN或它们的组合。种子层82可以设置在阻挡层81上。种子层82可以包括Cu。柱83可以设置在种子层82上。例如，柱83的下表面可以接触种子层82的上表面，并且种子层82的下表面可以接触阻挡层81的上表面。
柱83可以包括镍(Ni)、铜(Cu)、铝(Al)、银(Ag)、铂(Pt)、钌(Ru)、锡(Sn)、金(Au)、钨(W)、氮化钨(WN)、钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)或它们的组合。例如，柱83可以包括Ni层。
焊料87可以设置在柱结构85上。焊料87可以包括Sn、Ag、Cu、Ni、Au或它们的组合。例如，焊料87可以包括Sn-Ag-Cu层。界面金属层可以进一步形成在柱结构85与焊料87之间，但为了简洁将省略其描述。
参照图12，根据发明构思的示例实施例的半导体器件可以包括基底21、下绝缘层30、接触间隔件38、贯穿电极39、层间绝缘层40、多个中间互连件45、多个中间插塞47、上绝缘层50、多个第一上插塞61、多个第一上互连件65、多个第二上插塞71、多个第二上互连件75、开口55W、第一凸块89、基底绝缘层91和突出电极93。
参照图13，根据发明构思的示例实施例的半导体器件可以包括基底21、下绝缘层30、层间绝缘层40、多个中间互连件45、多个中间插塞47、上绝缘层50、多个第一上插塞61、多个第一上互连件65、多个第二上插塞71、多个第二上互连件75、开口55W和第一凸块89。
图14和图15是用于描述根据发明构思的示例实施例的半导体器件的剖视图。图16是示出图14和图15的部分III的放大视图。根据发明构思的实施例的半导体器件可以包括混合存储器立方体(HMC)、高带宽存储器(HBM)、双数据速率第五代(DDR5)DRAM或它们的组合。
参照图14，根据发明构思的示例实施例的半导体器件可以包括印刷电路板(PCB)PC、中继基底IP、多个半导体芯片CP、BD和MD1至MD4，多个凸块89、489、589和689、粘合层95以及包封剂96。多个半导体芯片CP、BD和MD1至MD4可以包括微处理器CP、缓冲芯片BD和多个存储器芯片MD1至MD4。在示例实施例中，多个存储器芯片MD1至MD4可以顺序地且垂直地堆叠在缓冲芯片BD上。多个存储器芯片MD1至MD4可以包括与诸如三个、四个、七个、八个、十一个、十二个、十五个、十六个、十九个或更多个的数目的各种组合对应的存储器芯片。
多个存储器芯片MD1至MD4可以包括第一存储器芯片MD1、第二存储器芯片MD2、第三存储器芯片MD3和第四存储器芯片MD4。多个存储器芯片MD1至MD4中的至少一些可以包括多个贯穿电极39。多个凸块89、489、589和689可以包括多个第一凸块89、多个第二凸块489、多个第三凸块589和多个第四凸块689。
PCB PC可以包括刚性PCB、柔性PCB或刚性-柔性PCB。PCB PC可以包括多层电路板。PCB PC可以对应于封装基底或主板。多个第四凸块689可以设置在PCB PC的下表面上。中继基底IP可以设置在PCB PC上。多个第三凸块589可以设置在PCB PC与中继基底IP之间。
多个半导体芯片CP、BD和MD1至MD4可以设置在中继基底IP上。中继基底IP可以包括诸如硅中介层的半导体基底。在示例实施例中，微处理器CP和缓冲芯片BD可以设置在中继基底IP上。多个第二凸块489可以设置在微处理器CP与中继基底IP之间以及缓冲芯片BD与中继基底IP之间。微处理器CP可以包括各种处理器，诸如图形处理单元(GPU)或应用处理器(AP)。缓冲芯片BD可以包括诸如存储器控制器的各种元件。缓冲芯片BD可以经由中继基底IP和多个第二凸块489连接到微处理器CP。
多个存储器芯片MD1至MD4可以顺序地堆叠在缓冲芯片BD上。多个存储器芯片MD1至MD4中的每个可以包括与参照图1至图13描述的多个组件类似的多个组件。例如，多个存储器芯片MD1至MD4中的每个可以对应于参照图1至图13示出的半导体器件。在一些实施例中，多个存储器芯片MD1至MD4中的每个可以包括多个第一凸块89。在示例实施例中，粘合层95可以设置在多个存储器芯片MD1至MD4之间以及第一存储器芯片MD1与缓冲芯片BD之间。粘合层95可以包括非导电膜(NCF)。
多个第一凸块89可以设置在多个存储器芯片MD1至MD4之间以及第一存储器芯片MD1与缓冲芯片BD之间。多个第一凸块89可以延伸到粘合层95中。多个第一凸块89可以穿过粘合层95。多个存储器芯片MD1至MD4可以经由多个第一凸块89和多个贯穿电极39连接到缓冲芯片BD。包封剂96可以设置在缓冲芯片BD上以覆盖多个存储器芯片MD1至MD4。包封剂96可以包括环氧模塑料(EMC)。
在示例性实施例中，缓冲芯片BD可以表示主芯片。多个存储器芯片MD1至MD4中的每个可以表示从属芯片。在示例性实施例中，第一存储器芯片MD1可以表示主芯片。第二存储器芯片MD2、第三存储器芯片MD3和第四存储器芯片MD4中的每个可以表示从属芯片。
参照图15，根据发明构思的示例实施例的半导体器件可以包括顺序地堆叠在封装基底PC2上的多个存储器芯片MD1至MD4。
封装基底PC2可以包括诸如刚性PCB、柔性PCB或刚性-柔性PCB的PCB。多个存储器芯片MD1至MD4可以包括第一存储器芯片MD1、第二存储器芯片MD2、第三存储器芯片MD3和第四存储器芯片MD4。粘合层95可以设置在多个存储器芯片MD1至MD4之间以及第一存储器芯片MD1与封装基底PC2之间。粘合层95可以包括NCF。
多个存储器芯片MD1至MD4可以经由多个第一凸块89和多个贯穿电极39连接到封装基底PC2。包封剂96可以设置在封装基底PC2上以覆盖多个存储器芯片MD1至MD4。包封剂96可以包括EMC。多个第二凸块489可以设置在封装基底PC2的下表面上。在示例性实施例中，第一存储器芯片MD1可以表示主芯片。第二存储器芯片MD2、第三存储器芯片MD3和第四存储器芯片MD4中的每个可以表示从属芯片。
参照图16、第三存储器芯片MD3可以包括基底21、下绝缘层30、接触间隔件38、贯穿电极39、层间绝缘层40、多个中间互连件45、多个中间插塞47、上绝缘层50、多个第一上插塞61、多个第一上互连件65、多个第二上插塞71、多个第二上互连件75、第一凸块89、基底绝缘层91以及突出电极93。
第二存储器芯片MD2可以包括与第三存储器芯片MD3的构造类似的构造。第三存储器芯片MD3的焊料87可以粘附到第二存储器芯片MD2的突出电极93。第四存储器芯片MD4的焊料87可以粘附到第三存储器芯片MD3的突出电极93。
图17至图21是用于描述形成根据发明构思的实施例的半导体器件的方法的剖视图。
参照图17，可以在基底21上形成下绝缘层30。可以形成穿过下绝缘层30和基底21的接触间隔件38和贯穿电极39。可以在下绝缘层30上形成层间绝缘层40、多个中间互连件45和多个中间插塞47。
多个中间互连件45可以包括第一中间互连件45A、多个第二中间互连件45B、多个第三中间互连件45C和多个第四中间互连件45D。多个中间插塞47可以包括多个第一中间插塞47A、多个第二中间插塞47B和多个第三中间插塞47C。可以在层间绝缘层40中形成多个中间互连件45和多个中间插塞47。第一中间互连件45A可以与贯穿电极39接触。多个中间互连件45和多个中间插塞47的形成可以包括多个镶嵌工艺。
可以在层间绝缘层40上形成第一组53、多个第一上插塞61和多个第一上互连件65。第一组53可以包括第一上绝缘层53A、第二上绝缘层53B、第三上绝缘层53C、第四上绝缘层53D和第五上绝缘层53E。
可以在层间绝缘层40上顺序地堆叠第四上绝缘层53D和第五上绝缘层53E。多个第一上插塞61中的每个可以穿过第五上绝缘层53E和第四上绝缘层53D，并且可以与多个第四中间互连件45D中的对应的一个接触。多个第一上插塞61中的每个可以包括第一导电层61B以及被构造为围绕第一导电层61B的侧表面和底部的第一阻挡层61A。
可以在第五上绝缘层53E上形成多个第一上互连件65。多个第一上互连件65的形成可以包括图案化工艺。多个第一上互连件65中的至少一个可以与多个第一上插塞61接触。多个第一上互连件65中的每个可以包括第二阻挡层65A、设置在第二阻挡层65A上的第二导电层65B以及设置在第二导电层65B上的第三阻挡层65C。
可以在第五上绝缘层53E上形成第一上绝缘层53A。第一上绝缘层53A可以覆盖多个第一上互连件65的上表面和侧表面。可以在第一上绝缘层53A上形成第二上绝缘层53B。第二上绝缘层53B可以对应于覆盖层。第二上绝缘层53B可以在退火工艺期间控制下层的除气。可以在第二上绝缘层53B上形成第三上绝缘层53C。可以使第三上绝缘层53C的上表面平坦化。
在示例实施例中，第一上绝缘层53A可以包括诸如HDP氧化物的氧化物层。第二上绝缘层53B可以包括与第一上绝缘层53A的材料不同的材料。第二上绝缘层53B可以包括诸如氮化硅的氮化物层。第三上绝缘层53C可以包括使用TEOS或FTEOS形成的氧化物层。
参照图18，可以使用图案化工艺形成穿过第三上绝缘层53C、第二上绝缘层53B和第一上绝缘层53A的多个接触孔71H。多个第一上互连件65的上表面可以在多个接触孔71H的底部处被暴露。
参照图19，可以在多个接触孔71H的内部形成多个第二上插塞71。多个第二上插塞71中的每个可以包括第三导电层71B以及围绕第三导电层71B的侧表面和底部的第四阻挡层71A。
参照图20，可以在第三上绝缘层53C上形成第二上互连件75，并且第二上互连件75可以与多个第二上插塞71接触。第二上互连件75的形成可以包括图案化工艺。第二上互连件75可以包括第五阻挡层75A、设置在第五阻挡层75A上的第四导电层75B以及设置在第四导电层75B上的第六阻挡层75C。
参照图21，可以在第三上绝缘层53C上形成第六上绝缘层55A。第六上绝缘层55A可以覆盖第二上互连件75的侧表面和上表面。可以在第六上绝缘层55A上形成第七上绝缘层55B。可以形成穿过第七上绝缘层55B和第六上绝缘层55A的开口55W。第二上互连件75的一部分可以在开口55W的底部处被暴露。
根据发明构思的示例实施例，由于多个中间互连件、多个第一上插塞、多个第一上互连件、多个第二上插塞和多个第二上互连件的构造，可以显著地减小互连电阻。第一上绝缘层、第二上绝缘层和第三上绝缘层的构造可以改善层间绝缘特性。第二上绝缘层可以改善设置在下绝缘层和/或层间绝缘层中的多个有源/无源元件的电特性和可靠性。可以实现简化了工艺并具有优异的电流驱动能力和高信号传输速率的半导体器件。
尽管已经参照附图描述了发明构思的实施例，但本领域技术人员应该理解的是，在不脱离发明构思的范围并且不改变其必要特征的情况下，可以进行各种修改。因此，应该仅以描述性的含义而不是出于限制的目的来考虑以上描述的实施例。

Claims (20)

1.一种半导体器件，所述半导体器件包括：
层间绝缘层，设置在基底上；
多个中间互连件，设置在层间绝缘层中；
多个中间插塞，设置在层间绝缘层中并且设置在所述多个中间互连件之间；
上绝缘层，设置在层间绝缘层上；
第一上插塞，设置在上绝缘层中并且连接到所述多个中间互连件中的一个中间互连件，所述一个中间互连件具有第一厚度；
第一上互连件，在第一上插塞上设置在上绝缘层中并且具有第二厚度，其中，第二厚度大于第一厚度；
第二上插塞，在第一上互连件上设置在上绝缘层中；
第二上互连件，在第二上插塞上设置在上绝缘层中并且具有第三厚度，其中，第三厚度大于第一厚度；以及
开口，被构造为穿过上绝缘层以使第二上互连件的部分暴露，
其中，第三厚度在第一厚度的2倍至100倍的范围内，并且
其中，第二上互连件包括与第二上插塞的材料不同的材料。
2.根据权利要求1所述的半导体器件，其中，第三厚度大于或等于第二厚度。
3.根据权利要求1所述的半导体器件，其中，第三厚度在2μm至10μm的范围内。
4.根据权利要求1所述的半导体器件，
其中，所述多个中间插塞中的每个具有第一高度，
其中，第一上插塞具有大于第一高度的第二高度，并且
其中，第二上插塞具有大于第一高度的第三高度。
5.根据权利要求4所述的半导体器件，其中，第三高度大于或等于第二高度。
6.根据权利要求1所述的半导体器件，其中，第一上互连件和第二上互连件中的每个包括与所述多个中间互连件的材料层不同的材料层。
7.根据权利要求6所述的半导体器件，
其中，所述多个中间互连件包括铜层，并且
其中，第二上互连件包括铝层。
8.根据权利要求6所述的半导体器件，其中，第一上互连件包括铝层。
9.根据权利要求6所述的半导体器件，其中，第二上插塞包括钨层。
10.根据权利要求1至9中的任一项所述的半导体器件，其中，上绝缘层包括：
第一上绝缘层；
第二上绝缘层，设置在第一上绝缘层上并且包括与第一上绝缘层的材料不同的材料；以及
第三上绝缘层，设置在第二上绝缘层上并且包括与第二上绝缘层的材料不同的材料，
其中，第一上绝缘层、第二上绝缘层和第三上绝缘层设置在第一上互连件与第二上互连件之间，并且
其中，第二上插塞穿过第一上绝缘层、第二上绝缘层和第三上绝缘层并且接触第一上互连件和第二上互连件。
11.根据权利要求10所述的半导体器件，
其中，第一上绝缘层包括氧化物层，
其中，第二上绝缘层包括氮化物层，并且
其中，第三上绝缘层包括氧化物层。
12.根据权利要求1所述的半导体器件，所述半导体器件还包括贯穿电极，贯穿电极延伸到基底中并且连接到所述多个中间互连件。
13.根据权利要求12所述的半导体器件，其中，贯穿电极具有1μm至20μm的直径。
14.根据权利要求1所述的半导体器件，所述半导体器件还包括：
下绝缘层，设置在基底与层间绝缘层之间；以及
存储器单元，设置在下绝缘层中。
15.根据权利要求14所述的半导体器件，其中，存储器单元包括动态随机存取存储器单元、静态随机存取存储器单元、闪存单元、磁阻随机存取存储器单元、相变随机存取存储器单元、铁电随机存取存储器单元、电阻随机存取存储器单元或它们的组合。
16.一种半导体器件，所述半导体器件包括顺序地堆叠在印刷电路板上的多个半导体芯片，
其中，所述多个半导体芯片中的至少一个包括：
下绝缘层，设置在基底上；
存储器单元，设置在下绝缘层中；
层间绝缘层，设置在下绝缘层上；
多个中间互连件，设置在层间绝缘层中；
多个中间插塞，设置在层间绝缘层中并且设置在所述多个中间互连件之间；
上绝缘层，设置在层间绝缘层上；
第一上插塞，设置在上绝缘层中并且连接到所述多个中间互连件中的一个中间互连件，所述一个中间互连件具有第一厚度；
第一上互连件，在第一上插塞上设置在上绝缘层中并且具有第二厚度，其中，第二厚度大于第一厚度；
第二上插塞，设置在上绝缘层中并且设置在第一上互连件上；
第二上互连件，在第二上插塞上设置在上绝缘层中并且具有第三厚度，其中，第三厚度大于第一厚度；
凸块，设置在上绝缘层上，凸块延伸到上绝缘层中并且接触第二上互连件；以及
贯穿电极，延伸到基底中并且连接到所述多个中间互连件，
其中，第三厚度在第一厚度的2倍至100倍的范围内，并且
其中，第二上互连件包括与第二上插塞的材料不同的材料。
17.根据权利要求16所述的半导体器件，其中，凸块具有10μm到50μm的直径。
18.根据权利要求16所述的半导体器件，其中，第三厚度大于或等于第二厚度。
19.根据权利要求16所述的半导体器件，
其中，所述多个中间插塞中的每个具有第一高度，
其中，第一上插塞具有大于第一高度的第二高度，并且
其中，第二上插塞具有大于第一高度的第三高度。
20.一种半导体器件，所述半导体器件包括：
中继基底；
微处理器，设置在中继基底上；
缓冲芯片，设置在中继基底上；以及
多个半导体芯片，顺序地堆叠在缓冲芯片上，
其中，所述多个半导体芯片中的至少一个包括：
下绝缘层，设置在基底上；
存储器单元，设置在下绝缘层中；
层间绝缘层，设置在下绝缘层上；
多个中间互连件，设置在层间绝缘层中；
多个中间插塞，设置在层间绝缘层中并且设置在所述多个中间互连件之间；
上绝缘层，设置在层间绝缘层上；
第一上插塞，设置在上绝缘层中并且连接到所述多个中间互连件中的一个中间互连件，所述一个中间互连件具有第一厚度；
第一上互连件，在第一上插塞上设置在上绝缘层中并且具有第二厚度，其中，第二厚度大于第一厚度；
第二上插塞，设置在上绝缘层中并且设置在第一上互连件上；
第二上互连件，在第二上插塞上设置在上绝缘层中并且具有第三厚度，其中，第三厚度大于第一厚度；
凸块，设置在上绝缘层上，凸块延伸到上绝缘层中并且接触第二上互连件；以及
贯穿电极，延伸到基底中并且连接到所述多个中间互连件，
其中，第三厚度在第一厚度的2倍至100倍的范围内，并且
其中，第二上互连件包括与第二上插塞的材料不同的材料。
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