CN112530279B - Display device - Google Patents
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- CN112530279B CN112530279B CN202011261094.XA CN202011261094A CN112530279B CN 112530279 B CN112530279 B CN 112530279B CN 202011261094 A CN202011261094 A CN 202011261094A CN 112530279 B CN112530279 B CN 112530279B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
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- Theoretical Computer Science (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract
A display device comprises a substrate, a pixel array, a first drive circuit, a second drive circuit, a plurality of first connecting lines, a plurality of second connecting lines and a plurality of signal lines. The substrate has a front surface, a back surface and a side surface. The side surface is connected with the front surface and the back surface. The pixel array is configured on the front surface of the substrate. The first driving circuit is electrically connected with the pixel array on the front surface of the substrate. The second driving circuit is disposed on the front surface of the substrate and electrically connected to the pixel array. The first connecting line is arranged on the side surface of the substrate and is electrically connected with the first driving circuit. The second connecting line is arranged on the side surface of the substrate and is electrically connected with the second driving circuit. The signal line is arranged on the back of the substrate. Two ends of each signal line are respectively connected with a corresponding one of the first connecting lines and a corresponding one of the second connecting lines.
Description
Technical Field
The present invention relates to a display device, and more particularly, to a display device.
Background
In recent years, in order to maximize the screen size, a display panel with a narrow bezel is widely used in various devices. In order to realize a large-sized display device, the concept and application of the tiled multi-panel display panel are gradually emerging. However, when a plurality of display panels are spliced into a large display device, the frame width of the display panels often causes discontinuity of a display image at a boundary between adjacent display panels.
Gate-Driver-on-Array (GOA) circuits are one of the technologies for implementing narrow frames. However, when this technique is adopted, the signal lines matched with the technique cannot be reduced to be too small in line width or line distance, otherwise, the problems of overheating and resistance capacitance delay (RC delay) are caused.
Disclosure of Invention
The invention provides a display device, which can improve the problems of overheating and resistance-capacitance delay so as to improve the effect of a narrow frame.
The display device of the invention comprises a substrate, a pixel array, a first drive circuit, a second drive circuit, a plurality of first connecting wires, a plurality of second connecting wires and a plurality of signal wires. The substrate has a front surface, a back surface and a side surface. The side surface connects the front surface and the back surface. The pixel array is arranged on the front surface of the substrate. The first driving circuit is electrically connected with the pixel array on the front surface of the substrate. The second driving circuit is disposed on the front surface of the substrate and electrically connected to the pixel array. The first connecting line is arranged on the side surface of the substrate and electrically connected with the first driving circuit. The second connecting line is arranged on the side surface of the substrate and electrically connected with the second driving circuit. The signal line is arranged on the back surface of the substrate. Two ends of each signal line are respectively connected with a corresponding one of the first connecting lines and a corresponding one of the second connecting lines.
In an embodiment of the invention, the second driving circuit is a gate driving circuit.
In an embodiment of the invention, the second driving circuit includes a plurality of gate driving sub-circuits. Each gate driving sub-circuit is used for generating a gate driving signal. Each gate driving sub-circuit comprises a pull-up control circuit, a pull-up circuit, a pull-down control circuit and a pull-down circuit. The pull-up control circuit is used for receiving a start signal. The pull-up circuit is coupled to the output end of the pull-up control circuit and is used for generating a grid driving signal. The pull-down control circuit is coupled to the output end of the pull-up control circuit. The pull-down circuit is coupled with the output end of the pull-down control circuit and is coupled with the input end of the pull-up circuit.
In an embodiment of the invention, the pull-down control circuit is further configured to receive a low-frequency signal, and the pull-up control circuit is further configured to receive a high-frequency signal.
In an embodiment of the invention, the first driving circuit includes a source driving circuit and a timing control circuit.
In an embodiment of the invention, the source driving circuit is a chip on film.
In an embodiment of the invention, the first driving circuit includes a plurality of first pads disposed on an edge of the front surface of the substrate. The first connecting line is connected with the first connecting pad.
In an embodiment of the invention, the second driving circuit includes a plurality of second pads disposed at an edge of the front surface of the substrate. The second connecting line is connected with the second connecting pad.
In an embodiment of the present invention, the signal lines include a high frequency signal line, a low frequency signal line and a ground line.
In an embodiment of the invention, the signal lines further include a common signal line.
In an embodiment of the invention, the display device further includes a black matrix disposed on the front surface of the substrate. The orthographic projection of the black matrix on the front surface covers the orthographic projection of the signal line on the front surface.
In an embodiment of the invention, an orthogonal projection of the pixel array on the front surface at least partially overlaps an orthogonal projection of the signal line on the front surface.
Based on the above, in the display device of the invention, since the signal lines are disposed on the back surface of the substrate, the effect of the narrow frame can be further enhanced, and the display performance can also be enhanced.
The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.
Drawings
Fig. 1 is a front view of a display device according to an embodiment of the invention.
Fig. 2 is a rear view schematic diagram of the display device of fig. 1.
Fig. 3 is a schematic cross-sectional view of the display device of fig. 1 at the location of a first connection line.
Fig. 4 is a block diagram of a second driving circuit of the display device of fig. 1.
FIG. 5 is a block diagram of a second driving circuit of a display device according to another embodiment of the invention.
Fig. 6 is a schematic rear view of a display device according to still another embodiment of the invention.
Fig. 7 is a schematic partial front view of a display device according to yet another embodiment of the invention.
Wherein, the reference numbers:
100 display device
110 base plate
112 front side
114 back side
116 side surface
120 pixel array
130 first drive circuit
132 source electrode driving circuit
132A Flexible Circuit Board
134 timing control circuit
136 printed circuit board
138 third connecting line
140 second drive circuit
140A gate drive sub-circuit
142 pull-up control circuit
144 pull-up circuit
146 pull-down control circuit
148 pull-down circuit
150 first connecting line
160 second connecting line
170. 270 signal line
172 high frequency signal line
174 low frequency signal line
176 ground wire
180 black matrix
272 common signal line
P10 first pad
P20: second pad
S12 Gate drive Signal
ST start signal
LC low frequency signal
HC high frequency signal
Detailed Description
The invention will be described in detail with reference to the following drawings, which are provided for illustration purposes and the like:
fig. 1 is a schematic diagram of a display device according to an embodiment of the invention. Fig. 2 is a rear view schematic diagram of the display device of fig. 1. Referring to fig. 1 and fig. 2, the display device 100 of the present embodiment includes a substrate 110, a pixel array 120, a first driving circuit 130, a second driving circuit 140, a plurality of first connecting lines 150, a plurality of second connecting lines 160, and a plurality of signal lines 170. The substrate 110 has a front surface 112, a back surface 114 and a side surface 116. In other words, the front surface 112 and the back surface 114 are two opposite main surfaces of the substrate 110, and the surfaces surrounding the entire periphery of the substrate are collectively referred to as the side surfaces 116, so that the side surfaces 116 may be a curved surface or may be formed by a plurality of flat surfaces and/or curved surfaces. The pixel array 120 is disposed on the front surface 112 of the substrate 110. The first driving circuit 130 is electrically connected to the pixel array 120 on the front surface 112 of the substrate 110. In other words, the connection point of the first driving circuit 130 and the pixel array 120 is located on the front surface 112 of the substrate 110. The second driving circuit 130 is disposed on the front surface 112 of the substrate 110 and electrically connected to the pixel array 120. The signal line 170 is disposed on the back surface 114 of the substrate 110.
Fig. 3 is a schematic cross-sectional view of the display device of fig. 1 at the location of a first connection line. Referring to fig. 1 and 3, the side surface 116 connects the front surface 112 and the back surface 114. The first connecting line 150 is disposed on the side 116 of the substrate 110 and electrically connected to the first driving circuit 130. The second connecting wires 160 are disposed on the side 116 of the substrate 110 and electrically connected to the second driving circuits 140. As shown in fig. 3, in the present embodiment, the first driving circuit 130 extends to the edge of the front surface 112 of the substrate 110, and the first connecting line 150 is disposed on the side surface 116 of the substrate 110 and extends to and contacts the first driving circuit 130. In other embodiments, the first connection line 150 may also extend from the side 116 of the substrate 110 to the front surface 112 of the substrate 110, thereby covering a portion of the first driving circuit 130 extending to an edge of the front surface 112 of the substrate 110. The present invention does not limit the contact manner between the first connection line 150 and the first driving circuit 130, as long as the first driving circuit 130 on the front surface 112 of the substrate 110 and the first connection line 150 on the side surface 116 of the substrate 110 can contact each other. Although the contact manner between the second connection line 160 and the second driving circuit 140 is not illustrated, the contact manner is comparable to the contact manner between the first connection line 150 and the first driving circuit 130.
Referring to fig. 2 and 3, two ends of each signal line 170 are respectively connected to a corresponding first connection line 150 and a corresponding second connection line 160. The signal line 170 is not limited to a single line with two ends, and may be any other type of signal line 170 with at least two ends. As shown in fig. 3, in the present embodiment, the signal line 170 extends to the edge of the back surface 114 of the substrate 110, and the first connecting line 150 is disposed on the side surface 116 of the substrate 110 and extends to and contacts the signal line 170. In other embodiments, the first connecting line 150 may also extend from the side surface 116 of the substrate 110 to the back surface 114 of the substrate 110, thereby covering a portion of the signal line 170 extending to the edge of the back surface 114 of the substrate 110. The present invention does not limit the contact manner between the first connecting lines 150 and the signal lines 170, as long as the signal lines 170 on the back surface 114 of the substrate 110 and the first connecting lines 150 on the side surface 116 of the substrate 110 can contact each other. Although the contact between the second connecting line 160 and the signal line 170 is not illustrated, the contact between the second connecting line 160 and the signal line 170 is comparable to that between the first connecting line 150 and the signal line 170.
In the display device 100 of the embodiment, the signal line 170 is disposed on the back surface 114 of the substrate 110, and the first driving circuit 130 and the second driving circuit 140 are connected by the first connecting line 150 and the second connecting line 160 located on the side surface 116 of the substrate 110. Therefore, the area for disposing the signal lines 170 does not need to be reserved on the front surface 112 of the substrate 110, and a better narrow frame effect can be achieved. Moreover, the back surface 114 of the substrate 110 has a larger area for the signal lines 170 to be routed, and the line width and the line distance of the signal lines 170 can be increased, thereby greatly improving the phenomena of heat concentration and RC delay.
In addition, in the embodiment, the back surface 114 of the substrate 110 can be formed with only the dielectric layer and the conductive layer required by the signal line 170, and the process is relatively simple. On the other hand, although the second driving circuit 140 with a complicated process is formed on the front surface 112 of the substrate 110, the pixel array 120 with a complicated process is originally required to be formed on the front surface 112 of the substrate 110, so that the complexity of the process is not increased as a whole.
Referring to fig. 1 again, in the present embodiment, the first driving circuit 130 includes a source driving circuit 132 and a timing control circuit 134. The source driving circuit 132 is electrically connected to the pixel array 120 for providing the pixel array 120 with the image signal required for displaying. In addition, the timing control circuit 134 is electrically connected to the source driving circuit 132 to control the driving timing of the source driving circuit 132. In the embodiment, the source driving circuit 132 is a Chip On Film (COF), and the timing control circuit 134 is disposed on a printed circuit board 136, for example, but the invention is not limited thereto. The source driving circuit 132 is electrically connected to the pixel array 120 on the front surface 112 of the substrate 110 through a flexible circuit board 132A, for example, and the source driving circuit 132 is also electrically connected to the timing control circuit 134 through the flexible circuit board 132A and a printed circuit board 136. In addition, the first driving circuit 130 further includes a third connecting line 138 disposed on the front surface 112 of the substrate 110. The first connecting line 150 is electrically connected to the timing control circuit 134 sequentially through the third connecting line 138, the flexible circuit board 132A and the printed circuit board 136.
In an embodiment not shown, the source driving circuit may also be a Chip On Film (COF), but the invention is not limited thereto. At this time, the chip-type source driving circuit is electrically connected to the pixel array and the flexible circuit board on the front surface of the substrate, and is electrically connected to the timing control circuit through the flexible circuit board.
Referring to fig. 1 again, the first driving circuit 130 of the present embodiment may include a plurality of first pads P10 disposed at the edge of the front surface 112 of the substrate 110. The first connection line 150 is connected to the first pad P10. The second driving circuit 140 of the present embodiment includes a plurality of second pads P20 disposed on the edge of the front surface 112 of the substrate 110. The second connection line 160 is connected to the second pad P20. For example, the first pads P10 are located at the edge of the upper side of the front surface 112 of the substrate 110 in fig. 1, and the second pads P20 are located at the edges of the left and right sides of the front surface 112 of the substrate 110 in fig. 1, but the invention is not limited thereto. Although the first driving circuit 130 and the second driving circuit 140 are named as pads for connecting the first connecting line 150 and the second connecting line 160, it does not mean that the first pad P10 and the second pad P20 have to be different from the adjacent portions in structure, size, shape or other aspects, and may refer to only the region for connecting the first connecting line 150 and the second connecting line 160.
Referring to fig. 2 again, the signal line 170 of the present embodiment may include a high frequency signal line 172, a low frequency signal line 174 and a ground line 176, but the invention is not limited thereto.
Fig. 4 is a block diagram of a second driving circuit of the display device of fig. 1. Referring to fig. 1 and fig. 4, the second driving circuit 140 of the present embodiment is, for example, a gate driving circuit. The second driving circuit 140 of the present embodiment includes, for example, a plurality of gate driving sub-circuits 140A. Each gate driving sub-circuit 140A is configured to generate a gate driving signal S12. Each gate driver sub-circuit 140A includes a pull-up control circuit 142, a pull-up circuit 144, a pull-down control circuit 146, and a pull-down circuit 148, but the invention is not limited thereto. The pull-up control circuit 142 is used for receiving a start signal ST. The pull-up circuit 144 is coupled to the output terminal of the pull-up control circuit 142 for generating the gate driving signal S12. The pull-down control circuit 146 is coupled to the output of the pull-up control circuit 142. The pull-down circuit 148 is coupled to the output of the pull-down control circuit 146 and to the input of the pull-up circuit 144.
FIG. 5 is a block diagram of a second driving circuit of a display device according to another embodiment of the invention. Referring to fig. 5, the embodiment is similar to the embodiment of fig. 4, and only the differences therebetween are explained herein, and the rest of the similarities are not repeated herein. In the present embodiment, the pull-down control circuit 146 is further configured to receive a low-frequency signal LC, and the pull-up control circuit 144 is further configured to receive a high-frequency signal HC.
Fig. 6 is a schematic rear view of a display device according to still another embodiment of the invention. Referring to fig. 6, the present embodiment is similar to the embodiment of fig. 2, and only the differences therebetween are described herein, and the remaining similarities are not repeated herein. In the present embodiment, the signal line 270 further includes a common signal line 272. Therefore, the area for disposing the common signal line 272 on the front surface 112 of the substrate 110 does not need to be reserved, and a better narrow frame effect can be achieved.
Fig. 7 is a partial front view schematically illustrating a display device according to yet another embodiment of the present invention. The solution described here can be applied to the previous embodiments and other embodiments consistent with the present invention, and will be described below with reference to the embodiment applied to fig. 1. Referring to fig. 1 and 7, the display device 100 further includes a black matrix 180 disposed on the front surface 112 of the substrate 110. In fig. 1, the black matrix 180 is not shown to clearly show the rest of the elements of the embodiment. Although some components are omitted in fig. 7, although the signal line 170 is shown in fig. 7, it is only used to indicate the relative position of the signal line 170, and the signal line 170 is not located on the front surface 112 of the substrate 110. The orthographic projection of the black matrix 180 on the front surface 112 covers the orthographic projection of the signal line 170 on the front surface 112. In other words, when viewed from the front surface 112 of the substrate 110, the signal lines 170 are substantially not visible because they are shielded by the black matrix 180. With this design, the signal line 170 can be prevented from causing a decrease in the aperture ratio of the display device 100. In the present embodiment, the display device 100 may be a liquid crystal display device, but the display device of the present invention may also be a light emitting diode array display device or other display devices. In addition, in the present embodiment, the orthographic projection of the pixel array 120 on the front surface 112 at least partially overlaps the orthographic projection of the signal line 170 on the front surface 112. In some types of display devices, the black matrix 180 may not be disposed or is not required to be disposed, but the orthographic projection of the pixel array 120 on the front surface 112 is at least partially overlapped with the orthographic projection of the signal line 170 on the front surface 112, so that the signal line 170 has a larger layout space, which is helpful for improving the phenomena of heat concentration and rc delay.
In summary, in the display device of the present invention, the signal lines are moved to the back surface of the substrate, which is helpful to further achieve the purpose of narrow frame. Meanwhile, the signal lines have larger wiring space on the back surface of the substrate, so that the phenomena of heat concentration and resistance-capacitance delay are favorably improved, and the display performance can be improved.
The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (12)
1. A display device, comprising:
a substrate having a front surface, a back surface, a first side surface and a second side surface, wherein the first side surface and the second side surface connect the front surface and the back surface;
a pixel array disposed on the front surface of the substrate;
a first driving circuit electrically connected to the pixel array on the front surface of the substrate;
a second driving circuit disposed on the front surface of the substrate and electrically connected to the pixel array;
a plurality of first connecting lines configured on the first side surface of the substrate and electrically connected with the first driving circuit;
a plurality of second connecting wires configured on the second side surface of the substrate and electrically connected with the second driving circuit; and
a plurality of signal lines disposed on the back surface of the substrate, wherein two ends of each signal line are respectively connected to a corresponding one of the first connecting lines and a corresponding one of the second connecting lines;
wherein, the first side face and the second side face form an included angle.
2. The display device according to claim 1, wherein the second driving circuit is a gate driving circuit.
3. The display device of claim 2, wherein the second driving circuit comprises a plurality of gate driving sub-circuits, each gate driving sub-circuit for generating a gate driving signal, each gate driving sub-circuit comprising:
a pull-up control circuit for receiving a start signal;
a pull-up circuit coupled to the output terminal of the pull-up control circuit for generating the gate driving signal;
a pull-down control circuit coupled to the output terminal of the pull-up control circuit; and
and the pull-down circuit is coupled with the output end of the pull-down control circuit and is coupled with the input end of the pull-up circuit.
4. The display device of claim 3, wherein the pull-down control circuit is further configured to receive a low frequency signal and the pull-up control circuit is further configured to receive a high frequency signal.
5. The display device according to claim 1, wherein the first driving circuit comprises a source driving circuit and a timing control circuit.
6. The display device according to claim 5, wherein the source driving circuit is a flip-chip.
7. The display device according to claim 1, wherein the first driving circuit comprises a plurality of first pads disposed at an edge of the front surface of the substrate, wherein the first connecting lines are connected to the first pads.
8. The display device according to claim 1, wherein the second driving circuit comprises a plurality of second pads disposed at an edge of the front surface of the substrate, wherein the second connecting wires are connected to the second pads.
9. The display device according to claim 1, wherein the signal lines include a high frequency signal line, a low frequency signal line, and a ground line.
10. The display device according to claim 9, wherein the signal lines further comprise common signal lines.
11. The display device of claim 1, further comprising a black matrix disposed on the front surface of the substrate, wherein an orthogonal projection of the black matrix on the front surface covers an orthogonal projection of the signal lines on the front surface.
12. The display device of claim 1, wherein an orthographic projection of the pixel array on the front surface at least partially overlaps with an orthographic projection of the signal lines on the front surface.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW109116866 | 2020-05-21 | ||
| TW109116866A TWI742681B (en) | 2020-05-21 | 2020-05-21 | Display device |
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| Publication Number | Publication Date |
|---|---|
| CN112530279A CN112530279A (en) | 2021-03-19 |
| CN112530279B true CN112530279B (en) | 2023-03-14 |
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| CN202011261094.XA Active CN112530279B (en) | 2020-05-21 | 2020-11-12 | Display device |
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| CN (1) | CN112530279B (en) |
| TW (1) | TWI742681B (en) |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10104651A (en) * | 1996-09-27 | 1998-04-24 | Toshiba Corp | Display device |
| JP2000098417A (en) * | 1998-09-28 | 2000-04-07 | Sony Corp | Liquid crystal display device |
| KR101137852B1 (en) * | 2004-05-31 | 2012-04-20 | 엘지디스플레이 주식회사 | Liquid Crystal Display Built-in Driving Circuit |
| CN103217845B (en) * | 2013-04-22 | 2015-07-15 | 京东方科技集团股份有限公司 | Lower substrate, manufacturing method thereof, liquid crystal display panel and liquid crystal displayer |
| TWI527019B (en) * | 2014-06-25 | 2016-03-21 | 友達光電股份有限公司 | Timing signal generation circuit and precharging/discharging method thereof |
| CN104992956B (en) * | 2015-05-15 | 2018-11-09 | 深圳市华星光电技术有限公司 | Frame-free displaying device and preparation method thereof |
| CN106445230A (en) * | 2016-09-12 | 2017-02-22 | 京东方科技集团股份有限公司 | Touch panel and manufacturing method thereof and display device |
| CN106681067B (en) * | 2016-12-20 | 2019-01-22 | 深圳市华星光电技术有限公司 | Display device |
| CN107833978B (en) * | 2017-10-31 | 2021-12-10 | 昆山国显光电有限公司 | Display device |
| CN107799087B (en) * | 2017-11-24 | 2020-06-05 | 深圳市华星光电技术有限公司 | GOA circuit and display device |
| CN207764515U (en) * | 2018-01-03 | 2018-08-24 | 京东方科技集团股份有限公司 | A kind of display panel and display device |
| CN108447891B (en) * | 2018-05-07 | 2021-03-16 | 京东方科技集团股份有限公司 | Display panel manufacturing method, display panel and pad printing device |
| KR102151099B1 (en) * | 2018-07-04 | 2020-09-02 | 삼성전자주식회사 | Display panel and large format display apparatus using the same |
| CN110211973B (en) * | 2019-06-12 | 2021-08-27 | 京东方科技集团股份有限公司 | Display panel and manufacturing method |
| CN110910774A (en) * | 2019-11-04 | 2020-03-24 | 深圳市华星光电半导体显示技术有限公司 | Display panel, manufacturing method and spliced display panel |
| CN111081720B (en) * | 2019-12-30 | 2022-02-25 | 上海天马微电子有限公司 | Display panel and display device |
-
2020
- 2020-05-21 TW TW109116866A patent/TWI742681B/en active
- 2020-11-12 CN CN202011261094.XA patent/CN112530279B/en active Active
Also Published As
| Publication number | Publication date |
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| TWI742681B (en) | 2021-10-11 |
| CN112530279A (en) | 2021-03-19 |
| TW202144874A (en) | 2021-12-01 |
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