CN114677987B

CN114677987B - Display panel and display device

Info

Publication number: CN114677987B
Application number: CN202210447564.4A
Authority: CN
Inventors: 邓祁; 王建; 张勇; 杨智超; 乜玲芳; 王德生; 郭赞武; 郝龙虎
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Optoelectronics Technology Co Ltd
Priority date: 2022-04-26
Filing date: 2022-04-26
Publication date: 2023-07-07
Anticipated expiration: 2042-04-26
Also published as: CN114677987A

Abstract

The application discloses a display panel and a display device, comprising a display area and a fan-out area, wherein the fan-out area comprises a first fan-out wiring area and a second fan-out wiring area arranged on at least one side of the first fan-out wiring area, a plurality of signal wires are arranged on the first fan-out wiring area, and the signal wires are used for being connected with the display area and providing driving signals for the display area; the second fan-out wiring area is provided with a plurality of auxiliary wirings, the auxiliary wirings are electrically connected with the first common electrode to form resistance compensation for the signal output end of the drive IC and/or the auxiliary wirings and the second common electrode to form capacitance compensation for the signal output end of the drive IC.

Description

Display panel and display device

Technical Field

The present disclosure relates generally to the field of display technologies, and in particular, to a display panel and a display device.

Background

With further improvement of display requirements, pixel resolution of the display device is larger and larger, correspondingly, data lines connected with the pixels are larger and larger, and the number of upper output terminals of corresponding ICs is larger and larger to match the number of data lines in the display area.

When the IC outputs, the panel load value can be stably output under the condition that the normal panel has RC load, and if the RC load value on the display panel drifts, the signal output end can generate the phenomenon of swing oscillation; when the screen resolution is smaller than the minimum resolution that the IC can support, the redundant IC input end still generates output behaviors on the terminal, and the input end on the panel can cause the phenomenon of swing oscillation at the signal output end under the condition of no load or insufficient load, and the phenomenon of swing oscillation can cause redundant power consumption.

Disclosure of Invention

In view of the above-mentioned drawbacks or shortcomings in the prior art, it is desirable to provide a display panel and a display device, which can reduce the swing oscillation phenomenon of the signal output end, reduce power consumption, and improve the display effect.

In a first aspect, the present application provides a display panel comprising a display area and a fan-out area, the fan-out area comprising a first fan-out routing area and a second fan-out routing area disposed on at least one side of the first fan-out routing area, wherein,

the first fan-out wiring area is provided with a plurality of signal wirings, and the signal wirings are used for being connected with the display area and providing driving signals for the display area;

the second fan-out wiring area is provided with a plurality of auxiliary wirings, the auxiliary wirings are electrically connected with the first common electrode to form resistance compensation for the signal output end of the drive IC and/or the auxiliary wirings and the second common electrode to form capacitance compensation for the signal output end of the drive IC.

Optionally, the fan-out area includes a first input pin area near one side of the display area and a second input pin area near one side of the driving IC; the second input pin area comprises a second signal input terminal connected with the signal wiring and a suspension input terminal connected with the auxiliary wiring.

Optionally, the display area includes a plurality of data lines extending along a first direction, and the first input pin area includes first signal input terminals in one-to-one correspondence with the data lines.

Optionally, the signal output end on the driving IC is configured to output a data driving signal, where the signal output end includes a first output terminal and a second output terminal, the first output terminal is bonded with the signal input terminal, and the second output terminal is bonded with the suspended input terminal.

Optionally, the first common electrode is disposed at a side of the second fan-out wiring region near the display region.

Optionally, the fan-out area includes a substrate base plate and the second common electrode disposed on the substrate base plate, where a front projection of the second common electrode on the substrate base plate at least partially overlaps a front projection of the auxiliary trace on the substrate base plate, and the second common electrode is used to form capacitance compensation for a signal output end of the driving IC with the auxiliary trace and/or the first common electrode. Forming capacitance compensation for signal output terminal of driving IC

Optionally, the orthographic projection of the first common electrode on the substrate at least partially overlaps with the orthographic projection of the second common electrode on the substrate.

Optionally, the fan-out region includes a source drain metal layer disposed on the substrate, and the source drain metal layer is used to form the plurality of signal traces and the plurality of auxiliary traces.

Optionally, the source-drain metal layer is overlapped with the first common electrode in the second fan-out area, so as to realize electrical connection between the first common electrode and the auxiliary wiring.

In a second aspect, the present application provides a display device comprising a display panel as described in any one of the above.

The technical scheme provided by the embodiment of the application can comprise the following beneficial effects:

the display panel provided by the embodiment of the application carries out load compensation on the suspended input terminal which is provided with signal output and is not used by the display panel on the drive IC through the auxiliary wiring, so that swing oscillation of the signal output end of the drive IC is prevented, power consumption of the drive IC is reduced, and display effect is improved.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the following drawings, in which:

fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present application;

FIG. 3 is an enlarged schematic view of the position P1 in FIG. 2;

FIG. 4 is an enlarged schematic view of the position P2 in FIG. 2;

FIG. 5 is an enlarged schematic view of the position P3 in FIG. 2;

FIG. 6 is an enlarged schematic view of the position P4 in FIG. 2;

fig. 7 is a schematic structural diagram of a driving IC according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of another display device according to an embodiment of the present application;

FIG. 9 is a schematic cross-sectional view of the position P2 of FIG. 2;

fig. 10 is a schematic structural diagram of an array substrate according to an embodiment of the present application.

Detailed Description

The present application is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be noted that, for convenience of description, only the portions related to the invention are shown in the drawings.

It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

As shown in fig. 1, the display device mainly includes a display panel and a driving IC. In practice, since display is performed by combining the driving of the source driver circuit and the gate driver circuit, a data connection portion (which may be referred to as Pad, pin, terminal, pad, or the like) for connecting to the source driver circuit and a gate connection portion (which may be referred to as Pad, pin, terminal, pad, or the like) for connecting to the gate driver circuit are directly formed at the time of manufacturing the array substrate; and the array substrate is also provided with a data line wiring and a grid line wiring, so that the data line is connected with the data connection part through the data line wiring, and the grid line is connected with the grid connection part through the grid line wiring.

When the screen resolution of the display panel is smaller than the minimum resolution that the IC can support, for example, when the screen resolution is 340×800, the number of output pins of the required data driving signals is 1020, and the number of output pins of the minimum resolution data driving signals that the IC can support is 1080, that is, the output pins of 41 data driving signals are redundant (suspended) and not used, but there is still signal output on the 41 suspended pins, and at this time, RC (Resistor/Capacitor) load value drift occurs. Therefore, under the condition that the output pin is not loaded or the load value is insufficient, the phenomenon of swing oscillation occurs at the signal output end, and the phenomenon of swing oscillation can cause redundant power consumption.

According to the application, the simulation situation which can be ensured at the IC end is that the behavior of converging the oscillation can be seen under ideal conditions, but the oscillation can occur when the load required by a single signal wiring is not met in practical IC application, the smaller the resistor R is, the smaller the capacitor C is, the larger the oscillation amplitude is, the longer the convergence time is, and the larger the redundant power consumption is.

In order to solve the problem of oscillation risk caused by an IC (integrated circuit), the application provides a wiring design for RC (resistance-capacitance) compensation at a panel display panel end, so that the oscillation risk of an IC suspended output end is reduced, and meanwhile, the redundant power consumption caused by oscillation is reduced.

As shown in fig. 2-6, the present application provides a display panel, which includes a display area AA and a fan-out area, wherein the fan-out area includes a first fan-out wiring area D1 and a second fan-out wiring area D2 disposed at least on one side of the first fan-out wiring area D1, wherein,

a plurality of signal wires 10 are arranged on the first fan-out wire area D1, and the signal wires 10 are used for being connected with the display area AA and providing driving signals for the display area AA;

the second fanout wiring area D2 is provided with a plurality of auxiliary wirings 20, and the auxiliary wirings 20 are electrically connected with the first common electrode 80 to form resistance compensation for the signal output end of the driving IC and/or the auxiliary wirings 20 and the second common electrode 90 form capacitance compensation for the signal output end of the driving IC.

In the embodiment of the application, the display area AA includes a plurality of data lines extending in a first direction and a plurality of gate lines extending in a second direction, and the gate lines and the data lines cross to define a plurality of pixel regions.

It should be noted that, the signal trace 10 may be a gate trace or a data trace, and in the implementation of the present application, the data trace is exemplified. In this embodiment of the present application, the driving IC may be a separate touch driving IC or a separate data driving IC, which is not limited in this embodiment, and in different embodiments, different setting manners may be adopted.

Optionally, the fan-out area includes a first input pin area 30 near a side of the display area AA and a second input pin area 40 near a side of the driving IC; the first input pin area 30 includes first signal input terminals 50 in one-to-one correspondence with the data lines. The second input pin area 40 comprises a second signal input terminal 41 connected to the signal trace 10 and a floating input terminal 42 connected to the auxiliary trace 20.

In this embodiment, the first end of the signal trace 10 is connected to the data line in the display area AA through the first signal input terminal 50, the second end is connected to the second signal input terminal 41, and the second signal input terminal 41 is used for bonding with the driving IC. The first end of the auxiliary trace 20 is connected to the first common electrode 80, and the second end is connected to the suspended input terminal 42 for bonding with the driving IC.

Correspondingly, the signal output end on the driving IC is used for outputting a data driving signal, the signal output end includes a first output terminal 71 and a second output terminal 72, the first output terminal 71 is bonded with the signal input terminal, and the second output terminal 72 is bonded with the suspended input terminal 42.

Note that, in the embodiment of the present application, the connection method between the display panel and the driving IC is not limited. For example, the display panel and the driving IC may be connected by COG Bonding (Bonding) via ACF (Anisotropic Conductive adhesive Film, anisotropic conductive film), and the PCB and the glass panel may be connected by FPC (Flexible Printed Circuit, flexible circuit board).

The display panel may also be realized by COF (Chip On Film) technology to achieve ultra-narrow frames. The COF technology is a die-attach technology for fixing a driver IC to a flexible wiring board. By introducing the technology into the display device, the size of a circuit area (also called a PAD area) of the display device can be reduced, so that an ultra-narrow frame is realized.

As shown in fig. 7, in the embodiment of the present application, the signal output end of the driving IC includes a first output pin area, a second output pin area, a third output pin area, and a fourth output pin area that are disposed from the center to two sides, where the number of the second output pin area, the third output pin area, and the fourth output pin area is two, and are disposed on two sides of the first output pin area respectively.

The first output pin area is provided with a first output terminal 71, the second output pin area is provided with a second output terminal 72, the third output pin area is provided with a third output terminal 73, and the fourth output pin area is provided with a fourth output terminal 74.

The terminals on the first output pin area provide driving signals to the data lines of the display panel through the signal lines by the driving ICs, and the number of the first output terminals 71 in the first output pin area is equal to the number of the data lines of the display area AA and the number of the first signal input terminals 50 of the first input pin area 30 and the number of the second signal input terminals 41 of the second input pin area 40 in the embodiment of the present application.

The terminals on the second output pin area provide output signals through the driver IC, but the signals are not used by the display area AA, and the number of second output terminals 72 in the second output pin area is equal to the number of auxiliary traces 20 and the number of floating signal terminals of the second input pin area 40 in the embodiment of the present application.

For example, when the screen resolution is 340×800, the number of output pins of the required data driving signal is 1020, and the number of output pins of the minimum resolution data driving signal that the IC can support is 1080, the number of first signal output terminals on the first output pin area is 1020, and the number of second signal output terminals on the second output pin area is 41.

The driver ICs on the third output terminals 73 in the third output pin zone do not provide output signals. The third output terminal 73 is determined by the type and specification of the driving IC, and the third output terminal 73 does not need to output a signal with respect to the resolution of the display panel, and thus does not need to perform load compensation.

The fourth output pin area is used for being connected with a grid driving circuit of the display panel and used for providing grid driving signals for the display panel. In this embodiment, the gate driving circuit adopts a GOA (Gate On Array) circuit, and the fourth signal output terminal is connected to a GOA circuit, and the GOA circuit provides the gate driving signals to the plurality of gate lines extending in the second direction Y in the display area AA.

In this embodiment of the present application, the first direction and the second direction may be perpendicular to each other or may be near perpendicular to each other, which is not limited to specific directions of the first direction and the second direction in this application. The arrangement direction of the pixel columns is exemplified as a first direction, and the arrangement direction of the pixel rows is exemplified as a second direction. Of course, in other embodiments, the first direction and the second direction may be interchanged, the first direction may be an arrangement direction of the pixel rows, and the second direction may be an arrangement direction of the pixel columns.

It should be noted that, in the embodiment of the present application, the fan-out area is disposed at the lower frame of the display panel for exemplary illustration, but the embodiment of the present application is not limited thereto, and the fan-out area may be disposed at the upper frame, the left frame or the right frame of the display panel. In addition, in the embodiment of the present application, the total number of terminals on each pin area is not limited, and in different embodiments, different settings may be performed according to the device and the application scenario; the number of rows of terminals on each pin field may be adjusted depending on the device or application scenario. Two rows or 3-5 rows are possible.

In this embodiment of the present application, the first output pin area is set at the middle position of the driving IC, and the second output pin area is set to two parts, which are respectively located at two sides of the first output pin area, and each second output pin area is used for connecting with the auxiliary trace 20 corresponding to the compensation area on the second outgoing trace area D2, so as to avoid the problems of increasing the outgoing trace oblique angle and narrowing the line width while realizing the narrowing frame.

It is further noted that the display device according to the embodiment of the present application may further include a plurality of driving ICs, as shown in fig. 8. Each driving IC is connected with the display panel through a fan-out area, and each fan-out area may include a first fan-out wiring area D1 and a second fan-out wiring area D2, and may further include a first fan-out wiring area D1 and two second fan-out wiring areas D2 respectively located at one side of the first fan-out wiring area D1.

Of course, in the case of providing the two fan-out areas, the first output pin area and the second output pin area may be provided in each of the two fan-out areas; for example, for the source drive ICs (generally including a plurality), the source drive ICs may be disposed dispersedly in the two connection regions; each fan-out region may also be provided with a fourth output pin region, for example, for a gate drive circuit, a double-side driven GOA circuit may be employed; the present invention is not limited thereto, and the setting may be selected according to actual needs in practice.

The width and length of the different auxiliary tracks 20 may be determined by the output signal to be compensated. The shape of the auxiliary trace 20 in this application is generally the same as the shape of the data trace, and the trace pattern is similar. In some special routing modes, the routing mode can be determined according to the signal on the signal output end and the required load value. The load value of the auxiliary trace 20 is adjusted for different output signals by increasing the width of the trace, extending the length of the trace, etc.

Specifically, the auxiliary trace 20 may be a linear, a folded or a curved trace. When the auxiliary wire 20 is designed into a linear wire, the process design difficulty of the auxiliary wire 20 can be reduced, when the auxiliary wire 20 is designed into a folded wire or a curved wire, the extension length of the auxiliary wire 20 can be reduced, the wiring difficulty of the wire can be reduced, and the specific wire mode of the auxiliary wire 20 can be set according to actual needs without being limited in particular.

In this embodiment, the resistor may be provided to perform RC load compensation of the output terminal by using the conductive material of the auxiliary trace 20. In the embodiment of the present application, the materials of the signal trace 10 and the auxiliary trace 20 are not limited, and may be conductive. Such as but not limited to a metallic material. In application, the signal trace 10 and the auxiliary trace 20 may be disposed on a single layer, or may be disposed on the same layer as the conductive pattern on the substrate, for example, may be disposed on the same layer as the source/drain metal layer 6 and the gate metal layer 4.

In one embodiment of the present application, as shown in fig. 9, the fan-out area includes a first common electrode 80 disposed at a side of the second fan-out trace area D2 near the display area AA, and the auxiliary trace 20 is electrically connected to the first common electrode 80. The second common electrode 90 is configured to be connected to a VCOM signal, so as to form a capacitance with the auxiliary wiring 20 and/or the first common electrode layer 80, and perform capacitance compensation on the signal input terminal of the driving IC; one end of the auxiliary wiring 20 is connected to the signal output end of the driving IC, and the other end is electrically connected to the first common electrode 80 for resistance compensation, so as to prevent the swing oscillation.

Optionally, the fan-out area includes a substrate 1 and a second common electrode 90 disposed on the substrate 1, where a front projection of the second common electrode 90 on the substrate 1 at least partially overlaps a front projection of the auxiliary trace 20 and the first common electrode 80 on the substrate 1, and the second common electrode 90 is used to form capacitance compensation with the auxiliary trace 20 and the first common electrode 80 for a signal output terminal of the driving IC.

In this embodiment, a certain overlapping area exists between the second common electrode 90 and the auxiliary trace 20, so that a capacitance may be formed between the auxiliary trace 20 and the second common electrode 90, and thus the load on the auxiliary trace 20 may be increased.

It should be noted that, in the embodiment of the present application, the second common electrode 90 may be only located in the second fan-out routing area D2, and only provide load value compensation for the auxiliary routing 20, which is determined according to the load value on the data routing, and since the load value required for the first signal output terminal is provided by the data routing and the data routing on the display area AA, the load value is sufficient to provide stable output of the first signal output terminal on the driving IC, and the second common electrode 90 is not required to provide compensation.

In addition, the orthographic projection of the first common electrode 80 on the substrate 1 is at least partially overlapped with the orthographic projection of the second common electrode 90 on the substrate 1. By having a certain overlapping area between the first common electrode 80 and the second common electrode 90, a capacitance can be formed between the auxiliary trace 20 and the second common electrode 90, so that a load on the auxiliary trace 20 can be increased.

The shapes of the common electrodes are not limited in the embodiments of the present application, and in different embodiments, the first common electrode 80 and the second common electrode 90 may be planar electrodes, slit electrodes, or the like, and the slit shape may be oblique bars, zigzag shapes, X shapes, Y shapes, or the like. The shape of the common electrode and the shape of the common electrode can be selected according to the requirements according to the device and the application scene.

In this embodiment, as shown in fig. 10, the substrate is an array substrate, where the array substrate includes a substrate 1, an active layer 2, a gate insulating layer 3, a gate metal layer 4, an interlayer dielectric layer 5, a source drain metal layer 6, and a planarization layer 7 that are stacked.

Optionally, the fan-out area includes a source drain metal layer 6 disposed on the substrate 1, and the source drain metal layer 6 is used to form the plurality of signal traces 10 and the plurality of auxiliary traces 20. The auxiliary wiring 20 and the signal wiring 10 can be formed by the same conductive layer and the same working procedure with the source drain metal layer 6, the manufacturing process is simple, the cost is low, and the thickness of the array substrate is thin because no additional conductive layer is needed to be added for forming the auxiliary wiring 20 and the signal wiring 10. The first and second

common electrodes

80 and 90 may be ITO.

Optionally, the source-drain metal layer 6 and the first common electrode 80 overlap in the second fan-out area, and a via hole is disposed between the source-drain metal layer 6 and the first common electrode 80, so as to realize electrical connection between the first common electrode 80 and the auxiliary trace 20. The specific arrangement is not particularly limited herein.

Note that the second common electrode 90 and the first common electrode 80 may be disposed according to actual situations, for example, the second common electrode 90 may be disposed separately, or the first common electrode 80 may be disposed separately, or the second common electrode 90 and the first common electrode 80 may be disposed at the same time, and the specific manner of disposing is not specifically limited herein.

The present application provides a display device comprising a display panel as described in any one of the above. The display device may be: a liquid crystal panel, electronic paper, an Organic Light-Emitting Diode (OLED) panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and other products or components with display functions.

It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are merely for convenience in describing and simplifying the description based on the orientation or positional relationship shown in the drawings, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the invention.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

Unless defined otherwise, technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular implementations only and is not intended to be limiting of the invention. Terms such as "disposed" or the like as used herein may refer to either one element being directly attached to another element or one element being attached to another element through an intermediate member. Features described herein in one embodiment may be applied to another embodiment alone or in combination with other features unless the features are not applicable or otherwise indicated in the other embodiment.

The present invention has been described in terms of the above embodiments, but it should be understood that the above embodiments are for purposes of illustration and description only and are not intended to limit the invention to the embodiments described. Those skilled in the art will appreciate that many variations and modifications are possible in light of the teachings of the invention, which variations and modifications are within the scope of the invention as claimed.

Claims

1. The display panel is characterized by comprising a display area and a fan-out area, wherein the fan-out area comprises a first fan-out wiring area and a second fan-out wiring area arranged on at least one side of the first fan-out wiring area, a plurality of signal wires are arranged on the first fan-out wiring area, and the signal wires are used for being connected with the display area and providing driving signals for the display area;

a plurality of auxiliary wires are arranged on the second fan-out wire area, and the auxiliary wires are electrically connected with the first common electrode to form resistance compensation for the signal output end of the drive IC and/or form capacitance compensation with the second common electrode;

the first public electrode is arranged on one side of the second fan-out wiring area close to the display area, and the auxiliary wiring is electrically connected with the first public electrode;

the fan-out area comprises a substrate base plate, and the orthographic projection of the second common electrode on the substrate base plate at least partially overlaps with the orthographic projection of the auxiliary wiring on the substrate base plate;

the fan-out area comprises a second input pin area close to one side of the drive IC, and the second input pin area comprises a second signal input terminal connected with the signal wiring and a suspension input terminal connected with the auxiliary wiring.

2. The display panel of claim 1, wherein the fan-out region comprises a first input pin region proximate a side of the display region.

3. The display panel of claim 2, wherein the display area includes a plurality of data lines extending in a first direction, and the first input pin area includes first signal input terminals in one-to-one correspondence with the data lines.

4. The display panel of claim 2, wherein a signal output on the driver IC is configured to output a data driving signal, the signal output including a first output terminal and a second output terminal, the first output terminal being bonded to the signal input terminal, the second output terminal being bonded to the floating input terminal.

5. The display panel of claim 1, wherein the first common electrode is disposed on a side of the second fanout wiring region adjacent to the display region.

6. The display panel according to claim 1, wherein the second common electrode is disposed on the substrate base, the second common electrode further being used to form capacitance compensation for a signal output terminal of the driving IC with the first common electrode.

7. The display panel of claim 6, wherein an orthographic projection of the first common electrode on the substrate at least partially overlaps an orthographic projection of the second common electrode on the substrate.

8. The display panel of claim 5, wherein the fan-out region comprises a source drain metal layer disposed on a substrate base plate, the source drain metal layer being used to form the plurality of signal traces and the plurality of auxiliary traces.

9. The display panel of claim 8, wherein the source drain metal layer overlaps the first common electrode in the second routing region to electrically connect the first common electrode and the auxiliary routing.

10. A display device comprising a display panel as claimed in any one of claims 1-9.